| /llvm-project/llvm/test/CodeGen/AMDGPU/ |
| H A D | atomic_optimizations_pixelshader.ll | 279 ; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
281 ; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
283 ; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
285 ; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
287 ; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
289 ; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
334 ; GFX9-NEXT: v_add_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
336 ; GFX9-NEXT: v_add_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
338 ; GFX9-NEXT: v_add_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
340 ; GFX9-NEXT: v_add_u32_dpp v
[all...] |
| /llvm-project/llvm/test/MC/AMDGPU/ |
| H A D | gfx8_asm_vop2.s | 8160 v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 label
8163 v_add_u32_dpp v255, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 label
8166 v_add_u32_dpp v5, vcc, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 label
8169 v_add_u32_dpp v5, vcc, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 label
8172 v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 label
8175 v_add_u32_dpp v5, vcc, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0 label
8178 v_add_u32_dpp v5, vcc, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0 label
8181 v_add_u32_dpp v5, vcc, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0 label
8184 v_add_u32_dpp v5, vcc, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0 label
8187 v_add_u32_dpp v5, vcc, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0 label
[all …]
|
| H A D | gfx9_asm_vop2.s | 14447 v_add_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 label
14450 v_add_u32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 label
14453 v_add_u32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 label
14456 v_add_u32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 label
14459 v_add_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 label
14462 v_add_u32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0 label
14465 v_add_u32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0 label
14468 v_add_u32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0 label
14471 v_add_u32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0 label
14474 v_add_u32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0 label
[all …]
|
| H A D | gfx10_unsupported.s | 1073 v_add_u32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
1070 v_add_u32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 global() label
|
| H A D | gfx7_unsupported.s | 838 v_add_u32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 label
|
| /llvm-project/llvm/test/MC/Disassembler/AMDGPU/ |
| H A D | gfx8_vop2_dpp.txt | 1815 # CHECK: v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: […
1818 # CHECK: v_add_u32_dpp v255, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding:…
1821 # CHECK: v_add_u32_dpp v5, vcc, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding:…
1824 # CHECK: v_add_u32_dpp v5, vcc, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding:…
1827 # CHECK: v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 ; encoding: […
1830 # CHECK: v_add_u32_dpp v5, vcc, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04…
1833 # CHECK: v_add_u32_dpp v5, vcc, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa…
1836 # CHECK: v_add_u32_dpp v5, vcc, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x…
1839 # CHECK: v_add_u32_dpp v5, vcc, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x…
1842 # CHECK: v_add_u32_dpp v5, vcc, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04…
[all …]
|
| H A D | gfx9_vop2_dpp.txt | 3855 # CHECK: v_add_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,…
3858 # CHECK: v_add_u32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xf…
3861 # CHECK: v_add_u32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xf…
3864 # CHECK: v_add_u32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xf…
3867 # CHECK: v_add_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,…
3870 # CHECK: v_add_u32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a…
3873 # CHECK: v_add_u32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04…
3876 # CHECK: v_add_u32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x…
3879 # CHECK: v_add_u32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x…
3882 # CHECK: v_add_u32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a…
[all …]
|
| /llvm-project/llvm/docs/AMDGPU/ |
| H A D | AMDGPUAsmGFX8.rst | 883 …v_add_u32_dpp :ref:`vdst<amdgpu_synid_gfx8_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx8_vcc…
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| H A D | AMDGPUAsmGFX9.rst | 1074 …v_add_u32_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_g…
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| H A D | AMDGPUAsmGFX90a.rst | 984 …v_add_u32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid…
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| H A D | AMDGPUAsmGFX940.rst | 980 …v_add_u32_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid…
|