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Searched refs:v_add_i32 (Results 1 – 25 of 27) sorted by relevance

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/llvm-project/llvm/test/MC/AMDGPU/
H A Dgfx7_asm_vop2.s2883 v_add_i32 v5, vcc, v1, v2 label
2886 v_add_i32 v255, vcc, v1, v2 label
2889 v_add_i32 v5, vcc, v255, v2 label
2892 v_add_i32 v5, vcc, s1, v2 label
2895 v_add_i32 v5, vcc, s103, v2 label
2898 v_add_i32 v5, vcc, flat_scratch_lo, v2 label
2901 v_add_i32 v5, vcc, flat_scratch_hi, v2 label
2904 v_add_i32 v5, vcc, vcc_lo, v2 label
2907 v_add_i32 v5, vcc, vcc_hi, v2 label
2910 v_add_i32 v5, vcc, tba_lo, v2 label
[all …]
H A Dlds_direct-err.s74 v_add_i32 v0, v0, lds_direct label
77 v_add_i32 lds_direct, v0, v0 label
H A Dout-of-range-registers.s22 v_add_i32 v256, v0, v1 label
28 v_add_i32 v257, v0, v1 label
H A Dvop3-gfx9.s694 v_add_i32 v1, v2, v3 label
699 v_add_i32 v1, v2, v3 clamp label
H A Dgfx9_asm_vop3_e64.s16026 v_add_i32 v5, v1, v2 label
16029 v_add_i32 v255, v1, v2 label
16032 v_add_i32 v5, v255, v2 label
16035 v_add_i32 v5, s1, v2 label
16038 v_add_i32 v5, s101, v2 label
16041 v_add_i32 v5, flat_scratch_lo, v2 label
16044 v_add_i32 v5, flat_scratch_hi, v2 label
16047 v_add_i32 v5, vcc_lo, v2 label
16050 v_add_i32 v5, vcc_hi, v2 label
16053 v_add_i32 v5, ttmp15, v2 label
[all …]
H A Dvop2.s297 v_add_i32 v1, s[0:1], v2, v3
299 v_add_i32 v1, s[0:1], v2, v3 global() label
H A Dgfx8_unsupported.s760 v_add_i32 lds_direct, v0, v0 label
H A Dgfx10_unsupported.s1046 v_add_i32 lds_direct, v0, v0
1043 v_add_i32 lds_direct, v0, v0 global() label
/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dadd_i64.ll7 ; SI: v_add_i32
57 ; SI: v_add_i32
59 ; SI: v_add_i32
H A Dr600.add.ll80 ; FUNC-LABEL: {{^}}v_add_i32:
81 define amdgpu_kernel void @v_add_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
117 ; The v_addc_u32 and v_add_i32 instruction can't read SGPRs, because they
H A Dmove-addr64-rsrc-dead-subreg-writes.ll6 ; FIXME: We should be able to use the SGPR directly as src0 to v_add_i32
H A Dearly-if-convert.ll410 ; GCN: v_add_i32
411 ; GCN: v_add_i32
435 ; GCN: v_add_i32
436 ; GCN: v_add_i32
H A Dsplit-scalar-i64-add.ll39 ; SI: v_add_i32
H A Dsminmax.v2i16.ll
H A Dsaddsat.ll148 ; GFX9-NEXT: v_add_i32 v0, v0, v1 clamp
421 ; GFX9-NEXT: v_add_i32 v0, v0, v2 clamp
422 ; GFX9-NEXT: v_add_i32 v1, v1, v3 clamp
H A Dadd.ll753 define amdgpu_kernel void @v_add_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
754 ; GFX6-LABEL: v_add_i32:
775 ; GFX8-LABEL: v_add_i32:
795 ; GFX9-LABEL: v_add_i32:
809 ; GFX10-LABEL: v_add_i32:
823 ; GFX11-LABEL: v_add_i32:
839 ; GFX12-LABEL: v_add_i32:
1046 ; The v_addc_u32 and v_add_i32 instruction can't read SGPRs, because they
H A Dsi-triv-disjoint-mem-access.ll267 ; CI-DAG: v_add_i32
268 ; CI-DAG: v_add_i32
H A Dsaddo.ll182 ; GFX9-NEXT: v_add_i32 v1, s6, v1 clamp
293 ; GFX9-NEXT: v_add_i32 v3, v1, v2 clamp
656 ; GFX9-NEXT: v_add_i32 v1, v1, v3 clamp
658 ; GFX9-NEXT: v_add_i32 v0, v0, v2 clamp
H A Dscratch-simple.ll17 ; This used to fail due to a v_add_i32 instruction with an illegal immediate
/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dsaddsat.ll1041 ; GFX9-NEXT: v_add_i32 v0, v0, v1 clamp
1095 ; GFX9-NEXT: v_add_i32 v0, s0, v0 clamp
1140 ; GFX9-NEXT: v_add_i32 v0, v0, v1 clamp
1178 ; GFX9-NEXT: v_add_i32 v0, s0, v0 clamp
1216 ; GFX9-NEXT: v_add_i32 v0, s0, v0 clamp
1253 ; GFX9-NEXT: v_add_i32 v0, v0, s0 clamp
1307 ; GFX9-NEXT: v_add_i32 v0, v0, v2 clamp
1308 ; GFX9-NEXT: v_add_i32 v1, v1, v3 clamp
1362 ; GFX9-NEXT: v_add_i32 v0, s0, v0 clamp
1363 ; GFX9-NEXT: v_add_i32 v
[all...]
/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
H A Dgfx9_vop3.txt21693 # CHECK: v_add_i32 v5, v1, v2 ; encoding: [0x05,0x00,0x9c,0xd2,0x01,0x05,0x02,0x…
21696 # CHECK: v_add_i32 v255, v1, v2 ; encoding: [0xff,0x00,0x9c,0xd2,0x01,0x05,0x02,0x…
21699 # CHECK: v_add_i32 v5, v255, v2 ; encoding: [0x05,0x00,0x9c,0xd2,0xff,0x05,0x02,0x…
21702 # CHECK: v_add_i32 v5, s1, v2 ; encoding: [0x05,0x00,0x9c,0xd2,0x01,0x04,0x02,0x…
21705 # CHECK: v_add_i32 v5, s101, v2 ; encoding: [0x05,0x00,0x9c,0xd2,0x65,0x04,0x02,0x…
21708 # CHECK: v_add_i32 v5, flat_scratch_lo, v2 ; encoding: [0x05,0x00,0x9c,0xd2,0x66,0x04,0x02,0x…
21711 # CHECK: v_add_i32 v5, flat_scratch_hi, v2 ; encoding: [0x05,0x00,0x9c,0xd2,0x67,0x04,0x02,0x…
21714 # CHECK: v_add_i32 v5, vcc_lo, v2 ; encoding: [0x05,0x00,0x9c,0xd2,0x6a,0x04,0x02,0x…
21717 # CHECK: v_add_i32 v5, vcc_hi, v2 ; encoding: [0x05,0x00,0x9c,0xd2,0x6b,0x04,0x02,0x…
21720 # CHECK: v_add_i32 v5, m0, v2 ; encoding: [0x05,0x00,0x9c,0xd2,0x7c,0x04,0x02,0x…
[all …]
/llvm-project/llvm/lib/Target/AMDGPU/
H A DVOP3Instructions.td622 defm V_ADD_I32 : VOP3Inst <"v_add_i32", VOP3_Profile<VOP_I32_I32_I32_ARITH>>;
H A DVOP2Instructions.td2308 defm V_ADD_I32 : VOP2be_Real_gfx6_gfx7_with_name<0x025, "V_ADD_CO_U32", "v_add_i32">;
/llvm-project/llvm/docs/AMDGPU/
H A DAMDGPUAsmGFX7.rst727 …v_add_i32 :ref:`vdst<amdgpu_synid_gfx7_vdst_89680f>`, :ref:`vcc<amdgpu_sy…
H A DAMDGPUAsmGFX9.rst1230 …v_add_i32 :ref:`vdst<amdgpu_synid_gfx9_vdst_89680f>`, :ref:`src0…

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