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/llvm-project/llvm/test/Analysis/CostModel/RISCV/
H A Dshuffle-transpose.ll13 ; CHECK-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %tmp0 = shufflevector <8 x i8> %v0, <8 x i8> %v1, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
14 ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i8> %tmp0
17 ; SIZE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %tmp0 = shufflevector <8 x i8> %v0, <8 x i8> %v1, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
18 ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <8 x i8> %tmp0
20 %tmp0 = shufflevector <8 x i8> %v0, <8 x i8> %v1, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
21 ret <8 x i8> %tmp0
26 ; CHECK-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %tmp0 = shufflevector <8 x i8> %v0, <8 x i8> %v1, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
27 ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i8> %tmp0
30 ; SIZE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %tmp0 = shufflevector <8 x i8> %v0, <8 x i8> %v1, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
31 ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <8 x i8> %tmp0
[all...]
/llvm-project/llvm/test/Transforms/InstCombine/
H A Dcanonicalize-ashr-shl-to-masking.ll22 %tmp0 = ashr i8 %x, %y
23 %ret = shl i8 %tmp0, %y
32 %tmp0 = ashr i8 %x, 3
33 %ret = shl i8 %tmp0, 3
43 %tmp0 = ashr i8 %x, 6
44 %ret = shl i8 %tmp0, 3
54 %tmp0 = ashr i8 %x, 3
55 %ret = shl i8 %tmp0, 6
69 %tmp0 = ashr i8 %x, %y
70 %ret = shl nuw i8 %tmp0,
[all...]
H A Dcanonicalize-constant-low-bit-mask-and-icmp-ult-to-icmp-ugt.ll22 %tmp0 = and i8 %x, 3
23 %ret = icmp ult i8 %tmp0, %x
33 %tmp0 = lshr i8 -1, %y
34 %tmp1 = and i8 %tmp0, %x
48 %tmp0 = and <2 x i8> %x, <i8 3, i8 3>
49 %ret = icmp ult <2 x i8> %tmp0, %x
58 %tmp0 = and <2 x i8> %x, <i8 3, i8 15> ; doesn't have to be splat.
59 %ret = icmp ult <2 x i8> %tmp0, %x
68 %tmp0 = and <2 x i8> %x, <i8 3, i8 0>
69 %ret = icmp ult <2 x i8> %tmp0,
[all...]
H A Dcanonicalize-constant-low-bit-mask-and-icmp-ne-to-icmp-ugt.ll22 %tmp0 = and i8 %x, 3
23 %ret = icmp ne i8 %tmp0, %x
33 %tmp0 = lshr i8 -1, %y
34 %tmp1 = and i8 %tmp0, %x
48 %tmp0 = and <2 x i8> %x, <i8 3, i8 3>
49 %ret = icmp ne <2 x i8> %tmp0, %x
58 %tmp0 = and <2 x i8> %x, <i8 3, i8 15> ; doesn't have to be splat.
59 %ret = icmp ne <2 x i8> %tmp0, %x
68 %tmp0 = and <2 x i8> %x, <i8 3, i8 0>
69 %ret = icmp ne <2 x i8> %tmp0,
[all...]
H A Dcanonicalize-constant-low-bit-mask-and-icmp-uge-to-icmp-ule.ll22 %tmp0 = and i8 %x, 3
23 %ret = icmp uge i8 %tmp0, %x
33 %tmp0 = lshr i8 -1, %y
34 %tmp1 = and i8 %tmp0, %x
48 %tmp0 = and <2 x i8> %x, <i8 3, i8 3>
49 %ret = icmp uge <2 x i8> %tmp0, %x
58 %tmp0 = and <2 x i8> %x, <i8 3, i8 15> ; doesn't have to be splat.
59 %ret = icmp uge <2 x i8> %tmp0, %x
68 %tmp0 = and <2 x i8> %x, <i8 3, i8 0>
69 %ret = icmp uge <2 x i8> %tmp0,
[all...]
H A Dcanonicalize-constant-low-bit-mask-and-icmp-slt-to-icmp-sgt.ll22 %tmp0 = and i8 %x, 3
23 %ret = icmp slt i8 %tmp0, %x
36 %tmp0 = and <2 x i8> %x, <i8 3, i8 3>
37 %ret = icmp slt <2 x i8> %tmp0, %x
46 %tmp0 = and <2 x i8> %x, <i8 3, i8 15> ; doesn't have to be splat.
47 %ret = icmp slt <2 x i8> %tmp0, %x
56 %tmp0 = and <2 x i8> %x, <i8 3, i8 0>
57 %ret = icmp slt <2 x i8> %tmp0, %x
66 %tmp0 = and <3 x i8> %x, <i8 3, i8 poison, i8 3>
67 %ret = icmp slt <3 x i8> %tmp0,
[all...]
H A Dcanonicalize-constant-low-bit-mask-and-icmp-sge-to-icmp-sle.ll22 %tmp0 = and i8 %x, 3
23 %ret = icmp sge i8 %tmp0, %x
36 %tmp0 = and <2 x i8> %x, <i8 3, i8 3>
37 %ret = icmp sge <2 x i8> %tmp0, %x
46 %tmp0 = and <2 x i8> %x, <i8 3, i8 15> ; doesn't have to be splat.
47 %ret = icmp sge <2 x i8> %tmp0, %x
56 %tmp0 = and <2 x i8> %x, <i8 3, i8 0>
57 %ret = icmp sge <2 x i8> %tmp0, %x
66 %tmp0 = and <3 x i8> %x, <i8 3, i8 poison, i8 3>
67 %ret = icmp sge <3 x i8> %tmp0,
[all...]
H A Dcanonicalize-constant-low-bit-mask-and-icmp-ugt-to-icmp-ugt.ll28 %tmp0 = and i8 %x, 3
29 %ret = icmp ugt i8 %x, %tmp0
41 %tmp0 = lshr i8 -1, %y
42 %tmp1 = and i8 %tmp0, %x
58 %tmp0 = and <2 x i8> %x, <i8 3, i8 3>
59 %ret = icmp ugt <2 x i8> %x, %tmp0
70 %tmp0 = and <2 x i8> %x, <i8 3, i8 15> ; doesn't have to be splat.
71 %ret = icmp ugt <2 x i8> %x, %tmp0
82 %tmp0 = and <2 x i8> %x, <i8 3, i8 0>
83 %ret = icmp ugt <2 x i8> %x, %tmp0
[all...]
H A Dcanonicalize-constant-low-bit-mask-and-icmp-eq-to-icmp-ule.ll22 %tmp0 = and i8 %x, 3
23 %ret = icmp eq i8 %tmp0, %x
33 %tmp0 = lshr i8 -1, %y
34 %tmp1 = and i8 %tmp0, %x
48 %tmp0 = and <2 x i8> %x, <i8 3, i8 3>
49 %ret = icmp eq <2 x i8> %tmp0, %x
58 %tmp0 = and <2 x i8> %x, <i8 3, i8 15> ; doesn't have to be splat.
59 %ret = icmp eq <2 x i8> %tmp0, %x
68 %tmp0 = and <2 x i8> %x, <i8 3, i8 0>
69 %ret = icmp eq <2 x i8> %tmp0,
[all...]
H A Dcanonicalize-constant-low-bit-mask-and-icmp-ule-to-icmp-ule.ll28 %tmp0 = and i8 %x, 3
29 %ret = icmp ule i8 %x, %tmp0
41 %tmp0 = lshr i8 -1, %y
42 %tmp1 = and i8 %tmp0, %x
58 %tmp0 = and <2 x i8> %x, <i8 3, i8 3>
59 %ret = icmp ule <2 x i8> %x, %tmp0
70 %tmp0 = and <2 x i8> %x, <i8 3, i8 15> ; doesn't have to be splat.
71 %ret = icmp ule <2 x i8> %x, %tmp0
82 %tmp0 = and <2 x i8> %x, <i8 3, i8 0>
83 %ret = icmp ule <2 x i8> %x, %tmp0
[all...]
H A Dcanonicalize-constant-low-bit-mask-and-icmp-sgt-to-icmp-sgt.ll30 %tmp0 = and i8 %x, 3
31 %ret = icmp sgt i8 %x, %tmp0
46 %tmp0 = and <2 x i8> %x, <i8 3, i8 3>
47 %ret = icmp sgt <2 x i8> %x, %tmp0
58 %tmp0 = and <2 x i8> %x, <i8 3, i8 15> ; doesn't have to be splat.
59 %ret = icmp sgt <2 x i8> %x, %tmp0
70 %tmp0 = and <2 x i8> %x, <i8 3, i8 0>
71 %ret = icmp sgt <2 x i8> %x, %tmp0
82 %tmp0 = and <3 x i8> %x, <i8 3, i8 poison, i8 3>
83 %ret = icmp sgt <3 x i8> %x, %tmp0
[all...]
H A Dcanonicalize-constant-low-bit-mask-and-icmp-sle-to-icmp-sle.ll30 %tmp0 = and i8 %x, 3
31 %ret = icmp sle i8 %x, %tmp0
46 %tmp0 = and <2 x i8> %x, <i8 3, i8 3>
47 %ret = icmp sle <2 x i8> %x, %tmp0
58 %tmp0 = and <2 x i8> %x, <i8 3, i8 15> ; doesn't have to be splat.
59 %ret = icmp sle <2 x i8> %x, %tmp0
70 %tmp0 = and <2 x i8> %x, <i8 3, i8 0>
71 %ret = icmp sle <2 x i8> %x, %tmp0
82 %tmp0 = and <3 x i8> %x, <i8 3, i8 poison, i8 3>
83 %ret = icmp sle <3 x i8> %x, %tmp0
[all...]
/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dsetcc64.ll14 %tmp0 = fcmp oeq double %a, %b
15 %tmp1 = sext i1 %tmp0 to i32
24 %tmp0 = fcmp ogt double %a, %b
25 %tmp1 = sext i1 %tmp0 to i32
34 %tmp0 = fcmp oge double %a, %b
35 %tmp1 = sext i1 %tmp0 to i32
44 %tmp0 = fcmp olt double %a, %b
45 %tmp1 = sext i1 %tmp0 to i32
54 %tmp0 = fcmp ole double %a, %b
55 %tmp1 = sext i1 %tmp0 to i32
[all …]
/llvm-project/llvm/test/Analysis/CostModel/AArch64/
H A Dfree-widening-casts.ll7 ; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %tmp0 = zext <8 x i8> %a to…
12 %tmp0 = zext <8 x i8> %a to <8 x i16>
14 %tmp2 = add <8 x i16> %tmp0, %tmp1
19 ; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %tmp0 = zext <4 x i16> %a t…
24 %tmp0 = zext <4 x i16> %a to <4 x i32>
26 %tmp2 = add <4 x i32> %tmp0, %tmp1
31 ; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %tmp0 = zext <2 x i32> %a t…
36 %tmp0 = zext <2 x i32> %a to <2 x i64>
38 %tmp2 = add <2 x i64> %tmp0, %tmp1
43 ; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %tmp0 = zext <16 x i8> %a t…
[all …]
H A Dshuffle-transpose.ll7 ; COST: Found an estimated cost of 1 for instruction: %tmp0 = shufflevector <8 x i8> %v0, <8 …
11 …%tmp0 = shufflevector <8 x i8> %v0, <8 x i8> %v1, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i…
12 ret <8 x i8> %tmp0
16 ; COST: Found an estimated cost of 1 for instruction: %tmp0 = shufflevector <8 x i8> %v0, <8 …
20 …%tmp0 = shufflevector <8 x i8> %v0, <8 x i8> %v1, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i…
21 ret <8 x i8> %tmp0
25 ; COST: Found an estimated cost of 1 for instruction: %tmp0 = shufflevector <16 x i8> %v0, <1…
29 …%tmp0 = shufflevector <16 x i8> %v0, <16 x i8> %v1, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 …
30 ret <16 x i8> %tmp0
34 ; COST: Found an estimated cost of 1 for instruction: %tmp0 = shufflevector <16 x i8> %v0, <1…
[all …]
H A Dshuffle-select.ll8 ; COST-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %tmp0 = shufflevector <8 x i8> %v0, <8 x i8> %v1, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
9 ; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i8> %tmp0
11 %tmp0 = shufflevector <8 x i8> %v0, <8 x i8> %v1, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
12 ret <8 x i8> %tmp0
17 ; COST-NEXT: Cost Model: Found an estimated cost of 60 for instruction: %tmp0 = shufflevector <16 x i8> %v0, <16 x i8> %v1, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
18 ; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %tmp0
20 %tmp0 = shufflevector <16 x i8> %v0, <16 x i8> %v1, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
21 ret <16 x i8> %tmp0
26 ; COST-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %tmp0 = shufflevector <4 x i16> %v0, <4 x i16> %v1, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
27 ; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i16> %tmp0
[all...]
/llvm-project/llvm/test/CodeGen/AArch64/
H A Dsigned-truncation-check.ll29 %tmp0 = shl i16 %x, 8 ; 16-8
30 %tmp1 = ashr exact i16 %tmp0, 8 ; 16-8
41 %tmp0 = shl i32 %x, 16 ; 32-16
42 %tmp1 = ashr exact i32 %tmp0, 16 ; 32-16
53 %tmp0 = shl i32 %x, 24 ; 32-8
54 %tmp1 = ashr exact i32 %tmp0, 24 ; 32-8
65 %tmp0 = shl i64 %x, 32 ; 64-32
66 %tmp1 = ashr exact i64 %tmp0, 32 ; 64-32
77 %tmp0 = shl i64 %x, 48 ; 64-16
78 %tmp1 = ashr exact i64 %tmp0, 4
[all...]
H A Dlack-of-signed-truncation-check.ll29 %tmp0 = shl i16 %x, 8 ; 16-8
30 %tmp1 = ashr exact i16 %tmp0, 8 ; 16-8
41 %tmp0 = shl i32 %x, 16 ; 32-16
42 %tmp1 = ashr exact i32 %tmp0, 16 ; 32-16
53 %tmp0 = shl i32 %x, 24 ; 32-8
54 %tmp1 = ashr exact i32 %tmp0, 24 ; 32-8
65 %tmp0 = shl i64 %x, 32 ; 64-32
66 %tmp1 = ashr exact i64 %tmp0, 32 ; 64-32
77 %tmp0 = shl i64 %x, 48 ; 64-16
78 %tmp1 = ashr exact i64 %tmp0, 48 ; 64-16
[all …]
H A Daddimm-mulimm.ll11 %tmp0 = add i64 %a, 31
12 %tmp1 = mul i64 %tmp0, 37
23 %tmp0 = add i64 %a, -31
24 %tmp1 = mul i64 %tmp0, 37
35 %tmp0 = add i32 %a, 31
36 %tmp1 = mul i32 %tmp0, 37
47 %tmp0 = add i32 %a, -31
48 %tmp1 = mul i32 %tmp0, 37
60 %tmp0 = add i64 %a, 31000
61 %tmp1 = mul i64 %tmp0, 37
[all …]
H A Dptrauth-call.ll28 %tmp0 = call i32 %arg0() [ "ptrauth"(i32 0, i64 0) ]
29 ret i32 %tmp0
44 %tmp0 = call i32 %arg0() [ "ptrauth"(i32 1, i64 0) ]
45 ret i32 %tmp0
51 %tmp0 = tail call i32 %arg0() [ "ptrauth"(i32 0, i64 0) ]
52 ret i32 %tmp0
58 %tmp0 = tail call i32 %arg0() [ "ptrauth"(i32 1, i64 0) ]
59 ret i32 %tmp0
76 %tmp0 = call i32 %arg0() [ "ptrauth"(i32 0, i64 42) ]
77 ret i32 %tmp0
[all...]
H A Dptrauth-bti-call.ll21 %tmp0 = tail call i32 %arg0() [ "ptrauth"(i32 0, i64 0) ]
22 ret i32 %tmp0
30 %tmp0 = tail call i32 %arg0() [ "ptrauth"(i32 1, i64 0) ]
31 ret i32 %tmp0
40 %tmp0 = tail call i32 %arg0() [ "ptrauth"(i32 0, i64 42) ]
41 ret i32 %tmp0
50 %tmp0 = tail call i32 %arg0() [ "ptrauth"(i32 1, i64 42) ]
51 ret i32 %tmp0
64 %tmp0 = load i64, i64* %arg1
65 %tmp1 = tail call i32 %arg0() [ "ptrauth"(i32 0, i64 %tmp0) ]
[all...]
/llvm-project/llvm/test/Analysis/UniformityAnalysis/AMDGPU/
H A Dintrinsics.ll38 ; CHECK: DIVERGENT: %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 1, i32 1, i32 1, i1 false) #0
40 %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 1, i32 1, i32 1, i1 false) #0
41 store i32 %tmp0, ptr addrspace(1) %out
45 ; CHECK: DIVERGENT: %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in, i32 1, i32 1, i32 1, i1 true) #0
47 %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in, i32 1, i32 1, i32 1, i1 true) #0
48 store i32 %tmp0, ptr addrspace(1) %out
52 ; CHECK: DIVERGENT: %tmp0 = call i32 @llvm.amdgcn.mov.dpp8.i32(i32 %in, i32 1) #0
54 %tmp0 = call i32 @llvm.amdgcn.mov.dpp8.i32(i32 %in, i32 1) #0
55 store i32 %tmp0, ptr addrspace(1) %out
59 ; CHECK: DIVERGENT: %tmp0
[all...]
/llvm-project/llvm/test/Transforms/InferAddressSpaces/AMDGPU/
H A Dbasic.ll6 ; CHECK-NEXT: %tmp0 = addrspacecast ptr %generic_scalar to ptr addrspace(1)
7 ; CHECK-NEXT: %tmp1 = load float, ptr addrspace(1) %tmp0
10 %tmp0 = addrspacecast ptr %generic_scalar to ptr addrspace(1)
11 %tmp1 = load float, ptr addrspace(1) %tmp0
16 ; CHECK-NEXT: %tmp0 = addrspacecast ptr %generic_scalar to ptr addrspace(4)
17 ; CHECK-NEXT: %tmp1 = load float, ptr addrspace(4) %tmp0
20 %tmp0 = addrspacecast ptr %generic_scalar to ptr addrspace(4)
21 %tmp1 = load float, ptr addrspace(4) %tmp0
26 ; CHECK-NEXT: %tmp0 = addrspacecast ptr %generic_scalar to ptr addrspace(3)
27 ; CHECK-NEXT: %tmp1 = load float, ptr addrspace(3) %tmp0
[all...]
/llvm-project/llvm/test/Transforms/SLPVectorizer/AArch64/
H A Dtranspose-inseltpoison.ll20 %tmp0.0 = add i64 %v0.0, %v1.0
21 %tmp0.1 = add i64 %v0.1, %v1.1
24 %tmp2.0 = add i64 %tmp0.0, %tmp0.1
50 %tmp0.0 = add i64 %v0.0, %v1.0
51 %tmp0.1 = add i64 %v0.1, %v1.1
54 %tmp2.0 = add i64 %tmp0.0, %tmp0.1
78 %tmp0.0 = add i32 %v0.0, %v1.0
79 %tmp0
[all...]
H A Dtranspose.ll20 %tmp0.0 = add i64 %v0.0, %v1.0
21 %tmp0.1 = add i64 %v0.1, %v1.1
24 %tmp2.0 = add i64 %tmp0.0, %tmp0.1
50 %tmp0.0 = add i64 %v0.0, %v1.0
51 %tmp0.1 = add i64 %v0.1, %v1.1
54 %tmp2.0 = add i64 %tmp0.0, %tmp0.1
78 %tmp0.0 = add i32 %v0.0, %v1.0
79 %tmp0
[all...]

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