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/llvm-project/llvm/utils/emacs/
H A DREADME6 * llvm-mode.el
8 Syntax highlighting mode for LLVM assembly files. To use, add this code to
13 (require 'llvm-mode)
15 * llvm-mir-mode.el
17 Syntax highlighting mode for LLVM Machine IR files. To use, add this code to
22 (require 'llvm-mir-mode)
24 * tablegen-mode.el
26 Syntax highlighting mode for TableGen description files. To use, add this code
31 (require 'tablegen-mode)
/llvm-project/llvm/utils/jedit/
H A DREADME5 * tablegen.xml
7 Syntax highlighting mode for TableGen description files. To use, copy this
10 <MODE NAME="tablegen" FILE="tablegen.xml" FILE_NAME_GLOB="*.td" />
/llvm-project/llvm/utils/gn/
H A DTODO.txt11 - "optimized tblgen" mode
12 - either just always build tablegen and support with opt config
13 - or use opt toolchain and build tablegen twice in debug builds, like cmake
19 - move run_tablegen.py from build to tablegen folder
/llvm-project/mlir/include/mlir/Reducer/
H A DPasses.td1 //===-- Passes.td - MLIR Reduce pass definition file -------*- tablegen -*-===//
33 Option<"traversalModeId", "traversal-mode", "unsigned",
35 "The graph traversal mode, the default is single-path mode">,
/llvm-project/llvm/lib/Target/Sparc/
H A DLeonFeatures.td1 //===-- LeonFeatures.td - Describe the Leon Features -------*- tablegen -*-===//
50 "LEON3 erratum detection: Detects any rounding mode change "
51 "request: use only the round-to-nearest rounding mode"
/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZfbfmin.td1 //===-- RISCVInstrInfoZfbfmin.td - 'Zfbfmin' instructions --*- tablegen -*-===//
H A DRISCVInstrInfoZfa.td1 //===-- RISCVInstrInfoZfa.td - RISC-V 'Zfa' instructions ---*- tablegen -*-===//
210 // frint rounds according to the current rounding mode and detects
235 // frint rounds according to the current rounding mode and detects
265 // frint rounds according to the current rounding mode and detects
/llvm-project/llvm/utils/vim/
H A DREADME4 tablegen *.td files. It comes with filetype detection rules in the (ftdetect),
20 " LLVM Makefile highlighting mode
H A Dvimrc82 " Enable syntax highlighting for tablegen files. To use, copy
83 " utils/vim/syntax/tablegen.vim to ~/.vim/syntax .
85 au! BufRead,BufNewFile *.td set filetype=tablegen
116 " In findstart mode, look for the beginning of the current identifier.
/llvm-project/mlir/include/mlir/Dialect/ArmSME/Transforms/
H A DPasses.td1 //===-- Passes.td - ArmSME pass definition file ------------*- tablegen -*-===//
15 def ArmStreamingMode : I32EnumAttr<"ArmStreamingMode", "Armv9 Streaming SVE mode",
18 // Streaming: Streaming-mode is part of the function interface (ABI).
24 // non-streaming mode (PSTATE.SM=0) or in streaming mode (PSTATE.SM=1)
41 def ArmZaMode : I32EnumAttr<"ArmZaMode", "Armv9 ZA storage mode",
63 let summary = "Enable Armv9 Streaming SVE mode";
65 Enables the Armv9 Streaming SVE mode [1] for func.func ops by annotating
72 Option<"streamingMode", "streaming-mode", "mlir::arm_sme::ArmStreamingMode",
74 "Select how streaming-mode i
[all...]
/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrFormats.td1 //===-- M68kInstrFormats.td - M68k Instruction Formats -----*- tablegen -*-===//
25 /// 14 M68020 ([bd,An],Xn.L,SCALE,od) u memory indirect postindexed mode
26 /// 13 M68020 ([bd,An],Xn.W,SCALE,od) U memory indirect postindexed mode
27 /// 16 M68020 ([bd,An,Xn.L,SCALE],od) v memory indirect preindexed mode
28 /// 15 M68020 ([bd,An,Xn.W,SCALE],od) V memory indirect preindexed mode
36 …/ 27 M68020 ([bd,PC],Xn.L,SCALE,od) x program counter memory indirect postindexed mode
37 …/ 26 M68020 ([bd,PC],Xn.W,SCALE,od) X program counter memory indirect postindexed mode
38 /// 31 M68020 ([bd,PC,Xn.L,SCALE],od) y program counter memory indirect preindexed mode
39 /// 30 M68020 ([bd,PC,Xn.W,SCALE],od) Y program counter memory indirect preindexed mode
211 // is composed of two 3-bit fields: the mode field and the register field. The
[all …]
H A DM68kInstrCompiler.td1 //===-- M68kInstrCompiler.td - Pseudos and Patterns --------*- tablegen -*-===//
97 // FIXME TC is disabled for PIC mode because the global base
98 // register which is part of the address mode may be assigned a
/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedPredicates.td1 //===- AArch64SchedPredicates.td - AArch64 Sched Preds -----*- tablegen -*-===//
40 // Check the extension type in the register offset addressing mode.
48 // Check for scaling in the register offset addressing mode.
145 // load using the post index addressing mode.
174 // store using the post index addressing mode.
195 // or store using the post index addressing mode.
200 // using the register offset addressing mode.
216 // using the register offset addressing mode.
228 // store using the register offset addressing mode.
254 // Identify a load or store using the register offset addressing mode
H A DAArch64SchedPredExynos.td1 //===- AArch64SchedPredExynos.td - AArch64 Sched Preds -----*- tablegen -*-===//
97 // Identify a load or store using the register offset addressing mode
/llvm-project/mlir/include/mlir/Dialect/GPU/IR/
H A DGPUDeviceMappingAttr.td1 //===-- GPUDeviceMappingAttr.td - Attribute definition -----*- tablegen -*-===//
57 2 modes are supported: (1) 3D mapping mode and (2) linear mapping mode.
59 #### 3D mapping mode
65 #### Linear mapping mode
104 2 modes are supported: (1) 3D mapping mode and (2) linear mapping mode.
106 #### 3D mapping mode
113 #### Linear mapping mode
153 2 modes are supported: (1) 3D mapping mode and (2) linear mapping mode.
155 #### 3D mapping mode
162 #### Linear mapping mode
[all …]
/llvm-project/mlir/include/mlir/Dialect/Arith/IR/
H A DArithOpsInterfaces.td1 //===-- ArithOpsInterfaces.td - arith op interfaces ---*- tablegen -*-===//
111 Access to op rounding mode.
H A DArithBase.td1 //===- ArithBase.td - Base defs for arith dialect -----------*- tablegen -*-==//
178 "RoundingMode", "Floating point rounding mode",
/llvm-project/llvm/lib/Target/VE/
H A DVECallingConv.td1 //===-- VECallingConv.td - Calling Conventions VE ----------*- tablegen -*-===//
108 // TODO: make this conditional on packed mode
129 // TODO: make this conditional on packed mode
/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrFormats.td1 //==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==//
14 def NoAddrMode : AddrModeType<0>; // No addressing mode
15 def Absolute : AddrModeType<1>; // Absolute addressing mode
16 def AbsoluteSet : AddrModeType<2>; // Absolute set addressing mode
20 def PostInc : AddrModeType<6>; // Post increment addressing mode
135 // Addressing mode for load/store instructions.
245 // is only leveraged in a special disassembler mode that's activated
/llvm-project/llvm/lib/Target/Mips/
H A DMips.td1 //===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
36 // Predicate for marking the instruction as usable in hard-float mode only.
73 "Disable IEEE 754-2008 abs.fmt mode">;
155 "Mips16 mode">;
179 "microMips mode">;
H A DMipsCallingConv.td1 //===-- MipsCallingConv.td - Calling Conventions for Mips --*- tablegen -*-===//
67 // tablegen-erated code.
106 // f64 arguments are returned in D0_64 and D2_64 in FP64bit mode or
107 // in D0 and D1 in FP32bit mode.
195 // whether the result was originally an f128 into the tablegen-erated code.
332 // whether the argument was originally an f128 into the tablegen-erated code.
/llvm-project/mlir/include/mlir/Dialect/NVGPU/TransformOps/
H A DNVGPUTransformOps.td1 //===- NVGPUTransformOps.td - NVGPU transform ops ----------*- tablegen -*-===//
113 predication. If failure propagation mode is set to "propagate", produces a
116 lack of loads into shared memory. If the failure propagation mode is set
/llvm-project/llvm/lib/Target/X86/
H A DX86InstrPredicates.td1 //===---X86InstrPredicates.td - X86 Predicate Definitions --*- tablegen -*-===//
198 AssemblerPredicate<(all_of (not Is64Bit)), "Not 64-bit mode">;
200 AssemblerPredicate<(all_of Is64Bit), "64-bit mode">;
204 AssemblerPredicate<(all_of Is16Bit), "16-bit mode">;
206 AssemblerPredicate<(all_of (not Is16Bit)), "Not 16-bit mode">;
208 AssemblerPredicate<(all_of Is32Bit), "32-bit mode">;
H A DX86InstrFormats.td1 //===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===//
180 // Operand size for encodings that change based on mode.
185 def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32/64-bit mode.
186 def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode.
188 // Address size for encodings that change based on mode.
233 // based on operand size of the mode?
236 // based on address size of the mode?
/llvm-project/mlir/include/mlir/Dialect/Transform/Transforms/
H A DPasses.td1 //===-- Passes.td - Transform dialect pass definitions -----*- tablegen -*-===//
55 // TODO: investigate using a resource blob if some ownership mode allows it.

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