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/llvm-project/mlir/test/Dialect/GPU/
H A Dmapping.mlir20 // CHECK: {mapping = [#gpu.loop_dim_map<processor = thread_x, map = (d0) -> (d0), bound = (d0)…
21 // CHECK-SAME: #gpu.loop_dim_map<processor = thread_y, map = (d0) -> (d0), bound = (d0)…
22 // CHECK: {mapping = [#gpu.loop_dim_map<processor = block_x, map = (d0) -> (d0), bound = (d0) …
23 // CHECK-SAME: #gpu.loop_dim_map<processor = block_y, map = (d0) -> (d0), bound = (d0) …
49 // CHECK: {mapping = [#gpu.loop_dim_map<processor = sequential, map = (d0) -> (d0), bound = (d…
50 // CHECK-SAME: #gpu.loop_dim_map<processor = sequential, map = (d0) -> (d0), bound = (d…
51 // CHECK-SAME: #gpu.loop_dim_map<processor = sequential, map = (d0) -> (d0), bound = (d…
52 // CHECK-SAME: #gpu.loop_dim_map<processor = sequential, map = (d0) -> (d0), bound = (d…
53 // CHECK: {mapping = [#gpu.loop_dim_map<processor = thread_x, map = (d0) -> (d0), bound = (d0)…
54 // CHECK-SAME: #gpu.loop_dim_map<processor = thread_y, map = (d0) -> (d0), bound = (d0)…
[all …]
/llvm-project/mlir/test/Conversion/SCFToGPU/
H A Dparallel_loop.mlir14 } { mapping = [#gpu.loop_dim_map<processor = block_y, map = (d0) -> (d0), bound = (d0) -> (d0)>, #gpu.loop_dim_map<processor = block_x, map = (d0) -> (d0), bound = (d0) -> (d0)>] }
59 #gpu.loop_dim_map<processor = thread_y, map = (d0) -> (d0), bound = (d0) -> (d0)>,
60 #gpu.loop_dim_map<processor = thread_x, map = (d0) -> (d0), bound = (d0) -> (d0)>
63 #gpu.loop_dim_map<processor = block_y, map = (d0) -> (d0), bound = (d0) -> (d0)>,
64 #gpu.loop_dim_map<processor = block_x, map = (d0) -> (d0), bound = (d0) -> (d0)>
112 #gpu.loop_dim_map<processor = block_y, map = (d0) -> (d0), bound = (d0) -> (d0)>,
113 #gpu.loop_dim_map<processor = sequential, map = (d0) -> (d0), bound = (d0) -> (d0)>
159 #gpu.loop_dim_map<processor = thread_y, map = (d0) -> (d0), bound = (d0) -> (d0)>,
160 #gpu.loop_dim_map<processor
[all...]
/llvm-project/mlir/lib/Dialect/GPU/Transforms/
H A DParallelLoopMapper.cpp39 gpu::Processor processor = dimAttr.getProcessor(); in setMappingAttr() local
40 if (processor != gpu::Processor::Sequential && in setMappingAttr()
41 specifiedMappings.count(processor)) in setMappingAttr()
44 specifiedMappings.insert(processor); in setMappingAttr()
/llvm-project/mlir/include/mlir/Dialect/GPU/IR/
H A DParallelLoopMapperAttr.td28 def ProcessorEnum : I64EnumAttr<"Processor", "processor for loop mapping", [
35 // processor: the hardware id to map to.
43 EnumParameter<ProcessorEnum>:$processor,
52 "parallel loop to processor mapping attribute">;
/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dunknown-processor.ll5 ; Should not crash when the processor is not recognized and the
10 ; ERROR: 'unknown' is not a recognized processor for this target (ignoring processor)
/llvm-project/mlir/lib/Conversion/SCFToGPU/
H A DSCFToGPU.cpp356 static bool isMappedToProcessor(gpu::Processor processor) { in isMappedToProcessor() argument
357 return processor != gpu::Processor::Sequential; in isMappedToProcessor()
360 static unsigned getLaunchOpArgumentNum(gpu::Processor processor) { in getLaunchOpArgumentNum() argument
361 switch (processor) { in getLaunchOpArgumentNum()
377 "invalid processor type while retrieving launch op argument number"); in getLaunchOpArgumentNum()
400 /// worklist. This signals the processor of the worklist to pop the rewriter
407 // processor ids: 0-2 block [x/y/z], 3-5 -> thread [x/y/z], 6-> sequential in processParallelLoop()
443 gpu::Processor processor = annotation.getProcessor(); in processParallelLoop() local
445 if (isMappedToProcessor(processor)) { in processParallelLoop()
448 launchOp.getBody().getArgument(getLaunchOpArgumentNum(processor)); in processParallelLoop()
[all...]
/llvm-project/lldb/source/Plugins/Process/Linux/
H A DProcfs.cpp44 cpu_id_t processor; in GetAvailableLogicalCoreIDs() local
45 if (val.getAsInteger(10, processor)) in GetAvailableLogicalCoreIDs()
49 logical_cores.push_back(processor); in GetAvailableLogicalCoreIDs()
/llvm-project/llvm/test/tools/llvm-readobj/ELF/
H A Dsymbol-types.test2 # and also for unknown types, both in the os/processor specific ranges and not,
55 # GNU: <processor specific>: 13 {{.*}} proc_specific_13
56 # GNU: <processor specific>: 14 {{.*}} proc_specific_14
57 # GNU: <processor specific>: 15 {{.*}} proc_specific_15
H A Dmips-reginfo.test27 0x55, 0x66, 0x77, 0x88, ## Bit-mask of used co-processor registers (0).
28 0x99, 0xAA, 0xBB, 0xCC, ## Bit-mask of used co-processor registers (1).
29 0xDD, 0xEE, 0xFF, 0x1E, ## Bit-mask of used co-processor registers (2).
30 0x2E, 0x3E, 0x4E, 0x5E, ## Bit-mask of used co-processor registers (3).
H A Dfile-header-machine-types.test121 … llvm-readelf --file-headers %t.ncpu.o | FileCheck %s -DMACHINE="Sony nCPU embedded RISC processor"
127 …: llvm-readelf --file-headers %t.starcore.o | FileCheck %s -DMACHINE="Motorola Star*Core processor"
130 # RUN: llvm-readelf --file-headers %t.me16.o | FileCheck %s -DMACHINE="Toyota ME16 processor"
133 …lvm-readelf --file-headers %t.st100.o | FileCheck %s -DMACHINE="STMicroelectronics ST100 processor"
136 … --file-headers %t.tinyj.o | FileCheck %s -DMACHINE="Advanced Logic Corp. TinyJ embedded processor"
142 # RUN: llvm-readelf --file-headers %t.pdsp.o | FileCheck %s -DMACHINE="Sony DSP processor"
181 …f --file-headers %t.cris.o | FileCheck %s -DMACHINE="Axis Communications 32-bit embedded processor"
187 …lvm-readelf --file-headers %t.firepath.o | FileCheck %s -DMACHINE="Element 14 64-bit DSP processor"
190 …N: llvm-readelf --file-headers %t.zsp.o | FileCheck %s -DMACHINE="LSI Logic's 16-bit DSP processor"
193 …elf --file-headers %t.mmix.o | FileCheck %s -DMACHINE="Donald Knuth's educational 64-bit processor"
[all …]
H A Dgnu-sections.test3 ## EM_NONE is a target that does not have any processor and OS specific flags,
26 # ELF32-NEXT: R (retain), p (processor specific)
100 # ELF64-NEXT: R (retain), l (large), p (processor specific)
112 # ARM-NEXT: R (retain), y (purecode), p (processor specific)
H A Dsection-flags-os-proc.test1 ## Here we test how OS and processor specific flags are dumped.
90 ## flags to test what we dump when bits in the OS and processor specific ranges are set.
126 ## 0x80000000. When SHF_EXCLUDE is mixed with other processor specific
129 ## processor flags set. Check llvm-readelf output matches GNU.
H A Dmips-options-sec.test74 … 0x55, 0x66, 0x77, 0x88, ## ODK_REGINFO: bit-mask of used co-processor registers (0).
75 … 0x99, 0xAA, 0xBB, 0xCC, ## ODK_REGINFO: bit-mask of used co-processor registers (1).
76 … 0xDD, 0xEE, 0xFF, 0x1E, ## ODK_REGINFO: bit-mask of used co-processor registers (2).
77 … 0x2E, 0x3E, 0x4E, 0x5E, ## ODK_REGINFO: bit-mask of used co-processor registers (3).
/llvm-project/llvm/test/tools/llvm-nm/
H A Dformat-sysv-type.test47 # CHECK-NEXT: proc_specific_13 | | U |<processor specific>: 13| …
48 # CHECK-NEXT: proc_specific_14 | | U |<processor specific>: 14| …
49 # CHECK-NEXT: proc_specific_15 | | U |<processor specific>: 15| …
/llvm-project/llvm/include/llvm/Target/
H A DTargetSchedule.td27 // processor resources and latency with each SchedReadWrite type.
105 // A processor may only implement part of published ISA, due to either new ISA
109 // For a processor which doesn't support some feature(s), the schedule model
132 // Define a kind of processor resource that may be common across
136 // Define a number of interchangeable processor resources. NumUnits
185 // SchedModel ties these units to a processor for any stand-alone defs
195 // Subtargets typically define processor resource kind and number of
249 // SchedModel ties these resources to a processor.
264 // Allow a processor to mark some scheduling classes as unsupported
267 // Allow a processor to mark some scheduling classes as single-issue.
[all …]
/llvm-project/llvm/test/tools/llvm-mca/X86/
H A Dinvalid-cpu.s3 # CHECK: 'foo' is not a recognized processor for this target (ignoring processor)
/llvm-project/llvm/docs/HistoricalNotes/
H A D2001-04-16-DynamicCompilation.txt32 evolve, and each implementation of an ISA (a processor) must choose a set
34 With every new processor introduced, the vendor faces two fundamental
35 problems: First, there is a lag time between when a processor is introduced
40 processor may be compiled quite sub-optimally for the current
H A D2001-07-06-LoweringIRForCodeGen.txt14 What I was going to suggest was that for a particular processor, we define
16 processor but have VM semantics otherwise, i.e., all operands are in SSA
/llvm-project/clang-tools-extra/docs/clang-tidy/checks/cert/
H A Denv33-c.rst7 execute a command processor. It does not flag calls to ``system()`` with a null
8 pointer argument, as such a call checks for the presence of a command processor
/llvm-project/clang/docs/
H A DClangOffloadBundler.rst291 * There can be multiple entries for the same processor provided they differ
294 entries must specify that target feature as *Any* for the same processor.
304 executed on a target processor, if:
315 A target ID is used to indicate the processor and optionally its configuration,
330 <target-id> ::== <processor> ( ":" <target-feature> ( "+" | "-" ) )*
334 **processor**
335 Is a the target specific processor or any alternative processor name.
338 Is a target feature name that is supported by the processor. Each target
345 value of a target feature can be loaded and executed on a processor
[all...]
/llvm-project/llvm/test/CodeGen/WebAssembly/
H A Dcpus.ll12 ; CHECK-NOT: is not a recognized processor for this target
13 ; INVALID: {{.+}} is not a recognized processor for this target
/llvm-project/llvm/test/CodeGen/X86/
H A D2008-06-13-VolatileLoadStore.ll25 store volatile double %b, ptr @atomic ; one processor operation only
26 store volatile double 0.000000e+00, ptr @atomic2 ; one processor operation only
H A Dcpus-other.ll4 ; CHECK-ERROR: not a recognized processor for this target
9 ; CHECK-NO-ERROR-NOT: not a recognized processor for this target
/llvm-project/llvm/utils/release/
H A Dbump-version.py207 for f, processor in files_to_update:
208 processor.process_file(source_root / Path(f), version)
/llvm-project/lldb/source/Plugins/TraceExporter/docs/
H A Dhtr.rst3 The humongous amount of data processor traces like the ones obtained with Intel PT contain is not d…
9 **Block Metadata:** Metadata associated with each *block*. For processor traces, some metadata exam…
22 …d on its specific purpose - for example, a pass designed to summarize a processor trace by functio…

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