| /llvm-project/llvm/test/MC/AMDGPU/ |
| H A D | gfx1030_err.s | 117 ds_min_src2_u64 v1 offset:65535 label
|
| H A D | gfx90a_err.s | 69 ds_min_src2_u64 v1 label
|
| H A D | gfx7_asm_ds.s | 2829 ds_min_src2_u64 v1 offset:65535 label
2832 ds_min_src2_u64 v255 offset:65535 label
2835 ds_min_src2_u64 v1 label
2838 ds_min_src2_u64 v1 offset:0 label
2841 ds_min_src2_u64 v1 offset:4 label
2844 ds_min_src2_u64 v1 offset:65535 gds label
|
| H A D | gfx9_asm_ds.s | 3138 ds_min_src2_u64 v1 offset:65535 label
3141 ds_min_src2_u64 v255 offset:65535 label
3144 ds_min_src2_u64 v1 label
3147 ds_min_src2_u64 v1 offset:0 label
3150 ds_min_src2_u64 v1 offset:4 label
3153 ds_min_src2_u64 v1 offset:65535 gds label
|
| H A D | gfx8_asm_ds.s | 2934 ds_min_src2_u64 v1 offset:65535 label
2937 ds_min_src2_u64 v255 offset:65535 label
2940 ds_min_src2_u64 v1 label
2943 ds_min_src2_u64 v1 offset:0 label
2946 ds_min_src2_u64 v1 offset:4 label
2949 ds_min_src2_u64 v1 offset:65535 gds label
|
| H A D | gfx10_asm_ds.s | 6761 ds_min_src2_u64 v1 offset:65535 label
6764 ds_min_src2_u64 v255 offset:65535 label
6767 ds_min_src2_u64 v1 label
6770 ds_min_src2_u64 v1 offset:0 label
6773 ds_min_src2_u64 v1 offset:4 label
6776 ds_min_src2_u64 v1 offset:65535 gds label
|
| H A D | gfx11_unsupported.s | 112 ds_min_src2_u64 v1
109 ds_min_src2_u64 v1 global() label
|
| /llvm-project/llvm/test/MC/Disassembler/AMDGPU/ |
| H A D | gfx8_ds.txt | 2490 # CHECK: ds_min_src2_u64 v1 offset:65535 ; encoding: [0xff,0xff,0x8e,0xd9,0x01,0x00,0x00,0x…
2493 # CHECK: ds_min_src2_u64 v255 offset:65535 ; encoding: [0xff,0xff,0x8e,0xd9,0xff,0x00,0x00,0x…
2496 # CHECK: ds_min_src2_u64 v1 ; encoding: [0x00,0x00,0x8e,0xd9,0x01,0x00,0x00,0x…
2499 # CHECK: ds_min_src2_u64 v1 offset:4 ; encoding: [0x04,0x00,0x8e,0xd9,0x01,0x00,0x00,0x…
2502 # CHECK: ds_min_src2_u64 v1 offset:65535 gds ; encoding: [0xff,0xff,0x8f,0xd9,0x01,0x00,0x00,0x…
|
| H A D | gfx9_ds.txt | 2658 # CHECK: ds_min_src2_u64 v1 offset:65535 ; encoding: [0xff,0xff,0x8e,0xd9,0x01,0x00,0x00,0x00]
2661 # CHECK: ds_min_src2_u64 v255 offset:65535 ; encoding: [0xff,0xff,0x8e,0xd9,0xff,0x00,0x00,0x00]
2664 # CHECK: ds_min_src2_u64 v1 ; encoding: [0x00,0x00,0x8e,0xd9,0x01,0x00,0x00,0x00]
2667 # CHECK: ds_min_src2_u64 v1 offset:4 ; encoding: [0x04,0x00,0x8e,0xd9,0x01,0x00,0x00,0x00]
2670 # CHECK: ds_min_src2_u64 v1 offset:65535 gds ; encoding: [0xff,0xff,0x8f,0xd9,0x01,0x00,0x00,0x00]
|
| H A D | gfx10_ds.txt | 2744 # GFX10: ds_min_src2_u64 v1 ; encoding: [0x00,0x00,0x1c,0xdb,0x01,0x00,0x00,0x00]
2747 # GFX10: ds_min_src2_u64 v1 offset:4 ; encoding: [0x04,0x00,0x1c,0xdb,0x01,0x00,0x00,0x00]
2750 # GFX10: ds_min_src2_u64 v1 offset:65535 ; encoding: [0xff,0xff,0x1c,0xdb,0x01,0x00,0x00,0x00]
2753 # GFX10: ds_min_src2_u64 v1 offset:65535 gds ; encoding: [0xff,0xff,0x1e,0xdb,0x01,0x00,0x00,0x00]
2756 # GFX10: ds_min_src2_u64 v255 offset:65535 ; encoding: [0xff,0xff,0x1c,0xdb,0xff,0x00,0x00,0x00]
|
| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | DSInstructions.td | 611 def DS_MIN_SRC2_U64 : DS_1A<"ds_min_src2_u64">;
|
| /llvm-project/llvm/docs/AMDGPU/ |
| H A D | AMDGPUAsmGFX7.rst | 115 …ds_min_src2_u64 :ref:`vaddr<amdgpu_synid_gfx7_vaddr_f20ee4>` …
|
| H A D | AMDGPUAsmGFX8.rst | 119 …ds_min_src2_u64 :ref:`vaddr<amdgpu_synid_gfx8_vaddr_f20ee4>` …
|
| H A D | AMDGPUAsmGFX9.rst | 119 …ds_min_src2_u64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr_f20ee4>` …
|
| H A D | AMDGPUAsmGFX10.rst | 333 …ds_min_src2_u64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` …
|