| /llvm-project/llvm/test/MC/AMDGPU/ |
| H A D | gfx1030_err.s | 69 ds_min_src2_i32 v1 offset:65535 label
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| H A D | gfx90a_err.s | 21 ds_min_src2_i32 v1 label
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| H A D | gfx7_asm_ds.s | 2523 ds_min_src2_i32 v1 offset:65535 label
2526 ds_min_src2_i32 v255 offset:65535 label
2529 ds_min_src2_i32 v1 label
2532 ds_min_src2_i32 v1 offset:0 label
2535 ds_min_src2_i32 v1 offset:4 label
2538 ds_min_src2_i32 v1 offset:65535 gds label
|
| H A D | gfx9_asm_ds.s | 2661 ds_min_src2_i32 v1 offset:65535 label
2664 ds_min_src2_i32 v255 offset:65535 label
2667 ds_min_src2_i32 v1 label
2670 ds_min_src2_i32 v1 offset:0 label
2673 ds_min_src2_i32 v1 offset:4 label
2676 ds_min_src2_i32 v1 offset:65535 gds label
|
| H A D | gfx8_asm_ds.s | 2475 ds_min_src2_i32 v1 offset:65535 label
2478 ds_min_src2_i32 v255 offset:65535 label
2481 ds_min_src2_i32 v1 label
2484 ds_min_src2_i32 v1 offset:0 label
2487 ds_min_src2_i32 v1 offset:4 label
2490 ds_min_src2_i32 v1 offset:65535 gds label
|
| H A D | gfx10_asm_ds.s | 6113 ds_min_src2_i32 v1 offset:65535 label
6116 ds_min_src2_i32 v255 offset:65535 label
6119 ds_min_src2_i32 v1 label
6122 ds_min_src2_i32 v1 offset:0 label
6125 ds_min_src2_i32 v1 offset:4 label
6128 ds_min_src2_i32 v1 offset:65535 gds label
|
| H A D | gfx11_unsupported.s | 103 ds_min_src2_i32 v1
100 ds_min_src2_i32 v1 global() label
|
| /llvm-project/llvm/test/MC/Disassembler/AMDGPU/ |
| H A D | gfx8_ds.txt | 2127 # CHECK: ds_min_src2_i32 v1 offset:65535 ; encoding: [0xff,0xff,0x0a,0xd9,0x01,0x00,0x00,0x…
2130 # CHECK: ds_min_src2_i32 v255 offset:65535 ; encoding: [0xff,0xff,0x0a,0xd9,0xff,0x00,0x00,0x…
2133 # CHECK: ds_min_src2_i32 v1 ; encoding: [0x00,0x00,0x0a,0xd9,0x01,0x00,0x00,0x…
2136 # CHECK: ds_min_src2_i32 v1 offset:4 ; encoding: [0x04,0x00,0x0a,0xd9,0x01,0x00,0x00,0x…
2139 # CHECK: ds_min_src2_i32 v1 offset:65535 gds ; encoding: [0xff,0xff,0x0b,0xd9,0x01,0x00,0x00,0x…
|
| H A D | gfx9_ds.txt | 2295 # CHECK: ds_min_src2_i32 v1 offset:65535 ; encoding: [0xff,0xff,0x0a,0xd9,0x01,0x00,0x00,0x00]
2298 # CHECK: ds_min_src2_i32 v255 offset:65535 ; encoding: [0xff,0xff,0x0a,0xd9,0xff,0x00,0x00,0x00]
2301 # CHECK: ds_min_src2_i32 v1 ; encoding: [0x00,0x00,0x0a,0xd9,0x01,0x00,0x00,0x00]
2304 # CHECK: ds_min_src2_i32 v1 offset:4 ; encoding: [0x04,0x00,0x0a,0xd9,0x01,0x00,0x00,0x00]
2307 # CHECK: ds_min_src2_i32 v1 offset:65535 gds ; encoding: [0xff,0xff,0x0b,0xd9,0x01,0x00,0x00,0x00]
|
| H A D | gfx10_ds.txt | 2699 # GFX10: ds_min_src2_i32 v1 ; encoding: [0x00,0x00,0x14,0xda,0x01,0x00,0x00,0x00]
2702 # GFX10: ds_min_src2_i32 v1 offset:4 ; encoding: [0x04,0x00,0x14,0xda,0x01,0x00,0x00,0x00]
2705 # GFX10: ds_min_src2_i32 v1 offset:65535 ; encoding: [0xff,0xff,0x14,0xda,0x01,0x00,0x00,0x00]
2708 # GFX10: ds_min_src2_i32 v1 offset:65535 gds ; encoding: [0xff,0xff,0x16,0xda,0x01,0x00,0x00,0x00]
2711 # GFX10: ds_min_src2_i32 v255 offset:65535 ; encoding: [0xff,0xff,0x14,0xda,0xff,0x00,0x00,0x00]
|
| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | DSInstructions.td | 594 def DS_MIN_SRC2_I32 : DS_1A<"ds_min_src2_i32">;
|
| /llvm-project/llvm/docs/AMDGPU/ |
| H A D | AMDGPUAsmGFX7.rst | 112 …ds_min_src2_i32 :ref:`vaddr<amdgpu_synid_gfx7_vaddr_f20ee4>` …
|
| H A D | AMDGPUAsmGFX8.rst | 116 …ds_min_src2_i32 :ref:`vaddr<amdgpu_synid_gfx8_vaddr_f20ee4>` …
|
| H A D | AMDGPUAsmGFX9.rst | 116 …ds_min_src2_i32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr_f20ee4>` …
|
| H A D | AMDGPUAsmGFX10.rst | 330 …ds_min_src2_i32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` …
|