| /llvm-project/llvm/test/MC/AMDGPU/ |
| H A D | gfx1030_err.s | 78 ds_max_src2_u32 v1 offset:65535 label
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| H A D | gfx90a_err.s | 30 ds_max_src2_u32 v1 label
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| H A D | gfx7_asm_ds.s | 2577 ds_max_src2_u32 v1 offset:65535 label
2580 ds_max_src2_u32 v255 offset:65535 label
2583 ds_max_src2_u32 v1 label
2586 ds_max_src2_u32 v1 offset:0 label
2589 ds_max_src2_u32 v1 offset:4 label
2592 ds_max_src2_u32 v1 offset:65535 gds label
|
| H A D | gfx9_asm_ds.s | 2715 ds_max_src2_u32 v1 offset:65535 label
2718 ds_max_src2_u32 v255 offset:65535 label
2721 ds_max_src2_u32 v1 label
2724 ds_max_src2_u32 v1 offset:0 label
2727 ds_max_src2_u32 v1 offset:4 label
2730 ds_max_src2_u32 v1 offset:65535 gds label
|
| H A D | gfx8_asm_ds.s | 2529 ds_max_src2_u32 v1 offset:65535 label
2532 ds_max_src2_u32 v255 offset:65535 label
2535 ds_max_src2_u32 v1 label
2538 ds_max_src2_u32 v1 offset:0 label
2541 ds_max_src2_u32 v1 offset:4 label
2544 ds_max_src2_u32 v1 offset:65535 gds label
|
| H A D | gfx10_asm_ds.s | 6167 ds_max_src2_u32 v1 offset:65535 label
6170 ds_max_src2_u32 v255 offset:65535 label
6173 ds_max_src2_u32 v1 label
6176 ds_max_src2_u32 v1 offset:0 label
6179 ds_max_src2_u32 v1 offset:4 label
6182 ds_max_src2_u32 v1 offset:65535 gds label
|
| H A D | gfx11_unsupported.s | 91 ds_max_src2_u32 v1
88 ds_max_src2_u32 v1 global() label
|
| /llvm-project/llvm/test/MC/Disassembler/AMDGPU/ |
| H A D | gfx8_ds.txt | 2172 # CHECK: ds_max_src2_u32 v1 offset:65535 ; encoding: [0xff,0xff,0x10,0xd9,0x01,0x00,0x00,0x…
2175 # CHECK: ds_max_src2_u32 v255 offset:65535 ; encoding: [0xff,0xff,0x10,0xd9,0xff,0x00,0x00,0x…
2178 # CHECK: ds_max_src2_u32 v1 ; encoding: [0x00,0x00,0x10,0xd9,0x01,0x00,0x00,0x…
2181 # CHECK: ds_max_src2_u32 v1 offset:4 ; encoding: [0x04,0x00,0x10,0xd9,0x01,0x00,0x00,0x…
2184 # CHECK: ds_max_src2_u32 v1 offset:65535 gds ; encoding: [0xff,0xff,0x11,0xd9,0x01,0x00,0x00,0x…
|
| H A D | gfx9_ds.txt | 2340 # CHECK: ds_max_src2_u32 v1 offset:65535 ; encoding: [0xff,0xff,0x10,0xd9,0x01,0x00,0x00,0x00]
2343 # CHECK: ds_max_src2_u32 v255 offset:65535 ; encoding: [0xff,0xff,0x10,0xd9,0xff,0x00,0x00,0x00]
2346 # CHECK: ds_max_src2_u32 v1 ; encoding: [0x00,0x00,0x10,0xd9,0x01,0x00,0x00,0x00]
2349 # CHECK: ds_max_src2_u32 v1 offset:4 ; encoding: [0x04,0x00,0x10,0xd9,0x01,0x00,0x00,0x00]
2352 # CHECK: ds_max_src2_u32 v1 offset:65535 gds ; encoding: [0xff,0xff,0x11,0xd9,0x01,0x00,0x00,0x00]
|
| H A D | gfx10_ds.txt | 2105 # GFX10: ds_max_src2_u32 v1 ; encoding: [0x00,0x00,0x20,0xda,0x01,0x00,0x00,0x00]
2108 # GFX10: ds_max_src2_u32 v1 offset:4 ; encoding: [0x04,0x00,0x20,0xda,0x01,0x00,0x00,0x00]
2111 # GFX10: ds_max_src2_u32 v1 offset:65535 ; encoding: [0xff,0xff,0x20,0xda,0x01,0x00,0x00,0x00]
2114 # GFX10: ds_max_src2_u32 v1 offset:65535 gds ; encoding: [0xff,0xff,0x22,0xda,0x01,0x00,0x00,0x00]
2117 # GFX10: ds_max_src2_u32 v255 offset:65535 ; encoding: [0xff,0xff,0x20,0xda,0xff,0x00,0x00,0x00]
|
| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | DSInstructions.td | 597 def DS_MAX_SRC2_U32 : DS_1A<"ds_max_src2_u32">;
|
| /llvm-project/llvm/docs/AMDGPU/ |
| H A D | AMDGPUAsmGFX7.rst | 96 …ds_max_src2_u32 :ref:`vaddr<amdgpu_synid_gfx7_vaddr_f20ee4>` …
|
| H A D | AMDGPUAsmGFX8.rst | 100 …ds_max_src2_u32 :ref:`vaddr<amdgpu_synid_gfx8_vaddr_f20ee4>` …
|
| H A D | AMDGPUAsmGFX9.rst | 100 …ds_max_src2_u32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr_f20ee4>` …
|
| H A D | AMDGPUAsmGFX10.rst | 314 …ds_max_src2_u32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` …
|