| /llvm-project/llvm/test/MC/AMDGPU/ |
| H A D | gfx1030_err.s | 66 ds_dec_src2_u32 v1 offset:65535 label
|
| H A D | gfx90a_err.s | 18 ds_dec_src2_u32 v1 label
|
| H A D | gfx7_asm_ds.s | 2505 ds_dec_src2_u32 v1 offset:65535 label
2508 ds_dec_src2_u32 v255 offset:65535 label
2511 ds_dec_src2_u32 v1 label
2514 ds_dec_src2_u32 v1 offset:0 label
2517 ds_dec_src2_u32 v1 offset:4 label
2520 ds_dec_src2_u32 v1 offset:65535 gds label
|
| H A D | gfx9_asm_ds.s | 2643 ds_dec_src2_u32 v1 offset:65535 label
2646 ds_dec_src2_u32 v255 offset:65535 label
2649 ds_dec_src2_u32 v1 label
2652 ds_dec_src2_u32 v1 offset:0 label
2655 ds_dec_src2_u32 v1 offset:4 label
2658 ds_dec_src2_u32 v1 offset:65535 gds label
|
| H A D | gfx8_asm_ds.s | 2457 ds_dec_src2_u32 v1 offset:65535 label
2460 ds_dec_src2_u32 v255 offset:65535 label
2463 ds_dec_src2_u32 v1 label
2466 ds_dec_src2_u32 v1 offset:0 label
2469 ds_dec_src2_u32 v1 offset:4 label
2472 ds_dec_src2_u32 v1 offset:65535 gds label
|
| H A D | gfx10_asm_ds.s | 6095 ds_dec_src2_u32 v1 offset:65535 label
6098 ds_dec_src2_u32 v255 offset:65535 label
6101 ds_dec_src2_u32 v1 label
6104 ds_dec_src2_u32 v1 offset:0 label
6107 ds_dec_src2_u32 v1 offset:4 label
6110 ds_dec_src2_u32 v1 offset:65535 gds label
|
| H A D | gfx11_unsupported.s | 67 ds_dec_src2_u32 v1
64 ds_dec_src2_u32 v1 global() label
|
| /llvm-project/llvm/test/MC/Disassembler/AMDGPU/ |
| H A D | gfx8_ds.txt | 2112 # CHECK: ds_dec_src2_u32 v1 offset:65535 ; encoding: [0xff,0xff,0x08,0xd9,0x01,0x00,0x00,0x…
2115 # CHECK: ds_dec_src2_u32 v255 offset:65535 ; encoding: [0xff,0xff,0x08,0xd9,0xff,0x00,0x00,0x…
2118 # CHECK: ds_dec_src2_u32 v1 ; encoding: [0x00,0x00,0x08,0xd9,0x01,0x00,0x00,0x…
2121 # CHECK: ds_dec_src2_u32 v1 offset:4 ; encoding: [0x04,0x00,0x08,0xd9,0x01,0x00,0x00,0x…
2124 # CHECK: ds_dec_src2_u32 v1 offset:65535 gds ; encoding: [0xff,0xff,0x09,0xd9,0x01,0x00,0x00,0x…
|
| H A D | gfx9_ds.txt | 2280 # CHECK: ds_dec_src2_u32 v1 offset:65535 ; encoding: [0xff,0xff,0x08,0xd9,0x01,0x00,0x00,0x00]
2283 # CHECK: ds_dec_src2_u32 v255 offset:65535 ; encoding: [0xff,0xff,0x08,0xd9,0xff,0x00,0x00,0x00]
2286 # CHECK: ds_dec_src2_u32 v1 ; encoding: [0x00,0x00,0x08,0xd9,0x01,0x00,0x00,0x00]
2289 # CHECK: ds_dec_src2_u32 v1 offset:4 ; encoding: [0x04,0x00,0x08,0xd9,0x01,0x00,0x00,0x00]
2292 # CHECK: ds_dec_src2_u32 v1 offset:65535 gds ; encoding: [0xff,0xff,0x09,0xd9,0x01,0x00,0x00,0x00]
|
| H A D | gfx10_ds.txt | 1169 # GFX10: ds_dec_src2_u32 v1 ; encoding: [0x00,0x00,0x10,0xda,0x01,0x00,0x00,0x00]
1172 # GFX10: ds_dec_src2_u32 v1 offset:4 ; encoding: [0x04,0x00,0x10,0xda,0x01,0x00,0x00,0x00]
1175 # GFX10: ds_dec_src2_u32 v1 offset:65535 ; encoding: [0xff,0xff,0x10,0xda,0x01,0x00,0x00,0x00]
1178 # GFX10: ds_dec_src2_u32 v1 offset:65535 gds ; encoding: [0xff,0xff,0x12,0xda,0x01,0x00,0x00,0x00]
1181 # GFX10: ds_dec_src2_u32 v255 offset:65535 ; encoding: [0xff,0xff,0x10,0xda,0xff,0x00,0x00,0x00]
|
| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | DSInstructions.td | 593 def DS_DEC_SRC2_U32 : DS_1A<"ds_dec_src2_u32">;
|
| /llvm-project/llvm/docs/AMDGPU/ |
| H A D | AMDGPUAsmGFX7.rst | 66 …ds_dec_src2_u32 :ref:`vaddr<amdgpu_synid_gfx7_vaddr_f20ee4>` …
|
| H A D | AMDGPUAsmGFX8.rst | 70 …ds_dec_src2_u32 :ref:`vaddr<amdgpu_synid_gfx8_vaddr_f20ee4>` …
|
| H A D | AMDGPUAsmGFX9.rst | 70 …ds_dec_src2_u32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr_f20ee4>` …
|
| H A D | AMDGPUAsmGFX10.rst | 284 …ds_dec_src2_u32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` …
|