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Searched refs:UndefElts (Results 1 – 25 of 26) sorted by relevance

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/llvm-project/llvm/lib/Target/X86/
H A DX86ShuffleDecodeConstantPool.cpp27 APInt &UndefElts, in extractConstantMask() argument
55 UndefElts = APInt(NumMaskElts, 0); in extractConstantMask()
67 UndefElts.setBit(i); in extractConstantMask()
104 UndefElts.setBit(i); in extractConstantMask()
123 APInt UndefElts; in DecodePSHUFBMask() local
125 if (!extractConstantMask(C, 8, UndefElts, RawMask)) in DecodePSHUFBMask()
133 if (UndefElts[i]) { in DecodePSHUFBMask()
162 APInt UndefElts; in DecodeVPERMILPMask() local
164 if (!extractConstantMask(C, ElSize, UndefElts, RawMask)) in DecodeVPERMILPMask()
173 if (UndefElts[i]) { in DecodeVPERMILPMask()
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H A DX86InstCombineIntrinsic.cpp2157 APInt UndefElts(Width, 0); in instCombineIntrinsic()
2159 return IC.SimplifyDemandedVectorElts(Op, DemandedElts, UndefElts); in instCombineIntrinsic()
3133 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, in simplifyDemandedVectorEltsIntrinsic()
3154 simplifyAndSetOp(&II, 0, DemandedElts, UndefElts); in simplifyDemandedVectorEltsIntrinsic()
3157 UndefElts = UndefElts[0]; in simplifyDemandedVectorEltsIntrinsic()
3163 simplifyAndSetOp(&II, 0, DemandedElts, UndefElts); in simplifyDemandedVectorEltsIntrinsic()
3183 simplifyAndSetOp(&II, 0, DemandedElts, UndefElts); in simplifyDemandedVectorEltsIntrinsic()
3198 UndefElts.clearBit(0); in simplifyDemandedVectorEltsIntrinsic()
3210 simplifyAndSetOp(&II, 0, DemandedElts2, UndefElts); in simplifyDemandedVectorEltsIntrinsic()
2149 APInt UndefElts(Width, 0); instCombineIntrinsic() local
3101 simplifyDemandedVectorEltsIntrinsic(InstCombiner & IC,IntrinsicInst & II,APInt DemandedElts,APInt & UndefElts,APInt & UndefElts2,APInt & UndefElts3,std::function<void (Instruction *,unsigned,APInt,APInt &)> simplifyAndSetOp) const simplifyDemandedVectorEltsIntrinsic() argument
[all...]
H A DX86TargetTransformInfo.h206 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
H A DX86ISelLowering.cpp4897 APInt &UndefElts, in getTargetConstantBitsFromNode()
4924 UndefElts = UndefSrcElts; in getTargetConstantBitsFromNode()
4941 UndefElts = APInt(NumElts, 0); in getTargetConstantBitsFromNode()
4952 UndefElts.setBit(i); in getTargetConstantBitsFromNode()
5164 UndefElts, EltBits, AllowWholeUndefs, in IsNOT()
5170 UndefElts = UndefElts.extractBits(NumSubElts, BaseIdx); in createPackShuffleMask()
5203 UndefElts = APInt::getZero(NumElts); in getPackDemandedElts()
5207 UndefElts.setBit(i); in getPackDemandedElts()
5211 UndefElts in getPackDemandedElts()
4738 getTargetConstantBitsFromNode(SDValue Op,unsigned EltSizeInBits,APInt & UndefElts,SmallVectorImpl<APInt> & EltBits,bool AllowWholeUndefs=true,bool AllowPartialUndefs=false) getTargetConstantBitsFromNode() argument
5069 APInt UndefElts; isConstantSplat() local
5098 getTargetShuffleMaskIndices(SDValue MaskNode,unsigned MaskEltSizeInBits,SmallVectorImpl<uint64_t> & RawMask,APInt & UndefElts) getTargetShuffleMaskIndices() argument
5135 APInt UndefElts; IsNOT() local
5796 APInt UndefElts; createShuffleMaskFromVSELECT() local
5863 APInt UndefElts; getFauxShuffleMask() local
23473 APInt UndefElts; LowerVSETCC() local
29436 APInt UndefElts; convertShiftLeftToScale() local
37496 APInt UndefElts; computeKnownBitsForTargetNode() local
39048 APInt UndefElts(NumMaskElts, 0); combineX86ShuffleChain() local
39589 APInt UndefElts(NumMaskElts, 0); combineX86ShufflesConstants() local
39999 APInt UndefElts; combineX86ShufflesRecursively() local
42076 APInt UndefElts; SimplifyDemandedVectorEltsForTargetNode() local
43287 isSplatValueForTargetNode(SDValue Op,const APInt & DemandedElts,APInt & UndefElts,const SelectionDAG & DAG,unsigned Depth) const isSplatValueForTargetNode() argument
43918 APInt UndefElts; combineBitcast() local
48359 auto &UndefElts = (Elt >= NumSrcEltsPerLane ? UndefElts1 : UndefElts0); combineVectorPack() local
48533 APInt UndefElts; combineVectorShiftVar() local
48649 APInt UndefElts; combineVectorShiftImm() local
49888 APInt UndefElts; combineAnd() local
49942 APInt UndefElts; combineAnd() local
50526 APInt UndefElts; combineOrXorWithSETCC() local
50671 APInt UndefElts; combineOr() local
52608 APInt UndefElts; isFNEG() local
53399 APInt UndefElts; combineAndnp() local
54367 APInt UndefElts; combineMOVMSK() local
54445 APInt UndefElts; combineMOVMSK() local
54582 BitVector UndefElts; combineGatherScatter() local
56532 APInt UndefElts = APInt::getZero(VT.getVectorNumElements()); combineConcatVectorOps() local
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H A DX86ISelLowering.h1327 APInt &UndefElts, const SelectionDAG &DAG,
/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86ShuffleDecode.h101 void DecodePSHUFBMask(ArrayRef<uint64_t> RawMask, const APInt &UndefElts,
125 void DecodeVPPERMMask(ArrayRef<uint64_t> RawMask, const APInt &UndefElts,
150 ArrayRef<uint64_t> RawMask, const APInt &UndefElts,
155 ArrayRef<uint64_t> RawMask, const APInt &UndefElts,
159 void DecodeVPERMVMask(ArrayRef<uint64_t> RawMask, const APInt &UndefElts,
163 void DecodeVPERMV3Mask(ArrayRef<uint64_t> RawMask, const APInt &UndefElts,
H A DX86ShuffleDecode.cpp293 void DecodePSHUFBMask(ArrayRef<uint64_t> RawMask, const APInt &UndefElts, in DecodePSHUFBMask()
297 if (UndefElts[i]) { in DecodePSHUFBMask()
325 void DecodeVPPERMMask(ArrayRef<uint64_t> RawMask, const APInt &UndefElts, in DecodeVPPERMMask()
343 if (UndefElts[i]) { in DecodeVPPERMMask()
478 ArrayRef<uint64_t> RawMask, const APInt &UndefElts, in DecodeVPERMILPMask()
488 if (UndefElts[i]) { in DecodeVPERMILPMask()
500 ArrayRef<uint64_t> RawMask, const APInt &UndefElts, in DecodeVPERMIL2PMask()
510 if (UndefElts[i]) { in DecodeVPERMIL2PMask()
545 void DecodeVPERMVMask(ArrayRef<uint64_t> RawMask, const APInt &UndefElts, in DecodeVPERMVMask()
549 if (UndefElts[ in DecodeVPERMVMask()
292 DecodePSHUFBMask(ArrayRef<uint64_t> RawMask,const APInt & UndefElts,SmallVectorImpl<int> & ShuffleMask) DecodePSHUFBMask() argument
324 DecodeVPPERMMask(ArrayRef<uint64_t> RawMask,const APInt & UndefElts,SmallVectorImpl<int> & ShuffleMask) DecodeVPPERMMask() argument
477 DecodeVPERMILPMask(unsigned NumElts,unsigned ScalarBits,ArrayRef<uint64_t> RawMask,const APInt & UndefElts,SmallVectorImpl<int> & ShuffleMask) DecodeVPERMILPMask() argument
499 DecodeVPERMIL2PMask(unsigned NumElts,unsigned ScalarBits,unsigned M2Z,ArrayRef<uint64_t> RawMask,const APInt & UndefElts,SmallVectorImpl<int> & ShuffleMask) DecodeVPERMIL2PMask() argument
544 DecodeVPERMVMask(ArrayRef<uint64_t> RawMask,const APInt & UndefElts,SmallVectorImpl<int> & ShuffleMask) DecodeVPERMVMask() argument
558 DecodeVPERMV3Mask(ArrayRef<uint64_t> RawMask,const APInt & UndefElts,SmallVectorImpl<int> & ShuffleMask) DecodeVPERMV3Mask() argument
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/llvm-project/llvm/unittests/CodeGen/
H A DAArch64SelectionDAGTest.cpp411 APInt UndefElts; in TEST_F()
413 EXPECT_FALSE(DAG->isSplatValue(Op, DemandedElts, UndefElts)); in TEST_F()
417 EXPECT_TRUE(DAG->isSplatValue(Op, DemandedElts, UndefElts)); in TEST_F()
435 APInt UndefElts; in TEST_F()
437 EXPECT_FALSE(DAG->isSplatValue(Op, DemandedElts, UndefElts)); in TEST_F()
441 EXPECT_TRUE(DAG->isSplatValue(Op, DemandedElts, UndefElts)); in TEST_F() local
455 APInt UndefElts; in TEST_F()
457 EXPECT_TRUE(DAG->isSplatValue(Op, DemandedElts, UndefElts)); in TEST_F()
475 APInt UndefElts; in TEST_F()
477 EXPECT_TRUE(DAG->isSplatValue(Op, DemandedElts, UndefElts)); in TEST_F()
397 APInt UndefElts; TEST_F() local
421 APInt UndefElts; TEST_F() local
461 APInt UndefElts; TEST_F() local
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/llvm-project/llvm/test/CodeGen/Hexagon/
H A Disel-splat-vector-dag-crash.ll3 ; This used to crash because SelectionDAG::isSplatValue did not set UndefElts
/llvm-project/llvm/include/llvm/Transforms/InstCombine/
H A DInstCombiner.h352 IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
519 SimplifyDemandedVectorElts(Value *V, APInt DemandedElts, APInt &UndefElts,
/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUTargetTransformInfo.h230 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
H A DAMDGPUInstCombineIntrinsic.cpp1539 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
1372 simplifyDemandedVectorEltsIntrinsic(InstCombiner & IC,IntrinsicInst & II,APInt DemandedElts,APInt & UndefElts,APInt & UndefElts2,APInt & UndefElts3,std::function<void (Instruction *,unsigned,APInt,APInt &)> SimplifyAndSetOp) const simplifyDemandedVectorEltsIntrinsic() argument
/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.h138 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
H A DAArch64TargetTransformInfo.cpp2535 APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, in getCastInstrCost()
2552 SimplifyAndSetOp(&II, 0, OrigDemandedElts, UndefElts); in getCastInstrCost()
2274 simplifyDemandedVectorEltsIntrinsic(InstCombiner & IC,IntrinsicInst & II,APInt OrigDemandedElts,APInt & UndefElts,APInt & UndefElts2,APInt & UndefElts3,std::function<void (Instruction *,unsigned,APInt,APInt &)> SimplifyAndSetOp) const simplifyDemandedVectorEltsIntrinsic() argument
/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.h125 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
H A DARMTargetTransformInfo.cpp280 APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, in simplifyDemandedVectorEltsIntrinsic()
296 SimplifyAndSetOp(&II, 0, OrigDemandedElts & DemandedElts, UndefElts); in simplifyDemandedVectorEltsIntrinsic()
298 UndefElts &= APInt::getSplat(NumElts, IsTop ? APInt::getLowBitsSet(2, 1) in simplifyDemandedVectorEltsIntrinsic()
261 simplifyDemandedVectorEltsIntrinsic(InstCombiner & IC,IntrinsicInst & II,APInt OrigDemandedElts,APInt & UndefElts,APInt & UndefElts2,APInt & UndefElts3,std::function<void (Instruction *,unsigned,APInt,APInt &)> SimplifyAndSetOp) const simplifyDemandedVectorEltsIntrinsic() argument
/llvm-project/llvm/include/llvm/Analysis/
H A DTargetTransformInfo.h703 APInt & UndefElts, APInt & UndefElts2, APInt & UndefElts3,
1982 APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3,
2498 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, in enableMaskedInterleavedAccessVectorization()
2503 IC, II, DemandedElts, UndefElts, UndefElts2, UndefElts3, in allowsMisalignedMemoryAccesses()
2318 simplifyDemandedVectorEltsIntrinsic(InstCombiner & IC,IntrinsicInst & II,APInt DemandedElts,APInt & UndefElts,APInt & UndefElts2,APInt & UndefElts3,std::function<void (Instruction *,unsigned,APInt,APInt &)> SimplifyAndSetOp) simplifyDemandedVectorEltsIntrinsic() argument
H A DTargetTransformInfoImpl.h224 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
207 simplifyDemandedVectorEltsIntrinsic(InstCombiner & IC,IntrinsicInst & II,APInt DemandedElts,APInt & UndefElts,APInt & UndefElts2,APInt & UndefElts3,std::function<void (Instruction *,unsigned,APInt,APInt &)> SimplifyAndSetOp) simplifyDemandedVectorEltsIntrinsic() argument
/llvm-project/llvm/lib/Analysis/
H A DTargetTransformInfo.cpp390 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, in getPeelingPreferences()
395 IC, II, DemandedElts, UndefElts, UndefElts2, UndefElts3, in isLegalAddImmediate()
375 simplifyDemandedVectorEltsIntrinsic(InstCombiner & IC,IntrinsicInst & II,APInt DemandedElts,APInt & UndefElts,APInt & UndefElts2,APInt & UndefElts3,std::function<void (Instruction *,unsigned,APInt,APInt &)> SimplifyAndSetOp) const simplifyDemandedVectorEltsIntrinsic() argument
/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp3030 APInt &UndefElts, unsigned Depth) const { in getValidShiftAmountRange()
3047 UndefElts = V.getOperand(0).isUndef() in getValidShiftAmountRange()
3061 UndefElts = UndefLHS | UndefRHS;
3070 return isSplatValue(V.getOperand(0), DemandedElts, UndefElts, Depth + 1); in getValidShiftAmount()
3074 return TLI->isSplatValueForTargetNode(V, DemandedElts, UndefElts, *this,
3086 UndefElts = APInt::getZero(NumElts); in getValidMinimumShiftAmount()
3094 UndefElts.setBit(i);
3113 UndefElts.setBit(i); in getValidMaximumShiftAmount()
3154 UndefElts = UndefSrcElts.extractBits(NumElts, Idx); in computeKnownBits()
3171 UndefElts in computeKnownBits()
2743 isSplatValue(SDValue V,const APInt & DemandedElts,APInt & UndefElts,unsigned Depth) const isSplatValue() argument
2932 APInt UndefElts; isSplatValue() local
2949 APInt UndefElts; getSplatSourceVector() local
[all...]
H A DDAGCombiner.cpp25971 APInt UndefElts; in visitVECTOR_SHUFFLE()
25972 if (DAG.isSplatValue(Shuf->getOperand(0), DemandedElts, UndefElts)) { in visitVECTOR_SHUFFLE()
25977 if (Idx < 0 || UndefElts[Idx]) in visitVECTOR_SHUFFLE()
25990 Idx = UndefElts[Idx] ? -1 : *MinNonUndefIdx; in visitVECTOR_SHUFFLE()
25407 APInt UndefElts; combineShuffleOfSplatVal() local
[all...]
/llvm-project/llvm/lib/IR/
H A DInstructions.cpp2089 APInt UndefElts = APInt::getZero(NumMaskElts); in isInsertSubvectorMask()
2098 UndefElts.setBit(i); in isInsertSubvectorMask()
2109 assert((Src0Elts | Src1Elts | UndefElts).isAllOnes() && in isInsertSubvectorMask()
2052 APInt UndefElts = APInt::getZero(NumMaskElts); isInsertSubvectorMask() local
/llvm-project/llvm/include/llvm/CodeGen/
H A DBasicTTIImpl.h736 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, in getMinPrefetchStride()
741 IC, II, DemandedElts, UndefElts, UndefElts2, UndefElts3, in getMaxPrefetchIterationsAhead()
698 simplifyDemandedVectorEltsIntrinsic(InstCombiner & IC,IntrinsicInst & II,APInt DemandedElts,APInt & UndefElts,APInt & UndefElts2,APInt & UndefElts3,std::function<void (Instruction *,unsigned,APInt,APInt &)> SimplifyAndSetOp) simplifyDemandedVectorEltsIntrinsic() argument
H A DSelectionDAG.h2179 /// On success \p UndefElts will indicate the elements that have UNDEF
2184 bool isSplatValue(SDValue V, const APInt &DemandedElts, APInt &UndefElts,
H A DTargetLowering.h4215 /// indicating any elements which may be undef in the output \p UndefElts.
4217 APInt &UndefElts,

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