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Searched refs:Sequential (Results 1 – 25 of 29) sorted by relevance

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/llvm-project/mlir/lib/Dialect/GPU/Transforms/
H A DParallelLoopMapper.cpp40 if (processor != gpu::Processor::Sequential && in setMappingAttr()
54 enum MappingLevel { MapGrid = 0, MapBlock = 1, Sequential = 2 }; enumerator
62 if (mappingLevel < Sequential) { in operator ++()
76 if (dimension >= kNumHardwareIds || level == Sequential) in getHardwareIdForMapping()
77 return Processor::Sequential; in getHardwareIdForMapping()
88 return Processor::Sequential; in getHardwareIdForMapping()
100 return Processor::Sequential; in getHardwareIdForMapping()
104 return Processor::Sequential; in getHardwareIdForMapping()
/llvm-project/llvm/lib/Support/
H A DParallel.cpp101 add(std::function<void ()> F,bool Sequential=false) add() argument
131 bool Sequential = hasSequentialTasks(); work() local
208 spawn(std::function<void ()> F,bool Sequential) spawn() argument
/llvm-project/mlir/include/mlir/Dialect/GPU/IR/
H A DParallelLoopMapperAttr.td26 def Sequential : I64EnumAttrCase<"Sequential", 6, "sequential">;
29 BlockX, BlockY, BlockZ, ThreadX, ThreadY, ThreadZ, Sequential]> {
/llvm-project/llvm/test/MachineVerifier/
H A Dtest_vector_reductions.mir28 ; CHECK: Bad machine code: Sequential FADD/FMUL vector reduction requires a scalar 1st operand
31 ; CHECK: Bad machine code: Sequential FADD/FMUL vector reduction must have a vector 2nd operand
/llvm-project/flang/runtime/
H A Dconnection.h23 enum class Access { Sequential, Direct, Stream }; enumerator
28 Access access{Access::Sequential}; // ACCESS='SEQUENTIAL', 'DIRECT', 'STREAM'
H A Dunit.cpp56 if (access == Access::Sequential) { in Emit()
226 if (anyWriteSinceLastPositioning_ && access == Access::Sequential) { in BeginReadingRecord()
234 if (access == Access::Sequential) { in FinishReadingRecord()
312 if (access == Access::Sequential) { in AdvanceRecord()
513 RUNTIME_CHECK(handler, access == Access::Sequential); in BeginSequentialVariableUnformattedInputRecord()
702 if (access == Access::Sequential && direction_ == Direction::Output) { in DoEndfile()
H A Dio-stmt.cpp336 unit().isUnformatted = unit().access != Access::Sequential; in EndIoStatement()
1114 case Access::Sequential: in Inquire()
1256 // "NO" for Direct, since Sequential would not work if in Inquire()
1259 : unit().access == Access::Sequential ? "YES" in Inquire()
H A Dio-api.cpp268 if (unit->access == Access::Sequential) { in BeginUnformattedIO()
702 open->set_access(Access::Sequential); in IODEF()
/llvm-project/flang/include/flang/Common/
H A DFortran.h52 Pending, Pos, Position, Read, Readwrite, Rec, Recl, Round, Sequential, Sign,
/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64Schedule.td90 // Sequential vector load and shuffle.
/llvm-project/llvm/include/llvm/Support/
H A DParallel.h98 // Tasks marked with \p Sequential will be executed
/llvm-project/mlir/include/mlir/Dialect/SCF/IR/
H A DSCFOps.td370 // Sequential context.
402 // Sequential context.
410 // Sequential context.
436 // Sequential context.
444 // Sequential context. Here `mapping` is expressed as GPU thread mapping
459 // Sequential context.
/llvm-project/llvm/include/llvm/Analysis/
H A DScalarEvolution.h646 bool Sequential = false);
648 bool Sequential = false);
745 bool Sequential = false);
750 bool Sequential = false);
/llvm-project/mlir/lib/Conversion/SCFToGPU/
H A DSCFToGPU.cpp357 return processor != gpu::Processor::Sequential; in isMappedToProcessor()
/llvm-project/flang/lib/Semantics/
H A Dcheck-io.cpp397 case ParseKind::Sequential: in Enter()
398 specKind = IoSpecKind::Sequential; in Enter()
/llvm-project/mlir/test/Target/LLVMIR/Import/
H A Dglobal-variables.ll177 ; Sequential constants.
/llvm-project/mlir/test/Integration/GPU/CUDA/sm90/
H A Dgemm_pred_f32_f16_f16_128x128x128.mlir18 // ## Sequential
H A Dgemm_f32_f16_f16_128x128x128.mlir18 // ## Sequential
/llvm-project/flang/lib/Parser/
H A Dio-parsers.cpp467 pure(InquireSpec::CharVar::Kind::Sequential),
/llvm-project/llvm/docs/
H A DAMDGPUOperandSyntax.rst86 **Non-Sequential Address (NSA) Syntax**
88 GFX10+ *image* instructions may use special *NSA* (Non-Sequential Address)
/llvm-project/llvm/lib/Analysis/
H A DScalarEvolution.cpp1886 return getUMinExpr(Operands, /*Sequential*/ true); in getSignExtendExpr()
4372 bool Sequential) { in getSMaxExpr()
4374 return getUMinExpr(Ops, Sequential); in getUMaxExpr()
4378 bool Sequential) {
4379 return Sequential ? getSequentialMinMaxExpr(scSequentialUMinExpr, Ops) in getUMaxExpr()
4792 bool Sequential) { in getTruncateOrNoop()
4794 return getUMinFromMismatchedTypes(Ops, Sequential); in getTruncateOrNoop()
4799 bool Sequential) { in getUMaxFromMismatchedTypes()
4820 return getUMinExpr(PromotedOps, Sequential); in getUMinFromMismatchedTypes()
6199 /*Sequential in createNodeForSelectViaUMinSeq()
4394 getUMinExpr(const SCEV * LHS,const SCEV * RHS,bool Sequential) getUMinExpr() argument
4400 getUMinExpr(SmallVectorImpl<const SCEV * > & Ops,bool Sequential) getUMinExpr() argument
4814 getUMinFromMismatchedTypes(const SCEV * LHS,const SCEV * RHS,bool Sequential) getUMinFromMismatchedTypes() argument
4821 getUMinFromMismatchedTypes(SmallVectorImpl<const SCEV * > & Ops,bool Sequential) getUMinFromMismatchedTypes() argument
[all...]
/llvm-project/llvm/unittests/Analysis/Inputs/ir2native_x86_64_model/
H A Dsaved_model.pbtxt8465 …Sequential\", \"name\": \"sequential\", \"trainable\": true, \"expects_training_arg\": true, \"dty…
/llvm-project/llvm/docs/Proposals/
H A DGitHubMove.rst122 - "Sequential IDs are important for LNT and llvmlab bisection tool." [MatthewsRevNum]_.
/llvm-project/flang/include/flang/Parser/
H A Dparse-tree.h2892 Readwrite, Round, Sequential, Sign, Stream, Status, Unformatted, Write,
/llvm-project/llvm/test/CodeGen/X86/
H A Dhorizontal-sum.ll510 ; Vectorized Sequential Sum Reductions

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