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Searched refs:MachineInstr (Results 1 – 25 of 932) sorted by relevance

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/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DCombinerHelper.h39 class MachineInstr;
53 MachineInstr *MI;
77 MachineInstr *Logic;
78 MachineInstr *Shift2;
163 void replaceOpcodeWith(MachineInstr &FromMI, unsigned ToOpcode) const;
179 bool tryCombineCopy(MachineInstr &MI) const;
180 bool matchCombineCopy(MachineInstr &MI) const;
181 void applyCombineCopy(MachineInstr &MI) const;
185 bool isPredecessor(const MachineInstr &DefMI,
186 const MachineInstr
38 class MachineInstr; global() variable
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H A DLegalizerHelper.h38 class MachineInstr;
95 LegalizeResult legalizeInstrStep(MachineInstr &MI,
99 LegalizeResult libcall(MachineInstr &MI, LostDebugLocObserver &LocObserver);
103 LegalizeResult narrowScalar(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy);
108 LegalizeResult widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
111 LegalizeResult bitcast(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
115 LegalizeResult lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
119 LegalizeResult fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
124 LegalizeResult moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
138 void widenScalarSrc(MachineInstr
37 class MachineInstr; global() variable
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/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.h34 class MachineInstr; variable
57 Register isLoadFromStackSlot(const MachineInstr &MI,
65 Register isStoreToStackSlot(const MachineInstr &MI,
72 const MachineInstr &MI,
79 const MachineInstr &MI,
188 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
197 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
205 bool expandPostRAPseudo(MachineInstr
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H A DHexagonVLIWPacketizer.h23 class MachineInstr; variable
29 std::vector<MachineInstr *> OldPacketMIs;
54 std::vector<MachineInstr*> IgnoreDepMIs;
89 bool ignorePseudoInstruction(const MachineInstr &MI,
94 bool isSoloInstruction(const MachineInstr &MI) override;
105 MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override;
108 bool shouldAddToPacket(const MachineInstr &MI) override;
119 bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType,
121 bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType,
124 bool canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU,
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/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNHazardRecognizer.h25 class MachineInstr; variable
34 typedef function_ref<bool(const MachineInstr &)> IsHazardFn;
43 MachineInstr *CurrCycleInstr;
44 std::list<MachineInstr*> EmittedInstrs;
65 void addClauseInst(const MachineInstr &MI);
69 unsigned getMFMAPipelineWaitStates(const MachineInstr &MI) const;
71 // Advance over a MachineInstr bundle. Look for hazards in the bundled
77 void runOnInstruction(MachineInstr *MI);
83 int checkSoftClauseHazards(MachineInstr *SMEM);
84 int checkSMRDHazards(MachineInstr *SMR
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H A DAMDGPULegalizerInfo.h37 bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI,
44 bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI,
46 bool legalizeFroundeven(MachineInstr &MI, MachineRegisterInfo &MRI,
48 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
50 bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI,
52 bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
54 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
56 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
58 bool legalizeMinNumMaxNum(LegalizerHelper &Helper, MachineInstr &MI) const;
59 bool legalizeExtractVectorElt(MachineInstr
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H A DAMDGPUInstructionSelector.h39 class MachineInstr; variable
58 bool select(MachineInstr &I) override;
74 bool isInstrUniform(const MachineInstr &MI) const;
82 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
88 bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
89 bool selectCOPY(MachineInstr &I) const;
90 bool selectCOPY_SCC_VCC(MachineInstr &I) const;
91 bool selectCOPY_VCC_SCC(MachineInstr &I) const;
92 bool selectReadAnyLane(MachineInstr &I) const;
93 bool selectPHI(MachineInstr
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H A DSIInstrInfo.h54 void insert(MachineInstr *MI); in top()
56 MachineInstr *top() const { in top()
73 bool isDeferred(MachineInstr *MI); in getDeferredList()
75 SetVector<MachineInstr *> &getDeferredList() { return DeferredList; }
79 SetVector<MachineInstr *> InstrList;
80 /// Deferred instructions are specific MachineInstr
82 SetVector<MachineInstr *> DeferredList;
103 using SetVectorType = SmallSetVector<MachineInstr *, 32>;
121 void swapOperands(MachineInstr &Inst) const;
124 moveScalarAddSub(SIInstrWorklist &Worklist, MachineInstr
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H A DR600InstrInfo.h34 class MachineInstr; variable
44 ExtractSrcs(MachineInstr &MI, const DenseMap<unsigned, unsigned> &PV,
92 bool canBeConsideredALU(const MachineInstr &MI) const;
95 bool isTransOnly(const MachineInstr &MI) const;
97 bool isVectorOnly(const MachineInstr &MI) const;
101 bool usesVertexCache(const MachineInstr &MI) const;
103 bool usesTextureCache(const MachineInstr &MI) const;
106 bool usesAddressRegister(MachineInstr &MI) const;
107 bool definesAddressRegister(MachineInstr &MI) const;
108 bool readsLDSSrcReg(const MachineInstr
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/llvm-project/llvm/lib/Target/X86/
H A DX86InstrInfo.h39 AC_EVEX_2_LEGACY = MachineInstr::TAsmComments,
60 CondCode getCondFromMI(const MachineInstr &MI);
63 CondCode getCondFromBranch(const MachineInstr &MI);
66 CondCode getCondFromSETCC(const MachineInstr &MI);
69 CondCode getCondFromCMov(const MachineInstr &MI);
72 CondCode getCondFromCFCMov(const MachineInstr &MI);
75 CondCode getCondFromCCMP(const MachineInstr &MI);
106 bool isX87Instruction(MachineInstr &MI);
112 int getFirstAddrOperandIdx(const MachineInstr &MI);
115 const Constant *getConstantFromPool(const MachineInstr
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H A DX86AsmPrinter.h82 void LowerSTACKMAP(const MachineInstr &MI);
83 void LowerPATCHPOINT(const MachineInstr &MI, X86MCInstLower &MCIL);
84 void LowerSTATEPOINT(const MachineInstr &MI, X86MCInstLower &MCIL);
85 void LowerFAULTING_OP(const MachineInstr &MI, X86MCInstLower &MCIL);
86 void LowerPATCHABLE_OP(const MachineInstr &MI, X86MCInstLower &MCIL);
88 void LowerTlsAddr(X86MCInstLower &MCInstLowering, const MachineInstr &MI);
91 void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI,
93 void LowerPATCHABLE_RET(const MachineInstr &MI, X86MCInstLower &MCIL);
94 void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI, X86MCInstLower &MCIL);
95 void LowerPATCHABLE_EVENT_CALL(const MachineInstr &MI, X86MCInstLower &MCIL);
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/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h25 #include "llvm/CodeGen/MachineInstr.h"
141 virtual bool isGlobalMemoryObject(const MachineInstr *MI) const;
148 bool isTriviallyReMaterializable(const MachineInstr &MI) const { in isTriviallyReMaterializable()
161 virtual bool isSafeToSink(MachineInstr &MI, MachineBasicBlock *SuccToSinkTo,
168 virtual bool shouldBreakCriticalEdgeToSink(MachineInstr &MI) const {
179 virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const;
196 virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
225 bool isFrameInstr(const MachineInstr &I) const {
231 bool isFrameSetup(const MachineInstr
784 createRemainingIterationsGreaterCondition(int TC,MachineBasicBlock & MBB,SmallVectorImpl<MachineOperand> & Cond,DenseMap<MachineInstr *,MachineInstr * > & LastStage0Insts) createRemainingIterationsGreaterCondition() argument
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H A DReachingDefAnalysis.h34 class MachineInstr; variable
141 DenseMap<MachineInstr *, int> InstIds;
155 using InstSet = SmallPtrSetImpl<MachineInstr*>;
192 int getReachingDef(MachineInstr *MI, Register Reg) const;
195 bool hasSameReachingDef(MachineInstr *A, MachineInstr *B, Register Reg) const;
199 bool isReachingDefLiveOut(MachineInstr *MI, Register Reg) const;
203 MachineInstr *getLocalLiveOutMIDef(MachineBasicBlock *MBB,
206 /// If a single MachineInstr creates the reaching definition, then return it.
208 MachineInstr *getUniqueReachingMIDe
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H A DModuloSchedule.h75 class MachineInstr; variable
88 std::vector<MachineInstr *> ScheduledInstrs;
91 DenseMap<MachineInstr *, int> Cycle;
94 DenseMap<MachineInstr *, int> Stage;
108 std::vector<MachineInstr *> ScheduledInstrs, in ModuloSchedule()
109 DenseMap<MachineInstr *, int> Cycle, in ModuloSchedule() argument
110 DenseMap<MachineInstr *, int> Stage) in ModuloSchedule()
135 int getStage(MachineInstr *MI) { in getStage()
141 int getCycle(MachineInstr *MI) { in getCycle()
147 void setStage(MachineInstr *M
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H A DLiveVariables.h37 #include "llvm/CodeGen/MachineInstr.h"
88 std::vector<MachineInstr*> Kills;
93 bool removeKill(MachineInstr &MI) {
94 std::vector<MachineInstr *>::iterator I = find(Kills, &MI);
102 MachineInstr *findKill(const MachineBasicBlock *MBB) const;
131 std::vector<MachineInstr *> PhysRegDef;
136 std::vector<MachineInstr *> PhysRegUse;
142 DenseMap<MachineInstr*, unsigned> DistanceMap;
152 bool HandlePhysRegKill(Register Reg, MachineInstr *MI);
157 void HandlePhysRegUse(Register Reg, MachineInstr
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/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.h70 Register isLoadFromStackSlot(const MachineInstr &MI,
72 Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex,
74 Register isStoreToStackSlot(const MachineInstr &MI,
76 Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex,
79 bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
81 bool shouldBreakCriticalEdgeToSink(MachineInstr &MI) const override {
99 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
105 MachineInstr::MIFlag Flags = MachineInstr
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/llvm-project/llvm/lib/Target/Mips/
H A DMipsRegisterBankInfo.h36 getInstrMapping(const MachineInstr &MI) const override;
48 void setRegBank(MachineInstr &MI, MachineRegisterInfo &MRI) const;
123 SmallVector<MachineInstr *, 2> DefUses;
124 SmallVector<MachineInstr *, 2> UseDefs;
134 MachineInstr *skipCopiesOutgoing(MachineInstr *MI) const;
141 MachineInstr *skipCopiesIncoming(MachineInstr *MI) const;
144 AmbiguousRegDefUseContainer(const MachineInstr *MI);
145 SmallVectorImpl<MachineInstr *>
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/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h185 SmallVectorImpl<MachineInstr *> &NewMIs) const;
189 SmallVectorImpl<MachineInstr *> &NewMIs) const;
193 bool simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
194 unsigned OpNoForForwarding, MachineInstr **KilledDef) const;
197 bool transformToNewImmFormFedByAdd(MachineInstr &MI, MachineInstr &DefMI,
201 bool transformToImmFormFedByLI(MachineInstr &MI, const ImmInstrInfo &III,
203 MachineInstr &DefMI) const;
206 bool transformToImmFormFedByAdd(MachineInstr
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/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.h188 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
190 bool isAsCheapAsAMove(const MachineInstr &MI) const override;
192 bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,
196 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
197 const MachineInstr &MIb) const override;
199 Register isLoadFromStackSlot(const MachineInstr &MI,
201 Register isStoreToStackSlot(const MachineInstr &MI,
205 static bool isGPRZero(const MachineInstr &MI);
208 static bool isGPRCopy(const MachineInstr &MI);
211 static bool isFPRCopy(const MachineInstr
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/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.h191 void expandRIPseudo(MachineInstr &MI, unsigned LowOpcode, unsigned HighOpcode,
193 void expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,
195 void expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,
197 void expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode,
199 void expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
201 void expandLoadStackGuard(MachineInstr *MI) const;
223 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
231 Register isLoadFromStackSlot(const MachineInstr &MI,
233 Register isStoreToStackSlot(const MachineInstr
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H A DSystemZElimCompare.cpp25 #include "llvm/CodeGen/MachineInstr.h"
81 Reference getRegReferences(MachineInstr &MI, unsigned Reg);
82 bool convertToBRCT(MachineInstr &MI, MachineInstr &Compare,
83 SmallVectorImpl<MachineInstr *> &CCUsers);
84 bool convertToLoadAndTrap(MachineInstr &MI, MachineInstr &Compare,
85 SmallVectorImpl<MachineInstr *> &CCUsers);
86 bool convertToLoadAndTest(MachineInstr &MI, MachineInstr
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/llvm-project/llvm/lib/Target/ARC/
H A DARCOptAddrMode.cpp77 MachineInstr *tryToCombine(MachineInstr &Ldst);
80 bool noUseOfAddBeforeLoadOrStore(const MachineInstr *Add,
81 const MachineInstr *Ldst);
85 bool canHoistLoadStoreTo(MachineInstr *Ldst, MachineInstr *To);
95 MachineInstr *canJoinInstructions(MachineInstr *Ldst, MachineInstr *Add,
96 SmallVectorImpl<MachineInstr *> *Uses);
100 bool canFixPastUses(const ArrayRef<MachineInstr *> &Uses,
105 void fixPastUses(ArrayRef<MachineInstr *> Uses, unsigned BaseReg,
111 void changeToAddrMode(MachineInstr &Ldst, unsigned NewOpcode,
134 static bool isAddConstantOp(const MachineInstr &MI, int64_t &Amount) { in isAddConstantOp()
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/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.h30 bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI,
34 MachineInstr &MI) const override;
37 bool legalizeVaArg(MachineInstr &MI, MachineRegisterInfo &MRI,
39 bool legalizeLoadStore(MachineInstr &MI, MachineRegisterInfo &MRI,
42 bool legalizeShlAshrLshr(MachineInstr &MI, MachineRegisterInfo &MRI,
46 bool legalizeSmallCMGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI,
49 bool legalizeBitfieldExtract(MachineInstr &MI, MachineRegisterInfo &MRI,
51 bool legalizeRotate(MachineInstr &MI, MachineRegisterInfo &MRI,
53 bool legalizeICMP(MachineInstr &MI, MachineRegisterInfo &MRI,
55 bool legalizeFunnelShift(MachineInstr
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/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h22 #include "llvm/CodeGen/MachineInstr.h"
66 const MachineInstr &MI, unsigned DefIdx,
79 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
95 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
106 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
113 isCopyInstrImpl(const MachineInstr &MI) const override;
118 describeLoadedValue(const MachineInstr &MI, Register Reg) const override;
128 MachineInstr *convertToThreeAddress(MachineInstr
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/llvm-project/llvm/lib/CodeGen/
H A DImplicitNullChecks.cpp38 #include "llvm/CodeGen/MachineInstr.h"
81 static bool canHandle(const MachineInstr *MI);
86 bool canReorder(const MachineInstr *A, const MachineInstr *B);
99 std::optional<ArrayRef<MachineInstr *>::iterator> PotentialDependence;
103 std::optional<ArrayRef<MachineInstr *>::iterator> PotentialDependence) in DependenceResult()
115 DependenceResult computeDependence(const MachineInstr *MI,
116 ArrayRef<MachineInstr *> Block);
121 MachineInstr *MemOperation;
124 MachineInstr *CheckOperatio
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