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Searched refs:AddSubOpc (Results 1 – 6 of 6) sorted by relevance

/llvm-project/llvm/lib/Target/ARM/
H A DMLxExpansionPass.cpp68 unsigned MulOpc, unsigned AddSubOpc,
270 unsigned MulOpc, unsigned AddSubOpc, in ExpandFPMLxInstruction() argument
285 const MCInstrDesc &MCID2 = TII->get(AddSubOpc); in ExpandFPMLxInstruction()
354 unsigned MulOpc, AddSubOpc; in ExpandFPMLxInstructions() local
357 MulOpc, AddSubOpc, NegAcc, HasLane) || in ExpandFPMLxInstructions()
361 ExpandFPMLxInstruction(MBB, MI, MulOpc, AddSubOpc, NegAcc, HasLane); in ExpandFPMLxInstructions()
H A DARMBaseInstrInfo.h519 unsigned &AddSubOpc, bool &NegAcc,
H A DARMBaseInstrInfo.cpp86 uint16_t AddSubOpc; // Expanded add / sub opcode
92 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
120 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc); in ARMBaseInstrInfo()
5023 unsigned &AddSubOpc,
5031 AddSubOpc = Entry.AddSubOpc;
88 uint16_t AddSubOpc; // Expanded add / sub opcode global() member
5007 isFpMLxInstruction(unsigned Opcode,unsigned & MulOpc,unsigned & AddSubOpc,bool & NegAcc,bool & HasLane) const isFpMLxInstruction() argument
/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerCombiner.cpp185 unsigned ShiftAmt, AddSubOpc; in matchAArch64MulConstCombine() local
199 AddSubOpc = TargetOpcode::G_ADD; in matchAArch64MulConstCombine()
202 AddSubOpc = TargetOpcode::G_SUB; in matchAArch64MulConstCombine()
212 AddSubOpc = TargetOpcode::G_SUB; in matchAArch64MulConstCombine()
216 AddSubOpc = TargetOpcode::G_ADD; in matchAArch64MulConstCombine()
231 auto Res = B.buildInstr(AddSubOpc, {Ty}, {AddSubLHS, AddSubRHS}); in matchAArch64MulConstCombine()
/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp14792 unsigned AddSubOpc; in canFoldToVW_W()
14799 AddSubOpc = V->getOpcode();
14800 if ((AddSubOpc == ISD::ADD || AddSubOpc == ISD::SUB) && V->hasOneUse()) { in canFoldToVWWithSEXT()
14803 if (AddSubOpc == ISD::SUB) in canFoldToVWWithSEXT()
14813 return DAG.getNode(AddSubOpc, DL, VT, N1, MulVal); in canFoldToVWWithZEXT()
14818 return DAG.getNode(AddSubOpc, DL, VT, N0, MulVal);
14031 unsigned AddSubOpc; performMULCombine() local
/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp18738 unsigned AddSubOpc; in performSVEAndCombine()
18741 AddSubOpc = V->getOpcode(); in performSVEAndCombine()
18742 if ((AddSubOpc == ISD::ADD || AddSubOpc == ISD::SUB) && V->hasOneUse()) { in performSVEAndCombine()
18745 if (AddSubOpc == ISD::SUB) in performSVEAndCombine()
18755 return DAG.getNode(AddSubOpc, DL, VT, N1, MulVal); in performSVEAndCombine()
18760 return DAG.getNode(AddSubOpc, DL, VT, N0, MulVal); in performSVEAndCombine()
18051 unsigned AddSubOpc; performMulCombine() local
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