Searched refs:hasImplicitDefOfPhysReg (Results 1 – 12 of 12) sorted by relevance
32 bool MCInstrDesc::hasImplicitDefOfPhysReg(unsigned Reg, in hasImplicitDefOfPhysReg() function in MCInstrDesc51 return hasImplicitDefOfPhysReg(Reg, &RI); in hasDefOfPhysReg()
593 bool hasImplicitDefOfPhysReg(unsigned Reg,
767 (Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) || in printRegularOperand() 768 Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO)); in printRegularOperand() 784 (Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) || in printRegularOperand() 785 Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO))) in printRegularOperand()
359 Desc.hasImplicitDefOfPhysReg(AMDGPU::EXEC); in encodeInstruction()
146 !TII->get(DstOpcode).hasImplicitDefOfPhysReg(MO.getReg())) in isLegal()
10568 MI.getDesc().hasImplicitDefOfPhysReg(X86::RSP)) in buildClearRegister() 10574 MI.getDesc().hasImplicitDefOfPhysReg(X86::RIP)) in buildClearRegister()
132 if (ResNo >= II.getNumDefs() && II.hasImplicitDefOfPhysReg(Reg)) in CheckForPhysRegDependency()
250 !DefMIDesc.hasImplicitDefOfPhysReg(Reg)); in addPhysRegDataDeps()
1384 get(MemOpcode).hasImplicitDefOfPhysReg(SystemZ::CC))) in expandPostRAPseudo() 1557 if (get(RegMemOpcode).hasImplicitDefOfPhysReg(SystemZ::CC)) { in getBranchInfo()
4726 if (MCID.isCall() || (MCID.hasImplicitDefOfPhysReg(ARM::CPSR) && in getPredicationCost() 4756 if (PredCost && (MCID.isCall() || (MCID.hasImplicitDefOfPhysReg(ARM::CPSR) && in getInstrLatency()
2902 MI.getDesc().hasImplicitDefOfPhysReg(RISCV::X5)) in commuteInstructionImpl()
16493 if (II.isCompare() && II.hasImplicitDefOfPhysReg(AMDGPU::SCC)) {