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Searched refs:getCondCode (Results 1 – 17 of 17) sorted by relevance

/freebsd-src/contrib/llvm-project/llvm/lib/Target/MSP430/Disassembler/
H A DMSP430Disassembler.cpp324 static MSP430CC::CondCodes getCondCode(unsigned Cond) { in getCondCode() function
353 MI.addOperand(MCOperand::createImm(getCondCode(Cond))); in getInstructionCJ()
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp749 DAG.getCondCode(ISD::SETEQ)); in lowerFP_TO_UINT()
759 DAG.getCondCode(ISD::SETEQ)); in lowerFP_TO_SINT()
837 CC = DAG.getCondCode(InverseCC); in LowerSELECT_CC()
843 CC = DAG.getCondCode(SwapInvCC); in LowerSELECT_CC()
871 CC = DAG.getCondCode(CCSwapped); in LowerSELECT_CC()
879 CC = DAG.getCondCode(CCSwapped); in LowerSELECT_CC()
911 DAG.getCondCode(CCOpcode)); in LowerSELECT_CC()
937 DAG.getCondCode(ISD::SETNE)); in LowerSELECT_CC()
H A DSIISelLowering.cpp6041 DAG.getCondCode(CCOpcode)); in ReplaceNodeResults()
6070 Src1, DAG.getCondCode(CCOpcode)); in findUser()
6110 DAG.getConstant(0, SL, MVT::i32), DAG.getCondCode(ISD::SETNE)); in shouldEmitGOTReloc()
/freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h828 SDValue getCondCode(ISD::CondCode Cond);
1242 {VT, MVT::Other}, {Chain, LHS, RHS, getCondCode(Cond)});
1243 return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
1254 return getNode(ISD::VP_SETCC, DL, VT, LHS, RHS, getCondCode(Cond), Mask,
1273 False, getCondCode(Cond));
/freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeFloatTypes.cpp1111 DAG.getCondCode(CCCode), NewLHS, NewRHS,
1196 DAG.getCondCode(CCCode)), in SoftenFloatOp_FCOPYSIGN()
1218 NewRHS, DAG.getCondCode(CCCode)); in SoftenFloatOp_Unary()
1221 DAG.getCondCode(CCCode)), 0);
2164 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandFloatOp_LLRINT()
2249 DAG.getCondCode(CCCode)), 0); in PromoteFloatOperand()
H A DLegalizeIntegerTypes.cpp5390 LHSHi, RHSHi, DAG.getCondCode(CCCode)); in ExpandIntOp_RETURNADDR()
5447 DAG.getCondCode(CCCode)); in ExpandIntOp_STORE()
5476 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandIntOp_STORE()
5495 DAG.getCondCode(CCCode)), 0); in ExpandIntOp_STORE()
5512 DAG.UpdateNodeOperands(N, NewLHS, NewRHS, DAG.getCondCode(CCCode)), 0); in ExpandIntOp_ATOMIC_STORE()
H A DLegalizeDAG.cpp4088 DAG.getCondCode(ISD::SETNE), Tmp3, in ExpandNode()
4234 CC = DAG.getCondCode(ISD::SETNE); in ExpandNode()
4266 Tmp4 = DAG.getCondCode(NeedInvert ? ISD::SETEQ : ISD::SETNE); in ExpandNode()
H A DTargetLowering.cpp9191 DAG.getCondCode(ISD::SETNE), Mask, EVL); in expandBITREVERSE()
10291 {Op0, Op1, DAG.getCondCode(CC)})) { in expandFixedPointMul()
10298 {Op0, Op1, DAG.getCondCode(CC)})) { in expandFixedPointDiv()
11557 CC = DAG.getCondCode(InvCC);
11570 CC = DAG.getCondCode(InvCC);
H A DSelectionDAGBuilder.cpp8227 Opers.push_back(DAG.getCondCode(Condition)); in lowerEndEH()
H A DSelectionDAG.cpp2017 SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { in getElementCount()
1981 SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { getCondCode() function in SelectionDAG
/freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp2979 {Src, Src, DAG.getCondCode(ISD::SETNE), in lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND()
3089 {Abs, MaxValSplat, DAG.getCondCode(ISD::SETOLT), in lowerFTRUNC_FCEIL_FFLOOR_FROUND()
3171 {Chain, Src, Src, DAG.getCondCode(ISD::SETUNE), in getExactInteger()
3198 {Abs, MaxValSplat, DAG.getCondCode(ISD::SETOLT), Mask, Mask, VL}); in isSimpleVIDSequence()
5541 {Source, AllZero, DAG.getCondCode(ISD::SETNE), in lowerFMAXIMUM_FMINIMUM()
5834 {FPCLASS, TDCMaskV, DAG.getCondCode(ISD::SETEQ),
5846 {AND, SplatZero, DAG.getCondCode(ISD::SETNE), in LowerOperation()
5918 {X, X, DAG.getCondCode(ISD::SETOEQ), in LowerOperation()
5927 {Y, Y, DAG.getCondCode(ISD::SETOEQ), in LowerOperation()
7807 SDValue SetNE = DAG.getCondCode(IS in lowerVectorFPExtendOrRoundLike()
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp983 ARMCC::CondCodes getCondCode() const { in getRegList()
2464 ARMCC::CondCodes CC = getCondCode();
2471 ARMCC::CondCodes CC = getCondCode(); in addCondCodeOperands()
2478 ARMCC::CondCodes CC = getCondCode(); in addVPTPredNOperands()
2486 ARMCC::CondCodes CC = getCondCode(); in addVPTPredROperands()
2493 ARMCC::CondCodes CC = getCondCode(); in addVPTPredROperands()
2534 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addCCOutOperands()
2535 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; in addCCOutOperands()
2586 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addDPRRegListOperands()
2591 Inst.addOperand(MCOperand::createImm(unsigned(ARMCC::getOppositeCondition(getCondCode()))));
957 ARMCC::CondCodes getCondCode() const { getCondCode() function in __anon9358e9b20111::ARMOperand
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp631 AArch64CC::CondCode getCondCode() const {
1958 Inst.addOperand(MCOperand::createImm(getCondCode())); in addUImm6Operands()
2562 OS << "<condcode " << getCondCode() << ">"; in print()
627 AArch64CC::CondCode getCondCode() const { getCondCode() function in __anon58533a440111::AArch64Operand
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp21051 N->getOperand(2), Splat, DAG.getCondCode(CC)); in performGLD1Combine()
21454 N->getOperand(3), DAG.getCondCode(ISD::SETUGE)); in combineBoolVectorAndTruncateStore()
21460 N->getOperand(3), DAG.getCondCode(ISD::SETUGT)); in combineBoolVectorAndTruncateStore()
21466 N->getOperand(3), DAG.getCondCode(ISD::SETGE)); in combineBoolVectorAndTruncateStore()
21472 N->getOperand(3), DAG.getCondCode(ISD::SETGT)); in combineBoolVectorAndTruncateStore()
21478 N->getOperand(3), DAG.getCondCode(ISD::SETEQ)); in isHalvingTruncateOfLegalScalableType()
21484 N->getOperand(3), DAG.getCondCode(ISD::SETNE)); in performSTORECombine()
21489 N->getOperand(3), DAG.getCondCode(ISD::SETUO)); in performSTORECombine()
24220 SetCC.getOperand(2) == DAG.getCondCode(ISD::SETGT)) { in mayBeEmittedAsTailCall()
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp6820 DAG.getCondCode(ISD::SETEQ)); in LowerVSETCC()
9317 DAG.getCondCode(ISD::SETNE)); in LowerTruncate()
10532 DAG.getCondCode(CC)); in LowerFSETCC()
/freebsd-src/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp3744 DAG.getCondCode(CC)); in LowerVAARG()
/freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp23115 SDValue CC = DAG.getCondCode(Cond); in LowerVSETCC()
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