| /freebsd-src/crypto/openssl/crypto/sm3/ |
| H A D | sm3.c | 35 W08, W09, W10, W11, W12, W13, W14, W15; in ossl_sm3_block_data_order() local
67 (void)HOST_c2l(data, W15); in ossl_sm3_block_data_order()
74 W02 = EXPAND(W02, W09, W15, W05, W12); in ossl_sm3_block_data_order()
80 W05 = EXPAND(W05, W12, W02, W08, W15); in ossl_sm3_block_data_order()
86 W08 = EXPAND(W08, W15, W05, W11, W02); in ossl_sm3_block_data_order()
91 R1(B, C, D, A, F, G, H, E, 0x6228CBCE, W11, W11 ^ W15); in ossl_sm3_block_data_order()
94 W12 = EXPAND(W12, W03, W09, W15, W06); in ossl_sm3_block_data_order()
99 R1(B, C, D, A, F, G, H, E, 0x228CBCE6, W15, W15 ^ W03); in ossl_sm3_block_data_order()
100 W15 = EXPAND(W15, W06, W12, W02, W09); in ossl_sm3_block_data_order()
106 W02 = EXPAND(W02, W09, W15, W05, W12); in ossl_sm3_block_data_order()
[all …]
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| /freebsd-src/contrib/llvm-project/llvm/lib/Support/ |
| H A D | SHA256.cpp | 89 uint32_t W15 = InternalState.Buffer.L[15]; in hashBlock() local
92 F_EXPAND(H, A, B, C, D, E, F, G, W01, W15, W10, W02, 0x71374491); in hashBlock()
97 F_EXPAND(C, D, E, F, G, H, A, B, W06, W04, W15, W07, 0x923F82A4); in hashBlock()
105 F_EXPAND(C, D, E, F, G, H, A, B, W14, W12, W07, W15, 0x9BDC06A7); in hashBlock()
106 F_EXPAND(B, C, D, E, F, G, H, A, W15, W13, W08, W00, 0xC19BF174); in hashBlock()
109 F_EXPAND(H, A, B, C, D, E, F, G, W01, W15, W10, W02, 0xEFBE4786); in hashBlock()
114 F_EXPAND(C, D, E, F, G, H, A, B, W06, W04, W15, W07, 0x5CB0A9DC); in hashBlock()
122 F_EXPAND(C, D, E, F, G, H, A, B, W14, W12, W07, W15, 0x06CA6351); in hashBlock()
123 F_EXPAND(B, C, D, E, F, G, H, A, W15, W13, W08, W00, 0x14292967); in hashBlock()
126 F_EXPAND(H, A, B, C, D, E, F, G, W01, W15, W10, W02, 0x2E1B2138); in hashBlock()
[all …]
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonVectorPrint.cpp | 75 (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) || in isVecReg()
186 } else if (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) { in runOnMachineFunction()
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| H A D | HexagonRegisterInfo.cpp | 86 W0, W1, W2, W3, W4, W5, W6, W7, W8, W9, W10, W11, W12, W13, W14, W15, 0 in getCallerSavedRegs()
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| H A D | HexagonRegisterInfo.td | 247 def W15 : Rd<30, "v31:30", [V30, V31, VF15]>, DwarfRegNum<[129]>;
279 def VQ7 : Rd<28, "v31:28", [W14, W15]>, DwarfRegNum<[259]>;
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| H A D | HexagonDepMappings.td | 278 def V6_vdd0Alias : InstAlias<"$Vdd32 = #0", (V6_vsubw_dv HvxWR:$Vdd32, W15, W15)>, Requires<[UseHVX…
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 47 case AArch64::X15: return AArch64::W15; in getWRegFromXReg()
87 case AArch64::W15: return AArch64::X15; in getXRegFromWReg()
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| /freebsd-src/sys/contrib/device-tree/src/arm64/ti/ |
| H A D | k3-am62a7-sk.dts | 341 AM62AX_IOPAD(0x154, PIN_INPUT, 0) /* (W15) RGMII1_RD2 */
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| H A D | k3-am62x-sk-common.dtsi | 230 AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17/W15) RGMII1_RD0 */
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 90 {codeview::RegisterId::ARM64_W15, AArch64::W15}, in initLLVMToCVRegMapping()
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.td | 81 def W15 : AArch64Reg<15, "w15">, DwarfRegNum<[15]>;
117 def X15 : AArch64Reg<15, "x15", [W15]>, DwarfRegAlias<W15>;
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 633 Hexagon::W15, Hexagon::WR15, in DecodeHvxWRRegisterClass()
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCInstrInfo.cpp | 695 return (VecReg >= Hexagon::W0 && VecReg <= Hexagon::W15) || in IsVecRegPair()
|