Home
last modified time | relevance | path

Searched refs:Subtarget (Results 1 – 25 of 305) sorted by relevance

12345678910>>...13

/freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrPredicates.td35 def HasEGPR : Predicate<"Subtarget->hasEGPR()">;
36 def NoEGPR : Predicate<"!Subtarget->hasEGPR()">;
46 def HasNDD : Predicate<"Subtarget->hasNDD()">;
47 def NoNDD : Predicate<"!Subtarget->hasNDD()">;
48 def HasCF : Predicate<"Subtarget->hasCF()">;
49 def HasCMOV : Predicate<"Subtarget->canUseCMOV()">;
50 def NoCMOV : Predicate<"!Subtarget->canUseCMOV()">;
51 def HasNOPL : Predicate<"Subtarget->hasNOPL()">;
52 def HasMMX : Predicate<"Subtarget->hasMMX()">;
53 def HasSSE1 : Predicate<"Subtarget
[all...]
H A DX86ISelLoweringCall.cpp71 const X86Subtarget &Subtarget) { in handleMaskRegisterForCallingConv()
86 if (NumElts == 32 && (!Subtarget.hasBWI() || CC != CallingConv::X86_RegCall)) in handleMaskRegisterForCallingConv()
89 if (NumElts == 64 && Subtarget.hasBWI() && CC != CallingConv::X86_RegCall) { in handleMaskRegisterForCallingConv()
90 if (Subtarget.useAVX512Regs()) in handleMaskRegisterForCallingConv()
96 if (!isPowerOf2_32(NumElts) || (NumElts == 64 && !Subtarget.hasBWI()) || in handleMaskRegisterForCallingConv()
107 if (VT.getVectorElementType() == MVT::i1 && Subtarget.hasAVX512()) { in getRegisterTypeForCallingConv()
113 handleMaskRegisterForCallingConv(NumElts, CC, Subtarget); in getRegisterTypeForCallingConv()
123 if ((VT == MVT::f64 || VT == MVT::f80) && !Subtarget.is64Bit() && in getRegisterTypeForCallingConv()
124 !Subtarget.hasX87()) in getRegisterTypeForCallingConv()
141 if (VT.getVectorElementType() == MVT::i1 && Subtarget in getNumRegistersForCallingConv()
70 handleMaskRegisterForCallingConv(unsigned NumElts,CallingConv::ID CC,const X86Subtarget & Subtarget) handleMaskRegisterForCallingConv() argument
715 Passv64i1ArgInRegs(const SDLoc & DL,SelectionDAG & DAG,SDValue & Arg,SmallVectorImpl<std::pair<Register,SDValue>> & RegsToPass,CCValAssign & VA,CCValAssign & NextVA,const X86Subtarget & Subtarget) Passv64i1ArgInRegs() argument
1008 getv64i1Argument(CCValAssign & VA,CCValAssign & NextVA,SDValue & Root,SelectionDAG & DAG,const SDLoc & DL,const X86Subtarget & Subtarget,SDValue * InGlue=nullptr) getv64i1Argument() argument
1201 hasCalleePopSRet(const SmallVectorImpl<T> & Args,const X86Subtarget & Subtarget) hasCalleePopSRet() argument
1411 get64BitArgumentGPRs(CallingConv::ID CallConv,const X86Subtarget & Subtarget) get64BitArgumentGPRs() argument
1430 get64BitArgumentXMMs(MachineFunction & MF,CallingConv::ID CallConv,const X86Subtarget & Subtarget) get64BitArgumentXMMs() argument
1467 VarArgsLoweringHelper(X86MachineFunctionInfo * FuncInfo,const SDLoc & Loc,SelectionDAG & DAG,const X86Subtarget & Subtarget,CallingConv::ID CallConv,CCState & CCInfo) VarArgsLoweringHelper() argument
1491 const X86Subtarget &Subtarget; global() member in __anon7a9913630211::VarArgsLoweringHelper
[all...]
H A DX86SelectionDAGInfo.cpp62 const X86Subtarget &Subtarget = in EmitTargetCodeForMemset()
69 ConstantSize->getZExtValue() > Subtarget.getMaxInlineSizeThreshold()) in EmitTargetCodeForMemset()
88 if (Subtarget.is64Bit() && Alignment >= Align(8)) { // QWORD aligned in EmitTargetCodeForMemset()
121 bool Use64BitRegs = Subtarget.isTarget64BitLP64(); in EmitTargetCodeForMemset()
156 static SDValue emitRepmovs(const X86Subtarget &Subtarget, SelectionDAG &DAG, in emitRepmovs()
159 const bool Use64BitRegs = Subtarget.isTarget64BitLP64(); in emitRepmovs()
178 static SDValue emitRepmovsB(const X86Subtarget &Subtarget, SelectionDAG &DAG, in emitRepmovsB()
181 return emitRepmovs(Subtarget, DAG, dl, Chain, Dst, Src, in emitRepmovsB()
186 static MVT getOptimalRepmovsType(const X86Subtarget &Subtarget, in getOptimalRepmovsType()
199 return Subtarget in getOptimalRepmovsType()
52 const X86Subtarget &Subtarget = EmitTargetCodeForMemset() local
154 emitRepmovs(const X86Subtarget & Subtarget,SelectionDAG & DAG,const SDLoc & dl,SDValue Chain,SDValue Dst,SDValue Src,SDValue Size,MVT AVT) emitRepmovs() argument
176 emitRepmovsB(const X86Subtarget & Subtarget,SelectionDAG & DAG,const SDLoc & dl,SDValue Chain,SDValue Dst,SDValue Src,uint64_t Size) emitRepmovsB() argument
184 getOptimalRepmovsType(const X86Subtarget & Subtarget,Align Alignment) getOptimalRepmovsType() argument
206 emitConstantSizeRepmov(SelectionDAG & DAG,const X86Subtarget & Subtarget,const SDLoc & dl,SDValue Chain,SDValue Dst,SDValue Src,uint64_t Size,EVT SizeVT,Align Alignment,bool isVolatile,bool AlwaysInline,MachinePointerInfo DstPtrInfo,MachinePointerInfo SrcPtrInfo) emitConstantSizeRepmov() argument
276 const X86Subtarget &Subtarget = EmitTargetCodeForMemcpy() local
[all...]
H A DX86ISelLowering.cpp129 : TargetLowering(TM), Subtarget(STI) { in X86TargetLowering()
130 bool UseX87 = !Subtarget.useSoftFloat() && Subtarget.hasX87(); in X86TargetLowering()
147 if (Subtarget.isAtom()) in X86TargetLowering()
149 else if (Subtarget.is64Bit()) in X86TargetLowering()
153 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in X86TargetLowering()
158 if (Subtarget.hasSlowDivide32()) in X86TargetLowering()
160 if (Subtarget.hasSlowDivide64() && Subtarget.is64Bit()) in X86TargetLowering()
165 if (Subtarget in X86TargetLowering()
2559 mayFoldLoad(SDValue Op,const X86Subtarget & Subtarget,bool AssumeSingleUse) mayFoldLoad() argument
2579 mayFoldLoadIntoBroadcastFromMem(SDValue Op,MVT EltVT,const X86Subtarget & Subtarget,bool AssumeSingleUse) mayFoldLoadIntoBroadcastFromMem() argument
2847 useVPTERNLOG(const X86Subtarget & Subtarget,MVT VT) useVPTERNLOG() argument
3735 getZeroVector(MVT VT,const X86Subtarget & Subtarget,SelectionDAG & DAG,const SDLoc & dl) getZeroVector() argument
3875 widenSubVector(MVT VT,SDValue Vec,bool ZeroNewElements,const X86Subtarget & Subtarget,SelectionDAG & DAG,const SDLoc & dl) widenSubVector() argument
3889 widenSubVector(SDValue Vec,bool ZeroNewElements,const X86Subtarget & Subtarget,SelectionDAG & DAG,const SDLoc & dl,unsigned WideSizeInBits) widenSubVector() argument
3902 widenMaskVectorType(MVT VT,const X86Subtarget & Subtarget) widenMaskVectorType() argument
3913 widenMaskVector(SDValue Vec,bool ZeroNewElements,const X86Subtarget & Subtarget,SelectionDAG & DAG,const SDLoc & dl) widenMaskVector() argument
4081 SplitOpsAndApply(SelectionDAG & DAG,const X86Subtarget & Subtarget,const SDLoc & DL,EVT VT,ArrayRef<SDValue> Ops,F Builder,bool CheckBWI=true) SplitOpsAndApply() argument
4125 getAVX512Node(unsigned Opcode,const SDLoc & DL,MVT VT,ArrayRef<SDValue> Ops,SelectionDAG & DAG,const X86Subtarget & Subtarget) getAVX512Node() argument
4188 insert1BitVector(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget) insert1BitVector() argument
4481 getPack(SelectionDAG & DAG,const X86Subtarget & Subtarget,const SDLoc & dl,MVT VT,SDValue LHS,SDValue RHS,bool PackHiHalf=false) getPack() argument
4550 getShuffleVectorZeroOrUndef(SDValue V2,int Idx,bool IsZero,const X86Subtarget & Subtarget,SelectionDAG & DAG) getShuffleVectorZeroOrUndef() argument
6355 LowerBuildVectorAsInsert(SDValue Op,const APInt & NonZeroMask,unsigned NumNonZero,unsigned NumZero,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerBuildVectorAsInsert() argument
6397 LowerBuildVectorv16i8(SDValue Op,const APInt & NonZeroMask,unsigned NumNonZero,unsigned NumZero,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerBuildVectorv16i8() argument
6479 LowerBuildVectorv8i16(SDValue Op,const APInt & NonZeroMask,unsigned NumNonZero,unsigned NumZero,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerBuildVectorv8i16() argument
6490 LowerBuildVectorv4x32(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerBuildVectorv4x32() argument
6752 EltsFromConsecutiveLoads(EVT VT,ArrayRef<SDValue> Elts,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget,bool IsAfterLegalize) EltsFromConsecutiveLoads() argument
7034 combineToConsecutiveLoads(EVT VT,SDValue Op,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget,bool IsAfterLegalize) combineToConsecutiveLoads() argument
7133 lowerBuildVectorAsBroadcast(BuildVectorSDNode * BVOp,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerBuildVectorAsBroadcast() argument
7477 LowerBUILD_VECTORvXbf16(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerBUILD_VECTORvXbf16() argument
7491 LowerBUILD_VECTORvXi1(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerBUILD_VECTORvXi1() argument
7771 isAddSubOrSubAdd(const BuildVectorSDNode * BV,const X86Subtarget & Subtarget,SelectionDAG & DAG,SDValue & Opnd0,SDValue & Opnd1,unsigned & NumExtracts,bool & IsSubAdd) isAddSubOrSubAdd() argument
7897 isFMAddSubOrFMSubAdd(const X86Subtarget & Subtarget,SelectionDAG & DAG,SDValue & Opnd0,SDValue & Opnd1,SDValue & Opnd2,unsigned ExpectedUses) isFMAddSubOrFMSubAdd() argument
7926 lowerToAddSubOrFMAddSub(const BuildVectorSDNode * BV,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerToAddSubOrFMAddSub() argument
8091 LowerToHorizontalOp(const BuildVectorSDNode * BV,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerToHorizontalOp() argument
8215 lowerBuildVectorToBitOp(BuildVectorSDNode * Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerBuildVectorToBitOp() argument
8293 materializeVectorConstant(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget) materializeVectorConstant() argument
8319 createVariablePermute(MVT VT,SDValue SrcVec,SDValue IndicesVec,SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) createVariablePermute() argument
8587 LowerBUILD_VECTORAsVariablePermute(SDValue V,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerBUILD_VECTORAsVariablePermute() argument
9073 LowerAVXCONCAT_VECTORS(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerAVXCONCAT_VECTORS() argument
9140 LowerCONCAT_VECTORSvXi1(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerCONCAT_VECTORSvXi1() argument
9215 LowerCONCAT_VECTORS(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerCONCAT_VECTORS() argument
9697 lowerShuffleWithPSHUFB(const SDLoc & DL,MVT VT,ArrayRef<int> Mask,SDValue V1,SDValue V2,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleWithPSHUFB() argument
9756 lowerShuffleToEXPAND(const SDLoc & DL,MVT VT,const APInt & Zeroable,ArrayRef<int> Mask,SDValue & V1,SDValue & V2,SelectionDAG & DAG,const X86Subtarget & Subtarget) lowerShuffleToEXPAND() argument
9779 matchShuffleWithUNPCK(MVT VT,SDValue & V1,SDValue & V2,unsigned & UnpackOpcode,bool IsUnary,ArrayRef<int> TargetMask,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) matchShuffleWithUNPCK() argument
9919 matchShuffleAsVTRUNC(MVT & SrcVT,MVT & DstVT,MVT VT,ArrayRef<int> Mask,const APInt & Zeroable,const X86Subtarget & Subtarget) matchShuffleAsVTRUNC() argument
9956 getAVX512TruncNode(const SDLoc & DL,MVT DstVT,SDValue Src,const X86Subtarget & Subtarget,SelectionDAG & DAG,bool ZeroUppers) getAVX512TruncNode() argument
10019 lowerShuffleWithVPMOV(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleWithVPMOV() argument
10069 lowerShuffleAsVTRUNC(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsVTRUNC() argument
10223 matchShuffleWithPACK(MVT VT,MVT & SrcVT,SDValue & V1,SDValue & V2,unsigned & PackOpcode,ArrayRef<int> TargetMask,const SelectionDAG & DAG,const X86Subtarget & Subtarget,unsigned MaxStages=1) matchShuffleWithPACK() argument
10293 lowerShuffleWithPACK(const SDLoc & DL,MVT VT,ArrayRef<int> Mask,SDValue V1,SDValue V2,SelectionDAG & DAG,const X86Subtarget & Subtarget) lowerShuffleWithPACK() argument
10343 lowerShuffleAsBitMask(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsBitMask() argument
10515 lowerShuffleAsBlend(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Original,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsBlend() argument
10798 lowerShuffleAsPermuteAndUnpack(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsPermuteAndUnpack() argument
10908 lowerShuffleAsByteRotateAndPermute(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsByteRotateAndPermute() argument
11025 lowerShuffleAsDecomposedShuffleMerge(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsDecomposedShuffleMerge() argument
11142 matchShuffleAsBitRotate(MVT & RotateVT,int EltSizeInBits,const X86Subtarget & Subtarget,ArrayRef<int> Mask) matchShuffleAsBitRotate() argument
11163 lowerShuffleAsBitRotate(const SDLoc & DL,MVT VT,SDValue V1,ArrayRef<int> Mask,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsBitRotate() argument
11314 lowerShuffleAsByteRotate(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsByteRotate() argument
11372 lowerShuffleAsVALIGN(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsVALIGN() argument
11423 lowerShuffleAsByteShiftMask(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsByteShiftMask() argument
11510 matchShuffleAsShift(MVT & ShiftVT,unsigned & Opcode,unsigned ScalarSizeInBits,ArrayRef<int> Mask,int MaskOffset,const APInt & Zeroable,const X86Subtarget & Subtarget) matchShuffleAsShift() argument
11572 lowerShuffleAsShift(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG,bool BitwiseOnly) lowerShuffleAsShift() argument
11759 lowerShuffleAsSpecificZeroOrAnyExtend(const SDLoc & DL,MVT VT,int Scale,int Offset,bool AnyExt,SDValue InputV,ArrayRef<int> Mask,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsSpecificZeroOrAnyExtend() argument
11923 lowerShuffleAsZeroOrAnyExtend(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsZeroOrAnyExtend() argument
12074 isSoftF16(T VT,const X86Subtarget & Subtarget) isSoftF16() argument
12085 lowerShuffleAsElementInsertion(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsElementInsertion() argument
12211 lowerShuffleAsTruncBroadcast(const SDLoc & DL,MVT VT,SDValue V0,int BroadcastIdx,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsTruncBroadcast() argument
12354 lowerShuffleAsBroadcast(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsBroadcast() argument
12659 lowerV2F64Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV2F64Shuffle() argument
12743 lowerV2I64Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV2I64Shuffle() argument
12935 lowerV4F32Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV4F32Shuffle() argument
13039 lowerV4I32Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV4I32Shuffle() argument
13180 lowerV8I16GeneralSingleInputShuffle(const SDLoc & DL,MVT VT,SDValue V,MutableArrayRef<int> Mask,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV8I16GeneralSingleInputShuffle() argument
13737 lowerV8I16Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV8I16Shuffle() argument
13941 lowerV8F16Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV8F16Shuffle() argument
13972 lowerShuffleWithPERMV(const SDLoc & DL,MVT VT,ArrayRef<int> Mask,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleWithPERMV() argument
14016 lowerV16I8Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV16I8Shuffle() argument
14373 lower128BitShuffle(const SDLoc & DL,ArrayRef<int> Mask,MVT VT,SDValue V1,SDValue V2,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lower128BitShuffle() argument
14539 lowerShuffleAsSplitOrBlend(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsSplitOrBlend() argument
14629 lowerShuffleAsLanePermuteAndPermute(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,SelectionDAG & DAG,const X86Subtarget & Subtarget) lowerShuffleAsLanePermuteAndPermute() argument
14752 lowerShuffleAsLanePermuteAndShuffle(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,SelectionDAG & DAG,const X86Subtarget & Subtarget) lowerShuffleAsLanePermuteAndShuffle() argument
14812 lowerV2X128Shuffle(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV2X128Shuffle() argument
14931 lowerShuffleAsLanePermuteAndRepeatedMask(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsLanePermuteAndRepeatedMask() argument
15195 lowerShuffleWithUndefHalf(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleWithUndefHalf() argument
15306 lowerShuffleAsRepeatedMaskAndLanePermute(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleAsRepeatedMaskAndLanePermute() argument
15551 lowerShuffleWithSHUFPD(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerShuffleWithSHUFPD() argument
15698 lowerV4F64Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV4F64Shuffle() argument
15818 lowerV4I64Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV4I64Shuffle() argument
15931 lowerV8F32Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV8F32Shuffle() argument
16053 lowerV8I32Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV8I32Shuffle() argument
16195 lowerV16I16Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV16I16Shuffle() argument
16318 lowerV32I8Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV32I8Shuffle() argument
16440 lower256BitShuffle(const SDLoc & DL,ArrayRef<int> Mask,MVT VT,SDValue V1,SDValue V2,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lower256BitShuffle() argument
16512 lowerV4X128Shuffle(const SDLoc & DL,MVT VT,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV4X128Shuffle() argument
16618 lowerV8F64Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV8F64Shuffle() argument
16672 lowerV16F32Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV16F32Shuffle() argument
16739 lowerV8I64Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV8I64Shuffle() argument
16812 lowerV16I32Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV16I32Shuffle() argument
16909 lowerV32I16Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV32I16Shuffle() argument
16973 lowerV64I8Shuffle(const SDLoc & DL,ArrayRef<int> Mask,const APInt & Zeroable,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerV64I8Shuffle() argument
17072 lower512BitShuffle(const SDLoc & DL,ArrayRef<int> Mask,MVT VT,SDValue V1,SDValue V2,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lower512BitShuffle() argument
17145 lower1BitShuffleAsKSHIFTR(const SDLoc & DL,ArrayRef<int> Mask,MVT VT,SDValue V1,SDValue V2,const X86Subtarget & Subtarget,SelectionDAG & DAG) lower1BitShuffleAsKSHIFTR() argument
17221 lower1BitShuffle(const SDLoc & DL,ArrayRef<int> Mask,MVT VT,SDValue V1,SDValue V2,const APInt & Zeroable,const X86Subtarget & Subtarget,SelectionDAG & DAG) lower1BitShuffle() argument
17421 canCombineAsMaskOperation(SDValue V,const X86Subtarget & Subtarget) canCombineAsMaskOperation() argument
17485 lowerVECTOR_SHUFFLE(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerVECTOR_SHUFFLE() argument
17628 lowerVSELECTtoVectorShuffle(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) lowerVSELECTtoVectorShuffle() argument
17795 ExtractBitFromMaskVector(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget) ExtractBitFromMaskVector() argument
18031 InsertBitToMaskVector(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget) InsertBitToMaskVector() argument
18266 LowerSCALAR_TO_VECTOR(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerSCALAR_TO_VECTOR() argument
18305 LowerINSERT_SUBVECTOR(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerINSERT_SUBVECTOR() argument
18312 LowerEXTRACT_SUBVECTOR(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerEXTRACT_SUBVECTOR() argument
18828 LowerI64IntToFP_AVX512DQ(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerI64IntToFP_AVX512DQ() argument
18870 LowerI64IntToFP16(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerI64IntToFP16() argument
18906 useVectorCast(unsigned Opcode,MVT FromVT,MVT ToVT,const X86Subtarget & Subtarget) useVectorCast() argument
18931 vectorizeExtractedCast(SDValue Cast,SelectionDAG & DAG,const X86Subtarget & Subtarget) vectorizeExtractedCast() argument
18973 lowerFPToIntToFP(SDValue CastToFP,SelectionDAG & DAG,const X86Subtarget & Subtarget) lowerFPToIntToFP() argument
19020 lowerINT_TO_FP_vXi64(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget) lowerINT_TO_FP_vXi64() argument
19128 isLegalConversion(MVT VT,bool IsSigned,const X86Subtarget & Subtarget) isLegalConversion() argument
19290 shouldUseHorizontalOp(bool IsSingleSource,SelectionDAG & DAG,const X86Subtarget & Subtarget) shouldUseHorizontalOp() argument
19298 LowerUINT_TO_FP_i64(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerUINT_TO_FP_i64() argument
19366 LowerUINT_TO_FP_i32(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerUINT_TO_FP_i32() argument
19416 lowerUINT_TO_FP_v2i32(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget,const SDLoc & DL) lowerUINT_TO_FP_v2i32() argument
19469 lowerUINT_TO_FP_vXi32(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget) lowerUINT_TO_FP_vXi32() argument
19627 lowerUINT_TO_FP_vec(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget) lowerUINT_TO_FP_vec() argument
19962 LowerAVXExtend(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerAVXExtend() argument
20038 LowerZERO_EXTEND_Mask(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerZERO_EXTEND_Mask() argument
20095 LowerZERO_EXTEND(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerZERO_EXTEND() argument
20114 truncateVectorWithPACK(unsigned Opcode,EVT DstVT,SDValue In,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) truncateVectorWithPACK() argument
20235 truncateVectorWithPACKUS(EVT DstVT,SDValue In,const SDLoc & DL,const X86Subtarget & Subtarget,SelectionDAG & DAG) truncateVectorWithPACKUS() argument
20243 truncateVectorWithPACKSS(EVT DstVT,SDValue In,const SDLoc & DL,const X86Subtarget & Subtarget,SelectionDAG & DAG) truncateVectorWithPACKSS() argument
20257 matchTruncateWithPACK(unsigned & PackOpcode,EVT DstVT,SDValue In,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) matchTruncateWithPACK() argument
20346 LowerTruncateVecPackWithSignBits(MVT DstVT,SDValue In,const SDLoc & DL,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerTruncateVecPackWithSignBits() argument
20379 LowerTruncateVecPack(MVT DstVT,SDValue In,const SDLoc & DL,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerTruncateVecPack() argument
20430 LowerTruncateVecI1(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerTruncateVecI1() argument
20636 expandFP_TO_UINT_SSE(MVT VT,SDValue Src,const SDLoc & dl,SelectionDAG & DAG,const X86Subtarget & Subtarget) expandFP_TO_UINT_SSE() argument
21552 lowerAddSubToHorizontalOp(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget) lowerAddSubToHorizontalOp() argument
21896 combineVectorSizedSetCCEquality(EVT VT,SDValue X,SDValue Y,ISD::CondCode CC,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineVectorSizedSetCCEquality() argument
22114 LowerVectorAllEqual(const SDLoc & DL,SDValue LHS,SDValue RHS,ISD::CondCode CC,const APInt & OriginalMask,const X86Subtarget & Subtarget,SelectionDAG & DAG,X86::CondCode & X86CC) LowerVectorAllEqual() argument
22262 MatchVectorAllEqualTest(SDValue LHS,SDValue RHS,ISD::CondCode CC,const SDLoc & DL,const X86Subtarget & Subtarget,SelectionDAG & DAG,X86::CondCode & X86CC) MatchVectorAllEqualTest() argument
22421 EmitTest(SDValue Op,unsigned X86CC,const SDLoc & dl,SelectionDAG & DAG,const X86Subtarget & Subtarget) EmitTest() argument
22530 EmitCmp(SDValue Op0,SDValue Op1,unsigned X86CC,const SDLoc & dl,SelectionDAG & DAG,const X86Subtarget & Subtarget) EmitCmp() argument
23012 LowerVSETCCWithSUBUS(SDValue Op0,SDValue Op1,MVT VT,ISD::CondCode Cond,const SDLoc & dl,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerVSETCCWithSUBUS() argument
23065 LowerVSETCC(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerVSETCC() argument
23501 EmitAVX512Test(SDValue Op0,SDValue Op1,ISD::CondCode CC,const SDLoc & dl,SelectionDAG & DAG,const X86Subtarget & Subtarget,SDValue & X86CC) EmitAVX512Test() argument
24142 LowerSIGN_EXTEND_Mask(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerSIGN_EXTEND_Mask() argument
24198 LowerANY_EXTEND(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerANY_EXTEND() argument
24215 LowerEXTEND_VECTOR_INREG(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerEXTEND_VECTOR_INREG() argument
24337 LowerSIGN_EXTEND(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerSIGN_EXTEND() argument
24458 LowerStore(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerStore() argument
24545 LowerLoad(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerLoad() argument
24925 LowerVACOPY(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerVACOPY() argument
25024 getTargetVShiftNode(unsigned Opc,const SDLoc & dl,MVT VT,SDValue SrcOp,SDValue ShAmt,int ShAmtIdx,const X86Subtarget & Subtarget,SelectionDAG & DAG) getTargetVShiftNode() argument
25120 getMaskNode(SDValue Mask,MVT MaskVT,const X86Subtarget & Subtarget,SelectionDAG & DAG,const SDLoc & dl) getMaskNode() argument
25155 getVectorMaskingNode(SDValue Op,SDValue Mask,SDValue PreservedSrc,const X86Subtarget & Subtarget,SelectionDAG & DAG) getVectorMaskingNode() argument
25181 getScalarMaskingNode(SDValue Op,SDValue Mask,SDValue PreservedSrc,const X86Subtarget & Subtarget,SelectionDAG & DAG) getScalarMaskingNode() argument
25253 const X86Subtarget &Subtarget = DAG.getSubtarget<X86Subtarget>(); recoverFramePointer() local
26290 getAVX2GatherNode(unsigned Opc,SDValue Op,SelectionDAG & DAG,SDValue Src,SDValue Mask,SDValue Base,SDValue Index,SDValue ScaleOp,SDValue Chain,const X86Subtarget & Subtarget) getAVX2GatherNode() argument
26322 getGatherNode(SDValue Op,SelectionDAG & DAG,SDValue Src,SDValue Mask,SDValue Base,SDValue Index,SDValue ScaleOp,SDValue Chain,const X86Subtarget & Subtarget) getGatherNode() argument
26360 getScatterNode(unsigned Opc,SDValue Op,SelectionDAG & DAG,SDValue Src,SDValue Mask,SDValue Base,SDValue Index,SDValue ScaleOp,SDValue Chain,const X86Subtarget & Subtarget) getScatterNode() argument
26391 getPrefetchNode(unsigned Opc,SDValue Op,SelectionDAG & DAG,SDValue Mask,SDValue Base,SDValue Index,SDValue ScaleOp,SDValue Chain,const X86Subtarget & Subtarget) getPrefetchNode() argument
26422 expandIntrinsicWChainHelper(SDNode * N,const SDLoc & DL,SelectionDAG & DAG,unsigned TargetOpcode,unsigned SrcReg,const X86Subtarget & Subtarget,SmallVectorImpl<SDValue> & Results) expandIntrinsicWChainHelper() argument
26475 getReadTimeStampCounter(SDNode * N,const SDLoc & DL,unsigned Opcode,SelectionDAG & DAG,const X86Subtarget & Subtarget,SmallVectorImpl<SDValue> & Results) getReadTimeStampCounter() argument
26494 LowerREADCYCLECOUNTER(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerREADCYCLECOUNTER() argument
26562 LowerINTRINSIC_W_CHAIN(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerINTRINSIC_W_CHAIN() argument
27627 createSetFPEnvNodes(SDValue Ptr,SDValue Chain,SDLoc DL,EVT MemVT,MachineMemOperand * MMO,SelectionDAG & DAG,const X86Subtarget & Subtarget) createSetFPEnvNodes() argument
27700 LowerVectorCTLZ_AVX512CDI(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerVectorCTLZ_AVX512CDI() argument
27730 LowerVectorCTLZInRegLUT(SDValue Op,const SDLoc & DL,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerVectorCTLZInRegLUT() argument
27812 LowerVectorCTLZ(SDValue Op,const SDLoc & DL,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerVectorCTLZ() argument
27833 LowerCTLZ(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerCTLZ() argument
27872 LowerCTTZ(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerCTTZ() argument
27898 lowerAddSub(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget) lowerAddSub() argument
27913 LowerADDSAT_SUBSAT(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerADDSAT_SUBSAT() argument
27982 LowerABS(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerABS() argument
28019 LowerAVG(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerAVG() argument
28034 LowerMINMAX(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerMINMAX() argument
28049 LowerFMINIMUM_FMAXIMUM(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerFMINIMUM_FMAXIMUM() argument
28197 LowerABD(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerABD() argument
28244 LowerMUL(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerMUL() argument
28389 LowervXi8MulWithUNPCK(SDValue A,SDValue B,const SDLoc & dl,MVT VT,bool IsSigned,const X86Subtarget & Subtarget,SelectionDAG & DAG,SDValue * Low=nullptr) LowervXi8MulWithUNPCK() argument
28466 LowerMULH(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerMULH() argument
28573 LowerMULO(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerMULO() argument
28840 supportedVectorShiftWithImm(EVT VT,const X86Subtarget & Subtarget,unsigned Opcode) supportedVectorShiftWithImm() argument
28866 supportedVectorShiftWithBaseAmnt(EVT VT,const X86Subtarget & Subtarget,unsigned Opcode) supportedVectorShiftWithBaseAmnt() argument
28873 supportedVectorVarShift(EVT VT,const X86Subtarget & Subtarget,unsigned Opcode) supportedVectorVarShift() argument
28898 LowerShiftByScalarImmediate(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerShiftByScalarImmediate() argument
29043 LowerShiftByScalarVariable(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerShiftByScalarVariable() argument
29107 convertShiftLeftToScale(SDValue Amt,const SDLoc & dl,const X86Subtarget & Subtarget,SelectionDAG & DAG) convertShiftLeftToScale() argument
29161 LowerShift(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerShift() argument
29648 LowerFunnelShift(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerFunnelShift() argument
29825 LowerRotate(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerRotate() argument
30648 emitLockedStackOp(SelectionDAG & DAG,const X86Subtarget & Subtarget,SDValue Chain,const SDLoc & DL) emitLockedStackOp() argument
30708 LowerATOMIC_FENCE(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerATOMIC_FENCE() argument
30731 LowerCMP_SWAP(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerCMP_SWAP() argument
30771 getPMOVMSKB(const SDLoc & DL,SDValue V,SelectionDAG & DAG,const X86Subtarget & Subtarget) getPMOVMSKB() argument
30798 LowerBITCAST(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerBITCAST() argument
30867 LowerHorizontalByteSum(SDValue V,MVT VT,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerHorizontalByteSum() argument
30931 LowerVectorCTPOPInRegLUT(SDValue Op,const SDLoc & DL,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerVectorCTPOPInRegLUT() argument
30977 LowerVectorCTPOP(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerVectorCTPOP() argument
31021 LowerCTPOP(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerCTPOP() argument
31073 LowerBITREVERSE(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerBITREVERSE() argument
31138 LowerPARITY(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerPARITY() argument
31195 lowerAtomicArithWithLOCK(SDValue N,SelectionDAG & DAG,const X86Subtarget & Subtarget) lowerAtomicArithWithLOCK() argument
31227 lowerAtomicArith(SDValue N,SelectionDAG & DAG,const X86Subtarget & Subtarget) lowerAtomicArith() argument
31296 LowerATOMIC_STORE(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget) LowerATOMIC_STORE() argument
31402 LowerFSINCOS(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerFSINCOS() argument
31507 LowerMSCATTER(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerMSCATTER() argument
31570 LowerMLOAD(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerMLOAD() argument
31636 LowerMSTORE(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerMSTORE() argument
31678 LowerMGATHER(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerMGATHER() argument
31785 LowerPREFETCH(SDValue Op,const X86Subtarget & Subtarget,SelectionDAG & DAG) LowerPREFETCH() argument
35076 getIndirectThunkSymbol(const X86Subtarget & Subtarget,unsigned Reg) getIndirectThunkSymbol() argument
37075 matchUnaryShuffle(MVT MaskVT,ArrayRef<int> Mask,bool AllowFloatDomain,bool AllowIntDomain,SDValue V1,const SelectionDAG & DAG,const X86Subtarget & Subtarget,unsigned & Shuffle,MVT & SrcVT,MVT & DstVT) matchUnaryShuffle() argument
37230 matchUnaryPermuteShuffle(MVT MaskVT,ArrayRef<int> Mask,const APInt & Zeroable,bool AllowFloatDomain,bool AllowIntDomain,const SelectionDAG & DAG,const X86Subtarget & Subtarget,unsigned & Shuffle,MVT & ShuffleVT,unsigned & PermuteImm) matchUnaryPermuteShuffle() argument
37378 matchBinaryShuffle(MVT MaskVT,ArrayRef<int> Mask,bool AllowFloatDomain,bool AllowIntDomain,SDValue & V1,SDValue & V2,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget,unsigned & Shuffle,MVT & SrcVT,MVT & DstVT,bool IsUnary) matchBinaryShuffle() argument
37574 matchBinaryPermuteShuffle(MVT MaskVT,ArrayRef<int> Mask,const APInt & Zeroable,bool AllowFloatDomain,bool AllowIntDomain,SDValue & V1,SDValue & V2,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget,unsigned & Shuffle,MVT & ShuffleVT,unsigned & PermuteImm) matchBinaryPermuteShuffle() argument
37754 combineX86ShuffleChain(ArrayRef<SDValue> Inputs,SDValue Root,ArrayRef<int> BaseMask,int Depth,bool HasVariableMask,bool AllowVariableCrossLaneMask,bool AllowVariablePerLaneMask,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineX86ShuffleChain() argument
38498 combineX86ShuffleChainWithExtract(ArrayRef<SDValue> Inputs,SDValue Root,ArrayRef<int> BaseMask,int Depth,bool HasVariableMask,bool AllowVariableCrossLaneMask,bool AllowVariablePerLaneMask,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineX86ShuffleChainWithExtract() argument
38619 canonicalizeShuffleMaskWithHorizOp(MutableArrayRef<SDValue> Ops,MutableArrayRef<int> Mask,unsigned RootSizeInBits,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) canonicalizeShuffleMaskWithHorizOp() argument
38829 combineX86ShufflesConstants(ArrayRef<SDValue> Ops,ArrayRef<int> Mask,SDValue Root,bool HasVariableMask,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineX86ShufflesConstants() argument
38953 combineX86ShufflesRecursively(ArrayRef<SDValue> SrcOps,int SrcOpIndex,SDValue Root,ArrayRef<int> RootMask,ArrayRef<const SDNode * > SrcNodes,unsigned Depth,unsigned MaxDepth,bool HasVariableMask,bool AllowVariableCrossLaneMask,bool AllowVariablePerLaneMask,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineX86ShufflesRecursively() argument
39384 combineX86ShufflesRecursively(SDValue Op,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineX86ShufflesRecursively() argument
39582 const X86Subtarget &Subtarget = DAG.getSubtarget<X86Subtarget>(); combineCommutableSHUFP() local
39844 combineTargetShuffle(SDValue N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineTargetShuffle() argument
40622 isAddSubOrSubAdd(SDNode * N,const X86Subtarget & Subtarget,SelectionDAG & DAG,SDValue & Opnd0,SDValue & Opnd1,bool & IsSubAdd) isAddSubOrSubAdd() argument
40683 combineShuffleToFMAddSub(SDNode * N,const X86Subtarget & Subtarget,SelectionDAG & DAG) combineShuffleToFMAddSub() argument
40726 combineShuffleToAddSubOrFMAddSub(SDNode * N,const X86Subtarget & Subtarget,SelectionDAG & DAG) combineShuffleToAddSubOrFMAddSub() argument
40768 combineShuffleOfConcatUndef(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineShuffleOfConcatUndef() argument
40844 combineShuffle(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineShuffle() argument
42503 combineBitcastvxi1(SelectionDAG & DAG,EVT VT,SDValue Src,const SDLoc & DL,const X86Subtarget & Subtarget) combineBitcastvxi1() argument
42669 combineCastedMaskArithmetic(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineCastedMaskArithmetic() argument
42724 createMMXBuildVector(BuildVectorSDNode * BV,SelectionDAG & DAG,const X86Subtarget & Subtarget) createMMXBuildVector() argument
42805 combineBitcastToBoolVector(EVT VT,SDValue V,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineBitcastToBoolVector() argument
42873 combineBitcast(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineBitcast() argument
43211 createVPDPBUSD(SelectionDAG & DAG,SDValue LHS,SDValue RHS,unsigned & LogBias,const SDLoc & DL,const X86Subtarget & Subtarget) createVPDPBUSD() argument
43257 createPSADBW(SelectionDAG & DAG,const SDValue & Zext0,const SDValue & Zext1,const SDLoc & DL,const X86Subtarget & Subtarget) createPSADBW() argument
43286 combineMinMaxReduction(SDNode * Extract,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineMinMaxReduction() argument
43360 combinePredicateReduction(SDNode * Extract,SelectionDAG & DAG,const X86Subtarget & Subtarget) combinePredicateReduction() argument
43500 combineVPDPBUSDPattern(SDNode * Extract,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineVPDPBUSDPattern() argument
43571 combineBasicSADPattern(SDNode * Extract,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineBasicSADPattern() argument
43648 combineExtractWithShuffle(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineExtractWithShuffle() argument
43846 scalarizeExtEltFP(SDNode * ExtElt,SelectionDAG & DAG,const X86Subtarget & Subtarget) scalarizeExtEltFP() argument
43947 combineArithReduction(SDNode * ExtElt,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineArithReduction() argument
44141 combineExtractVectorElt(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineExtractVectorElt() argument
44329 combineToExtendBoolVectorInReg(unsigned Opcode,const SDLoc & DL,EVT VT,SDValue N0,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineToExtendBoolVectorInReg() argument
44429 combineVSelectWithAllOnesOrZeros(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineVSelectWithAllOnesOrZeros() argument
44534 narrowVectorSelect(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) narrowVectorSelect() argument
44640 combineVSelectToBLENDV(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineVSelectToBLENDV() argument
44747 combineLogicBlendIntoConditionalNegate(EVT VT,SDValue Mask,SDValue X,SDValue Y,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineLogicBlendIntoConditionalNegate() argument
44792 commuteSelect(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) commuteSelect() argument
44825 combineSelect(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineSelect() argument
45345 combineSetCCAtomicArith(SDValue Cmp,X86::CondCode & CC,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineSetCCAtomicArith() argument
45695 combinePTESTCC(SDValue EFLAGS,X86::CondCode & CC,SelectionDAG & DAG,const X86Subtarget & Subtarget) combinePTESTCC() argument
45859 combineSetCCMOVMSK(SDValue EFLAGS,X86::CondCode & CC,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineSetCCMOVMSK() argument
46103 combineSetCCEFLAGS(SDValue EFLAGS,X86::CondCode & CC,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineSetCCEFLAGS() argument
46123 combineCMov(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineCMov() argument
46436 reduceVMULWidth(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) reduceVMULWidth() argument
46595 combineMulToPMADDWD(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineMulToPMADDWD() argument
46707 combineMulToPMULDQ(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineMulToPMULDQ() argument
46750 combineMul(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineMul() argument
46940 combineShiftToPMULH(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineShiftToPMULH() argument
47034 combineShiftRightArithmetic(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineShiftRightArithmetic() argument
47094 combineShiftRightLogical(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineShiftRightLogical() argument
47146 combineHorizOpWithShuffle(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineHorizOpWithShuffle() argument
47291 combineVectorPack(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineVectorPack() argument
47442 combineVectorHADDSUB(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineVectorHADDSUB() argument
47490 combineVectorShiftVar(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineVectorShiftVar() argument
47521 combineVectorShiftImm(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineVectorShiftImm() argument
47672 combineVectorInsert(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineVectorInsert() argument
47711 combineCompareEqual(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineCompareEqual() argument
47848 combineAndShuffleNot(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineAndShuffleNot() argument
47990 PromoteMaskArithmetic(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) PromoteMaskArithmetic() argument
48034 convertIntLogicToFPLogic(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) convertIntLogicToFPLogic() argument
48218 combineAndMaskToShift(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineAndMaskToShift() argument
48297 hasBZHI(const X86Subtarget & Subtarget,MVT VT) hasBZHI() argument
48319 combineAndLoadToBZHI(SDNode * Node,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineAndLoadToBZHI() argument
48401 combineScalarAndWithMaskSetcc(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineScalarAndWithMaskSetcc() argument
48526 combineBMILogicOp(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineBMILogicOp() argument
48546 combineAnd(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineAnd() argument
48809 canonicalizeBitSelect(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) canonicalizeBitSelect() argument
48911 combineLogicBlendIntoPBLENDV(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineLogicBlendIntoPBLENDV() argument
48988 combineOrCmpEqZeroToCtlzSrl(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineOrCmpEqZeroToCtlzSrl() argument
49353 combineOr(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineOr() argument
49567 foldVectorXorShiftIntoCmp(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) foldVectorXorShiftIntoCmp() argument
49703 combineTruncateWithSat(SDValue In,EVT VT,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineTruncateWithSat() argument
49805 detectAVGPattern(SDValue In,EVT VT,SelectionDAG & DAG,const X86Subtarget & Subtarget,const SDLoc & DL) detectAVGPattern() argument
49954 combineLoad(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineLoad() argument
50165 reduceMaskedLoadToScalarLoad(MaskedLoadSDNode * ML,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) reduceMaskedLoadToScalarLoad() argument
50254 combineMaskedLoad(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineMaskedLoad() argument
50301 reduceMaskedStoreToScalarStore(MaskedStoreSDNode * MS,SelectionDAG & DAG,const X86Subtarget & Subtarget) reduceMaskedStoreToScalarStore() argument
50333 combineMaskedStore(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineMaskedStore() argument
50381 combineStore(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineStore() argument
50663 combineVEXTRACT_STORE(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineVEXTRACT_STORE() argument
50698 isHorizontalBinOp(unsigned HOpcode,SDValue & LHS,SDValue & RHS,SelectionDAG & DAG,const X86Subtarget & Subtarget,bool IsCommutative,SmallVectorImpl<int> & PostShuffleMask) isHorizontalBinOp() argument
50886 combineToHorizontalAddSub(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineToHorizontalAddSub() argument
50951 combineFMulcFCMulc(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineFMulcFCMulc() argument
50992 combineFaddCFmul(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineFaddCFmul() argument
51067 combineFaddFsub(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineFaddFsub() argument
51083 combineTruncatedArithmetic(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget,const SDLoc & DL) combineTruncatedArithmetic() argument
51164 combinePMULH(SDValue Src,EVT VT,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) combinePMULH() argument
51248 detectPMADDUBSW(SDValue In,EVT VT,SelectionDAG & DAG,const X86Subtarget & Subtarget,const SDLoc & DL) detectPMADDUBSW() argument
51379 combineTruncate(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineTruncate() argument
51585 combineFneg(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineFneg() argument
51688 lowerX86FPLogicOp(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) lowerX86FPLogicOp() argument
51731 combineXorSubCTLZ(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineXorSubCTLZ() argument
51789 combineXor(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineXor() argument
51879 combineBITREVERSE(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineBITREVERSE() argument
51906 combineBEXTR(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineBEXTR() argument
51932 getNullFPConstForNullVal(SDValue V,SelectionDAG & DAG,const X86Subtarget & Subtarget) getNullFPConstForNullVal() argument
51943 combineFAndFNotToFAndn(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineFAndFNotToFAndn() argument
51975 combineFAnd(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineFAnd() argument
51992 combineFAndn(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineFAndn() argument
52007 combineFOr(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineFOr() argument
52047 combineFMinNumFMaxNum(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineFMinNumFMaxNum() argument
52184 combineAndnp(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineAndnp() argument
52415 combineSignExtendInReg(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineSignExtendInReg() argument
52462 promoteExtBeforeAdd(SDNode * Ext,SelectionDAG & DAG,const X86Subtarget & Subtarget) promoteExtBeforeAdd() argument
52584 combineExtSetcc(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineExtSetcc() argument
52629 combineSext(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineSext() argument
52733 combineFMA(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineFMA() argument
52844 combineZext(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineZext() argument
52910 truncateAVX512SetCCNoBWI(EVT VT,EVT OpVT,SDValue LHS,SDValue RHS,ISD::CondCode CC,const SDLoc & DL,SelectionDAG & DAG,const X86Subtarget & Subtarget) truncateAVX512SetCCNoBWI() argument
52923 combineSetCC(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineSetCC() argument
53153 combineMOVMSK(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineMOVMSK() argument
53268 combineTESTP(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineTESTP() argument
53436 combineX86SetCC(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineX86SetCC() argument
53450 combineBrCond(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineBrCond() argument
53559 combineUIntToFP(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineUIntToFP() argument
53623 combineSIntToFP(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineSIntToFP() argument
53803 combineCMP(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineCMP() argument
54064 matchPMADDWD(SelectionDAG & DAG,SDValue Op0,SDValue Op1,const SDLoc & DL,EVT VT,const X86Subtarget & Subtarget) matchPMADDWD() argument
54172 matchPMADDWD_2(SelectionDAG & DAG,SDValue N0,SDValue N1,const SDLoc & DL,EVT VT,const X86Subtarget & Subtarget) matchPMADDWD_2() argument
54355 pushAddIntoCmovOfConsts(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) pushAddIntoCmovOfConsts() argument
54421 combineAdd(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineAdd() argument
54544 combineSub(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineSub() argument
54611 combineVectorCompare(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineVectorCompare() argument
54631 combineConcatVectorOps(const SDLoc & DL,MVT VT,ArrayRef<SDValue> Ops,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineConcatVectorOps() argument
55227 combineCONCAT_VECTORS(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineCONCAT_VECTORS() argument
55263 combineINSERT_SUBVECTOR(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineINSERT_SUBVECTOR() argument
55474 combineEXTRACT_SUBVECTOR(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineEXTRACT_SUBVECTOR() argument
55748 combinePMULDQ(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combinePMULDQ() argument
55821 combineEXTEND_VECTOR_INREG(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const X86Subtarget & Subtarget) combineEXTEND_VECTOR_INREG() argument
55906 combineFP16_TO_FP(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineFP16_TO_FP() argument
55928 combineFP_EXTEND(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineFP_EXTEND() argument
56039 combineFP_ROUND(SDNode * N,SelectionDAG & DAG,const X86Subtarget & Subtarget) combineFP_ROUND() argument
[all...]
H A DX86FastISel.cpp48 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
50 const X86Subtarget *Subtarget; member in __anona4374c4e0111::X86FastISel
56 Subtarget = &funcInfo.MF->getSubtarget<X86Subtarget>(); in X86FastISel()
130 return Subtarget->getInstrInfo(); in getInstrInfo()
150 return (VT == MVT::f64 && Subtarget->hasSSE2()) || in isScalarFPTypeInSSEReg()
151 (VT == MVT::f32 && Subtarget->hasSSE1()) || VT == MVT::f16; in isScalarFPTypeInSSEReg()
299 if (VT == MVT::f64 && !Subtarget->hasSSE2()) in isTypeLegal()
301 if (VT == MVT::f32 && !Subtarget->hasSSE1()) in isTypeLegal()
319 bool HasSSE1 = Subtarget->hasSSE1(); in X86FastEmitLoad()
320 bool HasSSE2 = Subtarget in X86FastEmitLoad()
1357 X86ChooseCmpOpcode(EVT VT,const X86Subtarget * Subtarget) X86ChooseCmpOpcode() argument
3185 computeBytesPoppedByCalleeForSRet(const X86Subtarget * Subtarget,CallingConv::ID CC,const CallBase * CB) computeBytesPoppedByCalleeForSRet() argument
[all...]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMPredicates.td9 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
11 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
12 def HasV5T : Predicate<"Subtarget->hasV5TOps()">,
14 def NoV5T : Predicate<"!Subtarget->hasV5TOps()">;
15 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
17 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
19 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
20 def HasV6M : Predicate<"Subtarget->hasV6MOps()">,
23 def HasV8MBaseline : Predicate<"Subtarget->hasV8MBaselineOps()">,
26 def HasV8MMainline : Predicate<"Subtarget
[all...]
H A DARMMachineFunctionInfo.cpp30 const ARMSubtarget *Subtarget) { in GetBranchTargetEnforcement()
31 if (!Subtarget->isMClass() || !Subtarget->hasV7Ops()) in GetBranchTargetEnforcement()
56 const ARMSubtarget *Subtarget) in GetSignReturnAddress()
57 : isThumb(Subtarget->isThumb()), hasThumb2(Subtarget->hasThumb2()), in GetSignReturnAddress()
60 BranchTargetEnforcement(GetBranchTargetEnforcement(F, Subtarget)) { in GetSignReturnAddress()
61 if (Subtarget->isMClass() && Subtarget->hasV7Ops()) in GetSignReturnAddress()
29 GetBranchTargetEnforcement(const Function & F,const ARMSubtarget * Subtarget) GetBranchTargetEnforcement() argument
75 ARMFunctionInfo(const Function & F,const ARMSubtarget * Subtarget) ARMFunctionInfo() argument
H A DARMSelectionDAGInfo.cpp41 const ARMSubtarget &Subtarget = in EmitSpecializedLibcall() local
43 const ARMTargetLowering *TLI = Subtarget.getTargetLowering(); in EmitSpecializedLibcall()
141 static bool shouldGenerateInlineTPLoop(const ARMSubtarget &Subtarget, in shouldGenerateInlineTPLoop() argument
161 ConstantSize->getZExtValue() > Subtarget.getMaxInlineSizeThreshold() && in shouldGenerateInlineTPLoop()
163 Subtarget.getMaxMemcpyTPInlineSizeThreshold()) in shouldGenerateInlineTPLoop()
172 const ARMSubtarget &Subtarget = in EmitTargetCodeForMemcpy() local
176 if (Subtarget.hasMVEIntegerOps() && in EmitTargetCodeForMemcpy()
177 shouldGenerateInlineTPLoop(Subtarget, DAG, ConstantSize, Alignment, true)) in EmitTargetCodeForMemcpy()
191 if (!AlwaysInline && SizeVal > Subtarget.getMaxInlineSizeThreshold()) in EmitTargetCodeForMemcpy()
202 const unsigned MaxLoadsInLDM = Subtarget.isThumb1Only() ? 4 : 6; in EmitTargetCodeForMemcpy()
[all …]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.cpp94 const MipsSubtarget &Subtarget = MF->getSubtarget<MipsSubtarget>(); in getCalleeSavedRegs() local
97 if (Subtarget.hasMips64()) in getCalleeSavedRegs()
98 return Subtarget.hasMips64r6() ? CSR_Interrupt_64R6_SaveList in getCalleeSavedRegs()
101 return Subtarget.hasMips32r6() ? CSR_Interrupt_32R6_SaveList in getCalleeSavedRegs()
105 if (Subtarget.isSingleFloat()) in getCalleeSavedRegs()
108 if (Subtarget.isABI_N64()) in getCalleeSavedRegs()
111 if (Subtarget.isABI_N32()) in getCalleeSavedRegs()
114 if (Subtarget.isFP64bit()) in getCalleeSavedRegs()
117 if (Subtarget.isFPXX()) in getCalleeSavedRegs()
126 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>(); in getCallPreservedMask() local
[all …]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPU.td23 // Subtarget Features (device properties)
963 // Subtarget Features (options and debugging)
1768 Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS">,
1772 Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1773 "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1777 Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1778 "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1779 "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1783 Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1784 "Subtarget
[all...]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCLowerMASSVEntries.cpp54 static StringRef getCPUSuffix(const PPCSubtarget *Subtarget);
56 const PPCSubtarget *Subtarget);
59 const PPCSubtarget *Subtarget);
75 StringRef PPCLowerMASSVEntries::getCPUSuffix(const PPCSubtarget *Subtarget) { in getCPUSuffix()
76 // Assume generic when Subtarget is unavailable. in getCPUSuffix()
77 if (!Subtarget) in getCPUSuffix()
80 if (Subtarget->isAIXABI() && Subtarget->hasP10Vector()) in getCPUSuffix()
82 if (Subtarget->hasP9Vector()) in getCPUSuffix()
84 if (Subtarget in getCPUSuffix()
73 getCPUSuffix(const PPCSubtarget * Subtarget) getCPUSuffix() argument
96 createMASSVFuncName(Function & Func,const PPCSubtarget * Subtarget) createMASSVFuncName() argument
136 lowerMASSVCall(CallInst * CI,Function & Func,Module & M,const PPCSubtarget * Subtarget) lowerMASSVCall() argument
161 const PPCSubtarget *Subtarget; runOnModule() local
[all...]
H A DPPCRegisterInfo.cpp186 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>(); in getCalleeSavedRegs() local
188 if (!TM.isPPC64() && Subtarget.isAIXABI()) in getCalleeSavedRegs()
190 if (Subtarget.hasVSX()) { in getCalleeSavedRegs()
191 if (Subtarget.pairedVectorMemops()) in getCalleeSavedRegs()
193 if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI()) in getCalleeSavedRegs()
197 if (Subtarget.hasAltivec()) { in getCalleeSavedRegs()
198 if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI()) in getCalleeSavedRegs()
213 !Subtarget.isUsingPCRelativeCalls(); in getCalleeSavedRegs()
217 if (Subtarget.isAIXABI()) in getCalleeSavedRegs()
220 if (Subtarget in getCalleeSavedRegs()
280 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); getCallPreservedMask() local
356 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); getReservedRegs() local
455 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); requiresFrameIndexScavenging() local
530 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); requiresVirtualBaseRegisters() local
541 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); isCallerPreservedPhysReg() local
656 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); getRegPressureLimit() local
666 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); getRegPressureLimit() local
681 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); getLargestLegalSuperClass() local
743 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); lowerDynamicAlloc() local
803 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); prepareDynamicAlloca() local
889 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); lowerPrepareProbedAlloca() local
933 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); lowerDynamicAreaOffset() local
961 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); lowerCRSpilling() local
1006 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); lowerCRRestore() local
1049 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); lowerCRBitSpilling() local
1168 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); lowerCRBitRestore() local
1284 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); lowerOctWordSpilling() local
1318 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); lowerACCSpilling() local
1361 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); lowerACCRestore() local
1396 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); lowerWACCSpilling() local
1430 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); lowerWACCRestore() local
1462 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); lowerQuadwordSpilling() local
1489 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); lowerQuadwordRestore() local
1591 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); eliminateFrameIndex() local
1825 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); getBaseRegister() local
1910 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); materializeFrameBaseRegister() local
1940 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); resolveFrameIndex() local
[all...]
H A DPPCFrameLowering.cpp85 Subtarget(STI), ReturnSaveOffset(computeReturnSaveOffset(Subtarget)), in PPCFrameLowering()
86 TOCSaveOffset(computeTOCSaveOffset(Subtarget)), in PPCFrameLowering()
87 FramePointerSaveOffset(computeFramePointerSaveOffset(Subtarget)), in PPCFrameLowering()
88 LinkageSize(computeLinkageSize(Subtarget)), in PPCFrameLowering()
89 BasePointerSaveOffset(computeBasePointerSaveOffset(Subtarget)), in PPCFrameLowering()
90 CRSaveOffset(computeCRSaveOffset(Subtarget)) {} in PPCFrameLowering()
231 if (Subtarget.is64BitELFABI()) { in getCalleeSavedSpillSlots()
236 if (Subtarget.is32BitELFABI()) { in getCalleeSavedSpillSlots()
241 assert(Subtarget in getCalleeSavedSpillSlots()
[all...]
H A DPPCISelLowering.cpp172 : TargetLowering(TM), Subtarget(STI) { in PPCTargetLowering()
179 bool isPPC64 = Subtarget.isPPC64(); in PPCTargetLowering()
188 if (!Subtarget.hasEFPU2()) in PPCTargetLowering()
213 if (Subtarget.isISA3_0()) { in PPCTargetLowering()
243 if (!Subtarget.hasSPE()) { in PPCTargetLowering()
259 if (Subtarget.useCRBits()) { in PPCTargetLowering()
262 if (isPPC64 || Subtarget.hasFPCVT()) { in PPCTargetLowering()
336 if (Subtarget.isISA3_0()) { in PPCTargetLowering()
371 if (!Subtarget.hasSPE()) { in PPCTargetLowering()
376 if (Subtarget in PPCTargetLowering()
1951 const PPCSubtarget &Subtarget = DAG.getSubtarget<PPCSubtarget>(); isVPKUDUMShuffleMask() local
3130 getLabelAccessInfo(bool IsPIC,const PPCSubtarget & Subtarget,unsigned & HiOpFlags,unsigned & LoOpFlags,const GlobalValue * GV=nullptr) getLabelAccessInfo() argument
4852 needStackSlotPassParameters(const PPCSubtarget & Subtarget,const SmallVectorImpl<ISD::OutputArg> & Outs) needStackSlotPassParameters() argument
5106 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); EmitTailCallStoreFPAndRetAddr() local
5296 isIndirectCall(const SDValue & Callee,SelectionDAG & DAG,const PPCSubtarget & Subtarget,bool isPatchPoint) isIndirectCall() argument
5320 isTOCSaveRestoreRequired(const PPCSubtarget & Subtarget) isTOCSaveRestoreRequired() argument
5327 getCallOpcode(PPCTargetLowering::CallFlags CFlags,const Function & Caller,const SDValue & Callee,const PPCSubtarget & Subtarget,const TargetMachine & TM,bool IsStrictFPCall=false) getCallOpcode() argument
5389 transformCallee(const SDValue & Callee,SelectionDAG & DAG,const SDLoc & dl,const PPCSubtarget & Subtarget) transformCallee() argument
5500 prepareDescriptorIndirectCall(SelectionDAG & DAG,SDValue & Callee,SDValue & Glue,SDValue & Chain,SDValue CallSeqStart,const CallBase * CB,const SDLoc & dl,bool hasNest,const PPCSubtarget & Subtarget) prepareDescriptorIndirectCall() argument
5593 buildCallOperands(SmallVectorImpl<SDValue> & Ops,PPCTargetLowering::CallFlags CFlags,const SDLoc & dl,SelectionDAG & DAG,SmallVector<std::pair<unsigned,SDValue>,8> & RegsToPass,SDValue Glue,SDValue Chain,SDValue & Callee,int SPDiff,const PPCSubtarget & Subtarget) buildCallOperands() argument
6733 const PPCSubtarget &Subtarget = static_cast<const PPCSubtarget &>( CC_AIX() local
7074 const PPCSubtarget &Subtarget = DAG.getSubtarget<PPCSubtarget>(); LowerFormalArguments_AIX() local
7379 const PPCSubtarget &Subtarget = DAG.getSubtarget<PPCSubtarget>(); LowerCall_AIX() local
8192 convertFPToInt(SDValue Op,SelectionDAG & DAG,const PPCSubtarget & Subtarget) convertFPToInt() argument
8519 convertIntToFP(SDValue Op,SDValue Src,SelectionDAG & DAG,const PPCSubtarget & Subtarget,SDValue Chain=SDValue ()) convertIntToFP() argument
9280 isValidSplatLoad(const PPCSubtarget & Subtarget,const SDValue & Op,unsigned & Opcode) isValidSplatLoad() argument
10443 getVectorCompareInfo(SDValue Intrin,int & CompareOpc,bool & isDot,const PPCSubtarget & Subtarget) getVectorCompareInfo() argument
11117 getDataClassTest(SDValue Op,FPClassTest Mask,const SDLoc & Dl,SelectionDAG & DAG,const PPCSubtarget & Subtarget) getDataClassTest() argument
13478 getEstimateRefinementSteps(EVT VT,const PPCSubtarget & Subtarget) getEstimateRefinementSteps() argument
15246 fixupShuffleMaskForPermutedSToV(SmallVectorImpl<int> & ShuffV,int LHSMaxIdx,int RHSMinIdx,int RHSMaxIdx,int HalfVec,unsigned ValidLaneWidth,const PPCSubtarget & Subtarget) fixupShuffleMaskForPermutedSToV() argument
15261 getSToVPermuted(SDValue OrigSToV,SelectionDAG & DAG,const PPCSubtarget & Subtarget) getSToVPermuted() argument
17632 combineADDToADDZE(SDNode * N,SelectionDAG & DAG,const PPCSubtarget & Subtarget) combineADDToADDZE() argument
17718 combineADDToMAT_PCREL_ADDR(SDNode * N,SelectionDAG & DAG,const PPCSubtarget & Subtarget) combineADDToMAT_PCREL_ADDR() argument
[all...]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVFeatures.td78 def HasStdExtZicbom : Predicate<"Subtarget->hasStdExtZicbom()">,
85 def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">,
93 def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">,
116 def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
129 def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
136 def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">,
144 def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">,
152 def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
163 def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">,
171 def HasStdExtZicfilp : Predicate<"Subtarget
[all...]
H A DRISCVISelLowering.cpp85 : TargetLowering(TM), Subtarget(STI) { in RISCVTargetLowering()
87 RISCVABI::ABI ABI = Subtarget.getTargetABI(); in RISCVTargetLowering()
91 !Subtarget.hasStdExtF()) { in RISCVTargetLowering()
95 ABI = Subtarget.is64Bit() ? RISCVABI::ABI_LP64 : RISCVABI::ABI_ILP32; in RISCVTargetLowering()
97 !Subtarget.hasStdExtD()) { in RISCVTargetLowering()
101 ABI = Subtarget.is64Bit() ? RISCVABI::ABI_LP64 : RISCVABI::ABI_ILP32; in RISCVTargetLowering()
118 MVT XLenVT = Subtarget.getXLenVT(); in RISCVTargetLowering()
122 if (Subtarget.is64Bit() && RV64LegalI32) in RISCVTargetLowering()
125 if (Subtarget.hasStdExtZfhmin()) in RISCVTargetLowering()
127 if (Subtarget in RISCVTargetLowering()
2440 useRVVForFixedLengthVectorVT(MVT VT,const RISCVSubtarget & Subtarget) useRVVForFixedLengthVectorVT() argument
2512 getContainerForFixedLengthVector(const TargetLowering & TLI,MVT VT,const RISCVSubtarget & Subtarget) getContainerForFixedLengthVector() argument
2546 getContainerForFixedLengthVector(SelectionDAG & DAG,MVT VT,const RISCVSubtarget & Subtarget) getContainerForFixedLengthVector() argument
2557 convertToScalableVector(EVT VT,SDValue V,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) convertToScalableVector() argument
2569 convertFromScalableVector(EVT VT,SDValue V,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) convertFromScalableVector() argument
2597 getVLOp(uint64_t NumElts,MVT ContainerVT,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) getVLOp() argument
2611 getDefaultScalableVLOps(MVT VecVT,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) getDefaultScalableVLOps() argument
2620 getDefaultVLOps(uint64_t NumElts,MVT ContainerVT,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) getDefaultVLOps() argument
2633 getDefaultVLOps(MVT VecVT,MVT ContainerVT,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) getDefaultVLOps() argument
2650 computeVLMAXBounds(MVT VecVT,const RISCVSubtarget & Subtarget) computeVLMAXBounds() argument
2734 lowerFP_TO_INT_SAT(SDValue Op,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerFP_TO_INT_SAT() argument
2869 lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(SDValue Op,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND() argument
2978 lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(SDValue Op,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND() argument
3079 lowerFTRUNC_FCEIL_FFLOOR_FROUND(SDValue Op,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerFTRUNC_FCEIL_FFLOOR_FROUND() argument
3107 lowerVectorXRINT(SDValue Op,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerVectorXRINT() argument
3131 getVSlidedown(SelectionDAG & DAG,const RISCVSubtarget & Subtarget,const SDLoc & DL,EVT VT,SDValue Merge,SDValue Op,SDValue Offset,SDValue Mask,SDValue VL,unsigned Policy=RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED) getVSlidedown() argument
3143 getVSlideup(SelectionDAG & DAG,const RISCVSubtarget & Subtarget,const SDLoc & DL,EVT VT,SDValue Merge,SDValue Op,SDValue Offset,SDValue Mask,SDValue VL,unsigned Policy=RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED) getVSlideup() argument
3305 matchSplatAsGather(SDValue SplatVal,MVT VT,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) matchSplatAsGather() argument
3346 lowerBuildVectorViaDominantValues(SDValue Op,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerBuildVectorViaDominantValues() argument
3453 lowerBuildVectorOfConstants(SDValue Op,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerBuildVectorOfConstants() argument
3754 lowerBUILD_VECTOR(SDValue Op,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerBUILD_VECTOR() argument
4000 lowerScalarSplat(SDValue Passthru,SDValue Scalar,SDValue VL,MVT VT,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerScalarSplat() argument
4038 lowerScalarInsert(SDValue Scalar,SDValue VL,MVT VT,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerScalarInsert() argument
4098 isDeinterleaveShuffle(MVT VT,MVT ContainerVT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const RISCVSubtarget & Subtarget) isDeinterleaveShuffle() argument
4142 isInterleaveShuffle(ArrayRef<int> Mask,MVT VT,int & EvenSrc,int & OddSrc,const RISCVSubtarget & Subtarget) isInterleaveShuffle() argument
4253 getDeinterleaveViaVNSRL(const SDLoc & DL,MVT VT,SDValue Src,bool EvenElts,const RISCVSubtarget & Subtarget,SelectionDAG & DAG) getDeinterleaveViaVNSRL() argument
4313 lowerVECTOR_SHUFFLEAsVSlidedown(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const RISCVSubtarget & Subtarget,SelectionDAG & DAG) lowerVECTOR_SHUFFLEAsVSlidedown() argument
4390 lowerVECTOR_SHUFFLEAsVSlideup(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const RISCVSubtarget & Subtarget,SelectionDAG & DAG) lowerVECTOR_SHUFFLEAsVSlideup() argument
4434 lowerVECTOR_SHUFFLEAsVSlide1(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const RISCVSubtarget & Subtarget,SelectionDAG & DAG) lowerVECTOR_SHUFFLEAsVSlide1() argument
4487 getWideningInterleave(SDValue EvenV,SDValue OddV,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) getWideningInterleave() argument
4571 lowerBitreverseShuffle(ShuffleVectorSDNode * SVN,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerBitreverseShuffle() argument
4626 lowerVECTOR_SHUFFLEAsRotate(ShuffleVectorSDNode * SVN,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerVECTOR_SHUFFLEAsRotate() argument
4662 lowerShuffleViaVRegSplitting(ShuffleVectorSDNode * SVN,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerShuffleViaVRegSplitting() argument
4737 lowerVECTOR_SHUFFLE(SDValue Op,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerVECTOR_SHUFFLE() argument
5293 lowerConstant(SDValue Op,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerConstant() argument
5333 LowerATOMIC_FENCE(SDValue Op,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) LowerATOMIC_FENCE() argument
5464 lowerFMAXIMUM_FMINIMUM(SDValue Op,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerFMAXIMUM_FMINIMUM() argument
7059 combineSelectToBinOp(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) combineSelectToBinOp() argument
7125 foldBinOpIntoSelectIfProfitable(SDNode * BO,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) foldBinOpIntoSelectIfProfitable() argument
7881 getSmallestVTForIndex(MVT VecVT,unsigned MaxIdx,SDLoc DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) getSmallestVTForIndex() argument
8229 lowerVectorIntrinsicScalars(SDValue Op,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerVectorIntrinsicScalars() argument
8417 lowerGetVectorLength(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerGetVectorLength() argument
8455 const RISCVSubtarget &Subtarget = getVCIXOperands() local
8475 isValidEGW(int EGS,EVT VT,const RISCVSubtarget & Subtarget) isValidEGW() argument
9183 lowerReductionSeq(unsigned RVVOpcode,MVT ResVT,SDValue StartValue,SDValue Vec,SDValue Mask,SDValue VL,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerReductionSeq() argument
9265 getRVVFPReductionOpAndOperands(SDValue Op,SelectionDAG & DAG,EVT EltVT,const RISCVSubtarget & Subtarget) getRVVFPReductionOpAndOperands() argument
12089 combineBinOpOfExtractToReduceTree(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) combineBinOpOfExtractToReduceTree() argument
12185 combineBinOpToReduce(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) combineBinOpToReduce() argument
12291 transformAddShlImm(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) transformAddShlImm() argument
12348 combineSelectAndUse(SDNode * N,SDValue Slct,SDValue OtherOp,SelectionDAG & DAG,bool AllOnes,const RISCVSubtarget & Subtarget) combineSelectAndUse() argument
12413 combineSelectAndUseCommutative(SDNode * N,SelectionDAG & DAG,bool AllOnes,const RISCVSubtarget & Subtarget) combineSelectAndUseCommutative() argument
12442 transformAddImmMulImm(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) transformAddImmMulImm() argument
12516 performADDCombine(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) performADDCombine() argument
12575 performSUBCombine(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) performSUBCombine() argument
12647 performTRUNCATECombine(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) performTRUNCATECombine() argument
12674 performANDCombine(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,const RISCVSubtarget & Subtarget) performANDCombine() argument
12747 performORCombine(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,const RISCVSubtarget & Subtarget) performORCombine() argument
12774 performXORCombine(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) performXORCombine() argument
12941 performSETCCCombine(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) performSETCCCombine() argument
12988 performSIGN_EXTEND_INREGCombine(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) performSIGN_EXTEND_INREGCombine() argument
13457 canFoldToVWWithSameExtensionImpl(SDNode * Root,const NodeExtensionHelper & LHS,const NodeExtensionHelper & RHS,bool AllowSExt,bool AllowZExt,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) canFoldToVWWithSameExtensionImpl() argument
13483 canFoldToVWWithSameExtension(SDNode * Root,const NodeExtensionHelper & LHS,const NodeExtensionHelper & RHS,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) canFoldToVWWithSameExtension() argument
13495 canFoldToVW_W(SDNode * Root,const NodeExtensionHelper & LHS,const NodeExtensionHelper & RHS,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) canFoldToVW_W() argument
13521 canFoldToVWWithSEXT(SDNode * Root,const NodeExtensionHelper & LHS,const NodeExtensionHelper & RHS,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) canFoldToVWWithSEXT() argument
13533 canFoldToVWWithZEXT(SDNode * Root,const NodeExtensionHelper & LHS,const NodeExtensionHelper & RHS,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) canFoldToVWWithZEXT() argument
13545 canFoldToVW_SU(SDNode * Root,const NodeExtensionHelper & LHS,const NodeExtensionHelper & RHS,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) canFoldToVW_SU() argument
13602 combineBinOp_VLToVWBinOp_VL(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,const RISCVSubtarget & Subtarget) combineBinOp_VLToVWBinOp_VL() argument
13707 const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>(); tryMemPairCombine() local
13758 const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>(); performMemPairCombine() local
13843 performFP_TO_INTCombine(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,const RISCVSubtarget & Subtarget) performFP_TO_INTCombine() argument
13946 performFP_TO_INT_SATCombine(SDNode * N,TargetLowering::DAGCombinerInfo & DCI,const RISCVSubtarget & Subtarget) performFP_TO_INT_SATCombine() argument
14008 performBITREVERSECombine(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) performBITREVERSECombine() argument
14103 performVFMADD_VLCombine(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) performVFMADD_VLCombine() argument
14165 performVFMUL_VLCombine(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) performVFMUL_VLCombine() argument
14206 performFADDSUB_VLCombine(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) performFADDSUB_VLCombine() argument
14266 performSRACombine(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) performSRACombine() argument
14437 combine_CC(SDValue & LHS,SDValue & RHS,SDValue & CC,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) combine_CC() argument
14639 useInversedSetcc(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) useInversedSetcc() argument
14670 performSELECTCombine(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) performSELECTCombine() argument
14693 performBUILD_VECTORCombine(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget,const RISCVTargetLowering & TLI) performBUILD_VECTORCombine() argument
14745 performINSERT_VECTOR_ELTCombine(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget,const RISCVTargetLowering & TLI) performINSERT_VECTOR_ELTCombine() argument
14818 performCONCAT_VECTORSCombine(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget,const RISCVTargetLowering & TLI) performCONCAT_VECTORSCombine() argument
14948 combineToVWMACC(SDNode * N,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) combineToVWMACC() argument
14987 __anonbba6e2091702(SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) combineToVWMACC() argument
16607 emitSplitF64Pseudo(MachineInstr & MI,MachineBasicBlock * BB,const RISCVSubtarget & Subtarget) emitSplitF64Pseudo() argument
16646 emitBuildPairF64Pseudo(MachineInstr & MI,MachineBasicBlock * BB,const RISCVSubtarget & Subtarget) emitBuildPairF64Pseudo() argument
16702 emitQuietFCMP(MachineInstr & MI,MachineBasicBlock * BB,unsigned RelOpcode,unsigned EqOpcode,const RISCVSubtarget & Subtarget) emitQuietFCMP() argument
16739 EmitLoweredCascadedSelect(MachineInstr & First,MachineInstr & Second,MachineBasicBlock * ThisMBB,const RISCVSubtarget & Subtarget) EmitLoweredCascadedSelect() argument
16841 emitSelectPseudo(MachineInstr & MI,MachineBasicBlock * BB,const RISCVSubtarget & Subtarget) emitSelectPseudo() argument
17031 emitFROUND(MachineInstr & MI,MachineBasicBlock * MBB,const RISCVSubtarget & Subtarget) emitFROUND() argument
17739 convertLocVTToValVT(SelectionDAG & DAG,SDValue Val,const CCValAssign & VA,const SDLoc & DL,const RISCVSubtarget & Subtarget) convertLocVTToValVT() argument
17803 convertValVTToLocVT(SelectionDAG & DAG,SDValue Val,const CCValAssign & VA,const SDLoc & DL,const RISCVSubtarget & Subtarget) convertValVTToLocVT() argument
17916 const RISCVSubtarget &Subtarget = TLI.getSubtarget(); CC_RISCV_FastCC() local
18039 const RISCVSubtarget &Subtarget = CC_RISCV_GHC() local
[all...]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVCallLowering.cpp53 const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>(); in assignArg()
55 if (RISCVAssignFn(DL, Subtarget.getTargetABI(), ValNo, ValVT, LocVT, in assignArg()
57 *Subtarget.getTargetLowering(), RVVDispatcher)) in assignArg()
69 Subtarget(MIRBuilder.getMF().getSubtarget<RISCVSubtarget>()) {} in getStackAddress()
74 LLT p0 = LLT::pointer(0, Subtarget.getXLen()); in getStackAddress()
75 LLT sXLen = LLT::scalar(Subtarget.getXLen()); in getStackAddress()
170 const RISCVSubtarget &Subtarget;
199 const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>(); in assignArg()
204 if (RISCVAssignFn(DL, Subtarget.getTargetABI(), ValNo, ValVT, LocVT, in RISCVIncomingValueHandler()
206 *Subtarget in RISCVIncomingValueHandler()
49 const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>(); assignArg() local
162 const RISCVSubtarget &Subtarget; global() member
187 const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>(); assignArg() local
278 const RISCVSubtarget &Subtarget; global() member
310 isLegalElementTypeForRVV(Type * EltTy,const RISCVSubtarget & Subtarget) isLegalElementTypeForRVV() argument
331 isSupportedArgumentType(Type * T,const RISCVSubtarget & Subtarget,bool IsLowerArgs=false) isSupportedArgumentType() argument
352 isSupportedReturnType(Type * T,const RISCVSubtarget & Subtarget,bool IsLowerRetVal=false) isSupportedReturnType() argument
389 const RISCVSubtarget &Subtarget = lowerReturnVal() local
432 const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>(); saveVarArgRegisters() local
503 const RISCVSubtarget &Subtarget = lowerFormalArguments() local
554 const RISCVSubtarget &Subtarget = lowerCall() local
[all...]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64PointerAuth.cpp44 const AArch64Subtarget *Subtarget = nullptr;
78 static void BuildPACM(const AArch64Subtarget &Subtarget, MachineBasicBlock &MBB, in BuildPACM()
81 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in BuildPACM()
94 if (MFnI.branchProtectionPAuthLR() && !Subtarget.hasPAuthLR()) in signLR()
125 if (MFnI.branchProtectionPAuthLR() && Subtarget->hasPAuthLR()) { in signLR()
132 BuildPACM(*Subtarget, MBB, MBBI, DL, MachineInstr::FrameSetup); in signLR()
189 if (Subtarget->hasPAuth() && TerminatorIsCombinable && !NeedsWinCFI && in authenticateLR()
191 if (MFnI->branchProtectionPAuthLR() && Subtarget->hasPAuthLR()) { in authenticateLR()
199 BuildPACM(*Subtarget, MBB, TI, DL, MachineInstr::FrameDestroy, PACSym); in authenticateLR()
206 if (MFnI->branchProtectionPAuthLR() && Subtarget in authenticateLR()
40 const AArch64Subtarget *Subtarget = nullptr; global() member in __anond21e204c0111::AArch64PointerAuth
67 BuildPACM(const AArch64Subtarget & Subtarget,MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,DebugLoc DL,MachineInstr::MIFlag Flags,MCSymbol * PACSym=nullptr) BuildPACM() argument
213 createCheckMemOperand(MachineFunction & MF,const AArch64Subtarget & Subtarget) createCheckMemOperand() argument
229 const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>(); checkAuthenticatedRegister() local
[all...]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRMCInstLower.cpp27 const AVRSubtarget &Subtarget) const { in lowerSymbolOperand()
46 AVRMCExpr::create(Subtarget.hasEIJMPCALL() ? AVRMCExpr::VK_AVR_LO8_GS in lowerSymbolOperand()
55 AVRMCExpr::create(Subtarget.hasEIJMPCALL() ? AVRMCExpr::VK_AVR_HI8_GS in lowerSymbolOperand()
70 auto &Subtarget = MI.getParent()->getParent()->getSubtarget<AVRSubtarget>(); in lowerInstruction() local
91 lowerSymbolOperand(MO, Printer.getSymbol(MO.getGlobal()), Subtarget); in lowerInstruction()
95 MO, Printer.GetExternalSymbolSymbol(MO.getSymbolName()), Subtarget); in lowerInstruction()
105 MO, Printer.GetBlockAddressSymbol(MO.getBlockAddress()), Subtarget); in lowerInstruction()
109 Subtarget); in lowerInstruction()
113 Subtarget); in lowerInstruction()
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DLeonPasses.cpp40 Subtarget = &MF.getSubtarget<SparcSubtarget>(); in runOnMachineFunction()
41 if (!Subtarget->insertNOPLoad()) in runOnMachineFunction()
44 const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); in runOnMachineFunction()
79 Subtarget = &MF.getSubtarget<SparcSubtarget>(); in runOnMachineFunction()
80 if (!Subtarget->detectRoundChange()) in runOnMachineFunction()
129 Subtarget = &MF.getSubtarget<SparcSubtarget>(); in runOnMachineFunction()
130 if (!Subtarget->fixAllFDIVSQRT()) in runOnMachineFunction()
133 const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); in runOnMachineFunction()
H A DSparcRegisterInfo.cpp54 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in getReservedRegs() local
65 if (!Subtarget.is64Bit()) in getReservedRegs()
80 if (ReserveAppRegisters || !Subtarget.is64Bit()) in getReservedRegs()
88 if (!Subtarget.isV9()) { in getReservedRegs()
117 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in getPointerRegClass() local
118 return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass; in getPointerRegClass()
183 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in eliminateFrameIndex() local
192 if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) { in eliminateFrameIndex()
194 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); in eliminateFrameIndex()
206 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); in eliminateFrameIndex()
/freebsd-src/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp28 const CSKYSubtarget *Subtarget; member in __anonc3a991630111::CSKYDAGToDAGISel
36 Subtarget = &MF.getSubtarget<CSKYSubtarget>(); in runOnMachineFunction()
92 Register GP = Subtarget->getInstrInfo()->getGlobalBaseReg(*MF); in INITIALIZE_PASS()
102 ReplaceNode(N, CurDAG->getMachineNode(Subtarget->hasE2() ? CSKY::ADDI32 in INITIALIZE_PASS()
290 if (!Subtarget->hasFPUv2DoubleFloat()) in selectBITCAST_TO_LOHI()
315 Subtarget->has2E3() ? CSKY::CLRC32 : CSKY::CLRC16, Dl, Type1); in selectAddCarry()
317 Subtarget->has2E3() ? CSKY::ADDC32 : CSKY::ADDC16, Dl, {Type0, Type1}, in selectAddCarry()
321 Subtarget->has2E3() ? CSKY::SETC32 : CSKY::SETC16, Dl, Type1); in selectAddCarry()
323 Subtarget->has2E3() ? CSKY::ADDC32 : CSKY::ADDC16, Dl, {Type0, Type1}, in selectAddCarry()
326 NewNode = CurDAG->getMachineNode(Subtarget in selectAddCarry()
327 InvertCarryFlag(const CSKYSubtarget * Subtarget,SelectionDAG * DAG,SDLoc Dl,SDValue OldCarry) InvertCarryFlag() argument
[all...]
H A DCSKY.td24 def HasFPUv2_SF : Predicate<"Subtarget->hasFPUv2SingleFloat()">,
31 def HasFPUv2_DF : Predicate<"Subtarget->hasFPUv2DoubleFloat()">,
37 def HasFdivdu : Predicate<"Subtarget->hasFdivdu()">,
44 def HasFPUv3_HI : Predicate<"Subtarget->hasFPUv3HalfWord()">,
51 def HasFPUv3_HF : Predicate<"Subtarget->hasFPUv3HalfFloat()">,
58 def HasFPUv3_SF : Predicate<"Subtarget->hasFPUv3SingleFloat()">,
65 def HasFPUv3_DF : Predicate<"Subtarget->hasFPUv3DoubleFloat()">,
71 def iHasFLOATE1 : Predicate<"Subtarget->hasFLOATE1()">,
77 def iHasFLOAT1E2 : Predicate<"Subtarget->hasFLOAT1E2()">,
83 def iHasFLOAT1E3 : Predicate<"Subtarget->hasFLOAT1E3()">,
[all …]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp79 const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>(); in getRegAllocationHints() local
80 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); in getRegAllocationHints()
192 const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>(); in getCalleeSavedRegs() local
193 return Subtarget.hasVector() ? CSR_SystemZ_XPLINK64_Vector_SaveList in getCalleeSavedRegs()
199 const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>(); in getCalleeSavedRegs() local
203 return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_SaveList in getCalleeSavedRegs()
215 const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>(); in getCallPreservedMask() local
216 return Subtarget.hasVector() ? CSR_SystemZ_XPLINK64_Vector_RegMask in getCallPreservedMask()
223 const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>(); in getCallPreservedMask() local
227 return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_RegMask in getCallPreservedMask()
[all …]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArch.td24 : Predicate<"Subtarget->is64Bit()">,
28 : Predicate<"!Subtarget->is64Bit()">,
39 def HasBasicF : Predicate<"Subtarget->hasBasicF()">;
46 def HasBasicD : Predicate<"Subtarget->hasBasicD()">;
52 def HasExtLSX : Predicate<"Subtarget->hasExtLSX()">;
59 def HasExtLASX : Predicate<"Subtarget->hasExtLASX()">;
65 def HasExtLVZ : Predicate<"Subtarget->hasExtLVZ()">;
71 def HasExtLBT : Predicate<"Subtarget->hasExtLBT()">;
78 : Predicate<"Subtarget->hasLaGlobalWithPcrel()">,
87 : Predicate<"Subtarget
[all...]

12345678910>>...13