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Searched refs:NewOpcode (Results 1 – 25 of 47) sorted by relevance

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/freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonCFGOptimizer.cpp85 int NewOpcode = 0; in InvertAndChangeJumpTarget() local
88 NewOpcode = Hexagon::J2_jumpf; in InvertAndChangeJumpTarget()
91 NewOpcode = Hexagon::J2_jumpt; in InvertAndChangeJumpTarget()
94 NewOpcode = Hexagon::J2_jumpfnewpt; in InvertAndChangeJumpTarget()
97 NewOpcode = Hexagon::J2_jumptnewpt; in InvertAndChangeJumpTarget()
103 MI.setDesc(TII->get(NewOpcode)); in InvertAndChangeJumpTarget()
H A DHexagonVLIWPacketizer.cpp462 int NewOpcode; in promoteToDotNew()
464 NewOpcode = HII->getDotNewPredOp(MI, MBPI); in promoteToDotNew()
466 NewOpcode = HII->getDotNewOp(MI); in promoteToDotNew()
467 MI.setDesc(HII->get(NewOpcode)); in promoteToDotNew()
472 int NewOpcode = HII->getDotOldOp(MI); in demoteToDotOld()
473 MI.setDesc(HII->get(NewOpcode)); in demoteToDotOld()
891 int NewOpcode = (RC != &Hexagon::PredRegsRegClass) ? HII->getDotNewOp(MI) : in canPromoteToDotNew()
893 const MCInstrDesc &D = HII->get(NewOpcode); in canPromoteToDotNew()
461 int NewOpcode; promoteToDotNew() local
471 int NewOpcode = HII->getDotOldOp(MI); demoteToDotOld() local
890 int NewOpcode = (RC != &Hexagon::PredRegsRegClass) ? HII->getDotNewOp(MI) : canPromoteToDotNew() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMVEVPTBlockPass.cpp67 unsigned &NewOpcode) { in findVCMPToFoldIntoVPST() argument
82 NewOpcode = VCMPOpcodeToVPT(CmpMI->getOpcode()); in findVCMPToFoldIntoVPST()
83 if (NewOpcode == 0) in findVCMPToFoldIntoVPST()
275 unsigned NewOpcode; in InsertVPTBlocks()
277 if (MachineInstr *VCMP = findVCMPToFoldIntoVPST(MI, TRI, NewOpcode)) { in InsertVPTBlocks()
279 MIBuilder = BuildMI(Block, MI, DL, TII->get(NewOpcode)); in InsertVPTBlocks()
274 unsigned NewOpcode; InsertVPTBlocks() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.cpp138 int NewOpcode; in InsertSPImmInst() local
140 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6; in InsertSPImmInst()
141 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
146 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6; in InsertSPImmInst()
147 BuildMI(MBB, II, dl, TII.get(NewOpcode)) in InsertSPImmInst()
153 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6; in InsertSPImmInst()
154 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPostLegalizerCombiner.cpp114 bool matchCombine_s_mul_u64(MachineInstr &MI, unsigned &NewOpcode) const;
407 auto [LoadMI, NewOpcode] = MatchData; in matchCombineSignExtendInReg()
408 LoadMI->setDesc(TII.get(NewOpcode)); in matchCombineSignExtendInReg()
418 MachineInstr &MI, unsigned &NewOpcode) const { in matchCombineSignExtendInReg()
426 NewOpcode = AMDGPU::G_AMDGPU_S_MUL_U64_U32; in applyCombineSignExtendInReg()
432 NewOpcode = AMDGPU::G_AMDGPU_S_MUL_I64_I32; in applyCombineSignExtendInReg()
H A DSIShrinkInstructions.cpp385 unsigned NewOpcode = AMDGPU::getMIMGOpcode(Info->BaseOpcode, NewEncoding, in shrinkMadFma()
387 MI.setDesc(TII->get(NewOpcode)); in shrinkMadFma()
421 unsigned NewOpcode = AMDGPU::INSTRUCTION_LIST_END; in shrinkMadFma()
438 NewOpcode = AMDGPU::V_MADAK_F32; in shrinkMadFma()
441 NewOpcode = AMDGPU::V_FMAAK_F32; in shrinkMadFma()
444 NewOpcode = AMDGPU::V_MADAK_F16; in shrinkMadFma()
448 NewOpcode = ST->hasTrue16BitInsts() ? AMDGPU::V_FMAAK_F16_t16 in shrinkMadFma()
467 NewOpcode = AMDGPU::V_MADMK_F32; in shrinkMadFma()
470 NewOpcode = AMDGPU::V_FMAMK_F32; in shrinkMadFma()
473 NewOpcode in shrinkMadFma()
365 unsigned NewOpcode = AMDGPU::getMIMGOpcode(Info->BaseOpcode, NewEncoding, shrinkMIMG() local
401 unsigned NewOpcode = AMDGPU::INSTRUCTION_LIST_END; shrinkMadFma() local
[all...]
H A DGCNCreateVOPD.cpp76 int NewOpcode = in doReplace() local
79 assert(NewOpcode != -1 && in doReplace()
83 FirstMI->getDebugLoc(), SII->get(NewOpcode)) in doReplace()
H A DR600MachineCFGStructurizer.cpp200 void insertInstrEnd(MachineBasicBlock *MBB, int NewOpcode,
202 MachineInstr *insertInstrBefore(MachineBasicBlock *MBB, int NewOpcode,
204 MachineInstr *insertInstrBefore(MachineBasicBlock::iterator I, int NewOpcode);
205 void insertCondBranchBefore(MachineBasicBlock::iterator I, int NewOpcode,
208 MachineBasicBlock::iterator I, int NewOpcode,
435 int NewOpcode, const DebugLoc &DL) { in insertInstrEnd() argument
437 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL); in insertInstrEnd()
444 int NewOpcode, in insertInstrBefore() argument
447 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL); in insertInstrBefore()
457 MachineBasicBlock::iterator I, int NewOpcode) { in insertInstrBefore() argument
469 insertCondBranchBefore(MachineBasicBlock::iterator I,int NewOpcode,const DebugLoc & DL) insertCondBranchBefore() argument
482 insertCondBranchBefore(MachineBasicBlock * blk,MachineBasicBlock::iterator I,int NewOpcode,int RegNum,const DebugLoc & DL) insertCondBranchBefore() argument
[all...]
H A DSIWholeQuadMode.cpp754 unsigned NewOpcode = 0; in saveSCC()
757 NewOpcode = AMDGPU::S_AND_B32_term;
760 NewOpcode = AMDGPU::S_AND_B64_term; in splitBlock()
763 NewOpcode = AMDGPU::S_MOV_B32_term; in splitBlock()
766 NewOpcode = AMDGPU::S_MOV_B64_term; in splitBlock()
771 if (NewOpcode) in splitBlock()
772 TermMI->setDesc(TII->get(NewOpcode)); in splitBlock()
768 unsigned NewOpcode = 0; splitBlock() local
H A DSIOptimizeExecMasking.cpp578 const int NewOpcode = AMDGPU::getVCMPXOpFromVCMP(VCmp.getOpcode()); in optimizeVCMPSaveExecSequence() local
580 if (NewOpcode == -1) in optimizeVCMPSaveExecSequence()
600 VCmp.getDebugLoc(), TII->get(NewOpcode)); in optimizeVCMPSaveExecSequence()
H A DSIInstrInfo.cpp2603 unsigned NewOpcode = -1; in expandMovDPP64()
2605 NewOpcode = AMDGPU::S_LOAD_DWORDX8_IMM; in expandMovDPP64()
2607 NewOpcode = AMDGPU::S_LOAD_DWORDX4_IMM; in expandMovDPP64()
2611 const MCInstrDesc &TID = get(NewOpcode); in expandMovDPP64()
6981 unsigned NewOpcode = getVALUOp(Inst); in moveToVALUImpl()
6987 NewOpcode = AMDGPU::V_ADD_U64_PSEUDO; in moveToVALUImpl()
6990 NewOpcode = AMDGPU::V_SUB_U64_PSEUDO; in moveToVALUImpl()
7093 NewOpcode = AMDGPU::V_LSHLREV_B32_e64; in moveToVALUImpl()
7099 NewOpcode = AMDGPU::V_ASHRREV_I32_e64; in moveToVALUImpl()
7105 NewOpcode in moveToVALUImpl()
2552 unsigned NewOpcode = -1; reMaterialize() local
6858 unsigned NewOpcode = getVALUOp(Inst); moveToVALUImpl() local
[all...]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp524 unsigned NewOpcode = AluI->getOpcode(); in optLEAALU() local
525 NewMI1 = BuildMI(MBB, InsertPos, AluI->getDebugLoc(), TII->get(NewOpcode), in optLEAALU()
530 NewMI2 = BuildMI(MBB, InsertPos, AluI->getDebugLoc(), TII->get(NewOpcode), in optLEAALU()
588 unsigned NewOpcode = getADDrrFromLEA(MI.getOpcode()); in optTwoAddrLEA() local
594 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
599 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
612 unsigned NewOpcode = getINCDECFromLEA(MI.getOpcode(), IsINC); in optTwoAddrLEA() local
616 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
619 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
623 unsigned NewOpcode = getADDriFromLEA(MI.getOpcode(), Disp); in optTwoAddrLEA() local
[all …]
H A DX86InstrInfo.cpp5226 unsigned NewOpcode = 0; in optimizeCompareInstr()
5228 CASE_ND(A) NewOpcode = X86::B; \ in optimizeCompareInstr()
5247 CmpInstr.setDesc(get(NewOpcode)); in optimizeCompareInstr()
5252 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm || in optimizeCompareInstr()
5253 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm) in optimizeCompareInstr()
5121 unsigned NewOpcode = 0; optimizeCompareInstr() local
5543 unsigned NewOpcode = 0; ConvertALUrr2ALUri() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCOptAddrMode.cpp111 void changeToAddrMode(MachineInstr &Ldst, unsigned NewOpcode,
263 int NewOpcode = ARC::getPostIncOpcode(Ldst.getOpcode()); in tryToCombine() local
264 assert(NewOpcode > 0 && "No postincrement form found"); in tryToCombine()
266 changeToAddrMode(Ldst, NewOpcode, NewBaseReg, Add.getOperand(2)); in tryToCombine()
451 void ARCOptAddrMode::changeToAddrMode(MachineInstr &Ldst, unsigned NewOpcode, in changeToAddrMode() argument
469 Ldst.setDesc(AST->getInstrInfo()->get(NewOpcode)); in changeToAddrMode()
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.cpp173 int NewOpcode = -1; in encodeInstruction() local
176 NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6); in encodeInstruction()
177 if (NewOpcode == -1) in encodeInstruction()
178 NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6); in encodeInstruction()
181 NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips); in encodeInstruction()
184 if (NewOpcode == -1) in encodeInstruction()
185 NewOpcode = Mips::Dsp2MicroMips(Opcode, Mips::Arch_mmdsp); in encodeInstruction()
187 if (NewOpcode != -1) { in encodeInstruction()
191 TmpInst.setOpcode (NewOpcode); in encodeInstruction()
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.cpp228 unsigned NewOpcode = getOppositeALULoOpcode(MI.getOpcode()); in eliminateFrameIndex() local
233 BuildMI(*MI.getParent(), II, DL, TII->get(NewOpcode), in eliminateFrameIndex()
/freebsd-src/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp67 // each having the opcode given by NewOpcode.
69 unsigned NewOpcode) const { in splitMove()
95 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm()); in splitMove()
96 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm()); in splitMove()
143 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset); in splitAdjDynAlloc() local
144 assert(NewOpcode && "No support for huge argument lists yet"); in splitAdjDynAlloc()
145 MI->setDesc(get(NewOpcode)); in splitAdjDynAlloc()
1090 unsigned NewOpcode; in foldMemoryOperandImpl()
1092 NewOpcode = SystemZ::RISBG; in foldMemoryOperandImpl()
1095 NewOpcode in foldMemoryOperandImpl()
980 unsigned NewOpcode; convertToThreeAddress() local
[all...]
H A DSystemZFrameLowering.cpp715 unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); in emitEpilogue()
719 if (!NewOpcode) { in emitEpilogue()
724 NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); in emitEpilogue()
725 assert(NewOpcode && "No restore instruction available"); in emitEpilogue()
728 MBBI->setDesc(ZII->get(NewOpcode)); in emitEpilogue()
727 unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); emitEpilogue() local
H A DSystemZInstrInfo.h189 void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
/freebsd-src/contrib/llvm-project/llvm/lib/Target/PowerPC/AsmParser/
H A DPPCAsmParser.cpp1663 std::string NewOpcode; in ParseInstruction()
1665 NewOpcode = std::string(Name); in ParseInstruction()
1666 NewOpcode += '+'; in ParseInstruction()
1667 Name = NewOpcode; in ParseInstruction()
1670 NewOpcode = std::string(Name); in ParseInstruction()
1671 NewOpcode += '-'; in ParseInstruction()
1672 Name = NewOpcode; in ParseInstruction()
1678 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. in ParseInstruction()
1686 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. in ParseInstruction()
1661 std::string NewOpcode; ParseInstruction() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp1734 unsigned NewOpcode = 0u; in eliminateFrameIndex() local
1782 NewOpcode = ImmToIdxMap.find(OpC)->second; in eliminateFrameIndex()
1783 MI.setDesc(TII.get(NewOpcode)); in eliminateFrameIndex()
1802 if (NewOpcode == PPC::LQX_PSEUDO || NewOpcode == PPC::STQX_PSEUDO) { in eliminateFrameIndex()
1808 MI.setDesc(TII.get(NewOpcode == PPC::LQX_PSEUDO ? PPC::LQ : PPC::STQ)); in eliminateFrameIndex()
H A DPPCISelDAGToDAG.cpp7405 unsigned NewOpcode; in PeepholePPC64ZExt()
7409 case PPC::RLWINM: NewOpcode = PPC::RLWINM8; break; in PeepholePPC64ZExt()
7410 case PPC::RLWNM: NewOpcode = PPC::RLWNM8; break; in PeepholePPC64ZExt()
7411 case PPC::SLW: NewOpcode = PPC::SLW8; break; in PeepholePPC64ZExt()
7412 case PPC::SRW: NewOpcode = PPC::SRW8; break; in PeepholePPC64ZExt()
7413 case PPC::LI: NewOpcode = PPC::LI8; break; in PeepholePPC64ZExt()
7414 case PPC::LIS: NewOpcode = PPC::LIS8; break; in PeepholePPC64ZExt()
7415 case PPC::LHBRX: NewOpcode = PPC::LHBRX8; break; in PeepholePPC64ZExt()
7416 case PPC::LWBRX: NewOpcode = PPC::LWBRX8; break; in PeepholePPC64ZExt()
7417 case PPC::CNTLZW: NewOpcode in PeepholePPC64ZExt()
7394 unsigned NewOpcode; PeepholePPC64ZExt() local
[all...]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsDelaySlotFiller.cpp563 unsigned NewOpcode = TII->getEquivalentCompactForm(Branch); in replaceWithCompactBranch()
564 Branch = TII->genInstrWithNewOpc(NewOpcode, Branch); in replaceWithCompactBranch()
562 unsigned NewOpcode = TII->getEquivalentCompactForm(Branch); replaceWithCompactBranch() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ExpandPseudoInsts.cpp563 int NewOpcode; in expand_DestructiveOp()
565 if ((NewOpcode = AArch64::getSVERevInstr(Opcode)) != -1) in expand_DestructiveOp()
566 Opcode = NewOpcode; in expand_DestructiveOp()
568 else if ((NewOpcode = AArch64::getSVENonRevInstr(Opcode)) != -1) in expand_DestructiveOp()
569 Opcode = NewOpcode; in expand_DestructiveOp()
550 int NewOpcode; expand_DestructiveOp() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp1030 int NewOpcode = in convertMIMGInst()
1032 if (NewOpcode == -1) in convertMIMGInst()
1038 auto DataRCID = MCII->get(NewOpcode).operands()[VDataIdx].RegClass; in convertMIMGInst()
1064 auto AddrRCID = MCII->get(NewOpcode).operands()[VAddrSAIdx].RegClass; in convertMIMGInst()
1071 MI.setOpcode(NewOpcode); in convertMIMGInst()
1113 int NewOpcode = convertMIMGInst() local

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