Searched refs:MaskImm (Results 1 – 4 of 4) sorted by relevance
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FixupInstTuning.cpp | 136 unsigned MaskImm = MI.getOperand(NumOperands - 1).getImm(); in processInstruction() local
140 MI.addOperand(MachineOperand::CreateImm(MaskImm)); in processInstruction()
151 unsigned MaskImm = MI.getOperand(NumOperands - 1).getImm(); in processInstruction() local
155 MI.addOperand(MachineOperand::CreateImm(MaskImm)); in processInstruction()
186 auto ProcessUNPCK = [&](unsigned NewOpc, unsigned MaskImm) -> bool { in processInstruction() argument
191 MI.addOperand(MachineOperand::CreateImm(MaskImm)); in processInstruction()
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 1808 int64_t MaskImm = (Size == 1) ? 255 : 65535; in emitAtomicBinaryPartword()
1824 .addReg(Mips::ZERO).addImm(MaskImm); in emitAtomicBinaryPartword()
1995 int64_t MaskImm = (Size == 1) ? 255 : 65535; in emitAtomicCmpSwapPartword()
2011 .addReg(Mips::ZERO).addImm(MaskImm); in emitAtomicCmpSwapPartword()
2016 .addReg(CmpVal).addImm(MaskImm); in emitAtomicCmpSwapPartword()
2020 .addReg(NewVal).addImm(MaskImm); in emitAtomicCmpSwapPartword()
1792 int64_t MaskImm = (Size == 1) ? 255 : 65535; emitAtomicBinaryPartword() local
1979 int64_t MaskImm = (Size == 1) ? 255 : 65535; emitAtomicCmpSwapPartword() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 2573 // Value2 = AND Value, MaskImm in isBitfieldExtractOp()
2576 // with MaskImm >> ShiftImm to search for the bit width. in isBitfieldExtractOp()
2580 // UBFM Value, ShiftImm, Log2_64(MaskImm) in isBitfieldExtractOp()
3239 // Generate a BFI/BFXIL from 'or (and X, MaskImm), OrImm' iff the value being in isWorthFoldingIntoOrrWithShift()
3260 uint64_t MaskImm; in tryOrrWithShift()
3264 !isOpcWithIntImmediate(And.getNode(), ISD::AND, MaskImm)) in tryOrrWithShift()
3826 uint64_t MaskImm; in tryReadRegister()
3827 if (!isOpcWithIntImmediate(ShiftAmt.getNode(), ISD::AND, MaskImm) && in tryReadRegister()
3828 !isOpcWithIntImmediate(ShiftAmt.getNode(), AArch64ISD::ANDS, MaskImm)) in tryReadRegister()
3831 if ((unsigned)llvm::countr_one(MaskImm) < Bit in tryReadRegister()
3105 uint64_t MaskImm; tryBitfieldInsertOpFromOrAndImm() local
3671 uint64_t MaskImm; tryShiftAmountMod() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 2407 int64_t MaskImm; in earlySelect()
2411 m_OneNonDBGUse(m_GAnd(m_Reg(MaskSrc), m_ICst(MaskImm)))))) in earlySelect()
2414 if (ShiftImm > Size || ((1ULL << ShiftImm) - 1ULL) != uint64_t(MaskImm)) in earlySelect()
2391 int64_t MaskImm; earlySelect() local
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