| /freebsd-src/contrib/llvm-project/llvm/lib/MCA/ |
| H A D | InstrBuilder.cpp | 222 static void computeMaxLatency(InstrDesc &ID, const MCInstrDesc &MCDesc, in computeMaxLatency()
226 if (MCDesc.isCall()) { in computeMaxLatency()
239 static Error verifyOperands(const MCInstrDesc &MCDesc, const MCInst &MCI) { in verifyOperands()
242 unsigned NumExplicitDefs = MCDesc.getNumDefs(); in verifyOperands()
254 if (MCDesc.hasOptionalDef()) { in verifyOperands()
256 const MCOperand &Op = MCI.getOperand(MCDesc.getNumOperands() - 1); in verifyOperands()
270 const MCInstrDesc &MCDesc = MCII.get(MCI.getOpcode()); in populateWrites()
278 // 2. Uses start at index #(MCDesc.getNumDefs()). in populateWrites()
302 // MCDesc reports: in populateWrites()
317 unsigned NumExplicitDefs = MCDesc in populateWrites()
221 computeMaxLatency(InstrDesc & ID,const MCInstrDesc & MCDesc,const MCSchedClassDesc & SCDesc,const MCSubtargetInfo & STI) computeMaxLatency() argument
236 verifyOperands(const MCInstrDesc & MCDesc,const MCInst & MCI) verifyOperands() argument
267 const MCInstrDesc &MCDesc = MCII.get(MCI.getOpcode()); populateWrites() local
436 const MCInstrDesc &MCDesc = MCII.get(MCI.getOpcode()); populateReads() local
520 const MCInstrDesc &MCDesc = MCII.get(Opcode); createInstrDescImpl() local
649 const MCInstrDesc &MCDesc = MCII.get(MCI.getOpcode()); createInstruction() local
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| H A D | Support.cpp | 99 const MCProcResourceDesc &MCDesc = *SM.getProcResource(I); in computeBlockRThroughput() local
100 double Throughput = static_cast<double>(ReleaseAtCycles) / MCDesc.NumUnits; in computeBlockRThroughput()
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/SPIRV/MCTargetDesc/ |
| H A D | SPIRVMCCodeEmitter.cpp | 64 const MCInstrDesc &MCDesc = MII.get(MI.getOpcode()); in hasType() local
66 if (MCDesc.getNumDefs() == 1 && MCDesc.getNumOperands() >= 2) { in hasType()
68 auto &DefOpInfo = MCDesc.operands()[0]; in hasType()
69 auto &FirstArgOpInfo = MCDesc.operands()[1]; in hasType()
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| H A D | SPIRVInstPrinter.cpp | 121 const MCInstrDesc &MCDesc = MII.get(OpCode); in printInst()
122 if (MCDesc.isVariadic()) { in printInst()
123 const unsigned NumFixedOps = MCDesc.getNumOperands(); in printInst()
126 if (NumFixedOps > 0 && MCDesc.operands()[LastFixedIndex].OperandType == in printInst()
228 const MCInstrDesc &MCDesc = MII.get(MI->getOpcode()); in printOpExtInst()
229 unsigned NumFixedOps = MCDesc.getNumOperands(); in printOpExtInst()
243 const MCInstrDesc &MCDesc = MII.get(MI->getOpcode()); in printOpDecorate()
244 unsigned NumFixedOps = MCDesc.getNumOperands(); in printOpDecorate()
119 const MCInstrDesc &MCDesc = MII.get(OpCode); printInst() local
226 const MCInstrDesc &MCDesc = MII.get(MI->getOpcode()); printOpExtInst() local
241 const MCInstrDesc &MCDesc = MII.get(MI->getOpcode()); printOpDecorate() local
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| /freebsd-src/contrib/llvm-project/llvm/tools/llvm-mca/Views/ |
| H A D | InstructionInfoView.cpp | 118 const MCInstrDesc &MCDesc = MCII.get(Inst.getOpcode()); in collectData() local
125 ? MCDesc.getSchedClass() in collectData()
141 IIVDEntry.mayLoad = MCDesc.mayLoad(); in collectData()
142 IIVDEntry.mayStore = MCDesc.mayStore(); in collectData()
143 IIVDEntry.hasUnmodeledSideEffects = MCDesc.hasUnmodeledSideEffects(); in collectData()
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| H A D | TimelineView.cpp | 49 const MCProcResourceDesc &MCDesc = *SM.getProcResource(Buffer); in onReservedBuffers() local
50 if (!BufferInfo.first || BufferInfo.second > MCDesc.BufferSize) { in onReservedBuffers()
52 BufferInfo.second = MCDesc.BufferSize; in onReservedBuffers()
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| /freebsd-src/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | SubtargetEmitter.cpp | 1432 MCSchedClassDesc &MCDesc = SCTab[SCIdx];
1437 OS << MCDesc.NumMicroOps << ", " << (MCDesc.BeginGroup ? "true" : "false") in EmitProcessorModels()
1438 << ", " << (MCDesc.EndGroup ? "true" : "false") << ", " in EmitProcessorModels()
1439 << (MCDesc.RetireOOO ? "true" : "false") << ", " in EmitProcessorModels()
1440 << format("%2d", MCDesc.WriteProcResIdx) << ", " in EmitProcessorModels()
1441 << MCDesc.NumWriteProcResEntries << ", " in EmitProcessorModels()
1442 << format("%2d", MCDesc.WriteLatencyIdx) << ", " in EmitProcessorModels()
1443 << MCDesc.NumWriteLatencyEntries << ", " in EmitProcessorModels()
1444 << format("%2d", MCDesc in EmitProcessorModels()
1412 MCSchedClassDesc &MCDesc = SCTab[SCIdx]; EmitSchedClassTables() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RenameIndependentSubregs.cpp | 332 const MCInstrDesc &MCDesc = TII->get(TargetOpcode::IMPLICIT_DEF); in computeMainRangesFixFlags() local
334 DebugLoc(), MCDesc, Reg); in computeMainRangesFixFlags()
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