| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstPropagation.cpp | 633 RegisterSubReg DefR(MD); in visitPHI() local
634 assert(DefR.Reg.isVirtual()); in visitPHI()
639 if (DefR.SubReg) { in visitPHI()
641 const LatticeCell &T = Cells.get(DefR.Reg); in visitPHI()
643 Cells.update(DefR.Reg, Bottom); in visitPHI()
645 visitUsesOf(DefR.Reg); in visitPHI()
649 LatticeCell DefC = Cells.get(DefR.Reg); in visitPHI()
676 Cells.update(DefR.Reg, DefC); in visitPHI()
681 visitUsesOf(DefR.Reg); in visitPHI()
703 RegisterSubReg DefR(MO); in visitNonBranch() local
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| H A D | HexagonGenMux.cpp | 108 unsigned DefR, PredR; member
115 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(&D1), in MuxInfo()
337 auto NewMux = BuildMI(B, MX.At, DL, HII->get(MxOpc), MX.DefR) in genMuxInBlock()
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| H A D | HexagonConstExtenders.cpp | 1533 llvm::Register DefR = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass); in insertInitializer()
1546 // DefR = PS_fi Rb,##EV in insertInitializer()
1547 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::PS_fi), DefR) in insertInitializer()
1553 // DefR = ##EV in insertInitializer()
1554 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_tfrsi), DefR) in insertInitializer()
1558 // DefR = sub(##EV,Rb) in insertInitializer()
1559 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_subri), DefR) in insertInitializer()
1563 // DefR = add(Rb,##EV) in insertInitializer()
1564 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_addi), DefR) in insertInitializer()
1572 // DefR in insertInitializer()
1530 llvm::Register DefR = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass); insertInitializer() local
1925 Register DefR = insertInitializer(Q.first, P.first); replaceExtenders() local
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| H A D | HexagonEarlyIfConv.cpp | 441 Register DefR = MI.getOperand(0).getReg(); in isValid() local
442 if (isPredicate(DefR)) in isValid()
991 Register DefR = PN->getOperand(0).getReg(); in eliminatePhis() local
998 const TargetRegisterClass *RC = MRI->getRegClass(DefR); in eliminatePhis()
1003 MRI->replaceRegWith(DefR, NewR); in eliminatePhis()
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| H A D | HexagonBitSimplify.cpp | 1250 Register DefR = UseI.getOperand(0).getReg(); in computeUsedBits() local
1251 if (!DefR.isVirtual()) in computeUsedBits()
1253 Pending.push_back(DefR); in computeUsedBits()
2955 unsigned DefR;
2962 bool isBitShuffle(const MachineInstr *MI, unsigned DefR) const;
2963 bool isStoreInput(const MachineInstr *MI, unsigned DefR) const;
2981 DefR = HexagonLoopRescheduling::getDefReg(&P); in PhiInfo()
3016 unsigned DefR) const { in isBitShuffle()
3168 dbgs() << ' ' << printReg(I.DefR, HRI) << "=phi(" in processLoop()
3196 Register DefR in processLoop()
2954 unsigned DefR; global() member
3195 Register DefR = Defs.find_first(); processLoop() local
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| H A D | HexagonOptAddrMode.cpp | 99 bool analyzeUses(unsigned DefR, const NodeList &UNodeList,
807 Register DefR = MI->getOperand(0).getReg(); in processBlock()
812 if (!analyzeUses(DefR, UNodeList, InstrEvalResult, SizeInc)) in processBlock()
836 if (op.isReg() && op.isUse() && DefR == op.getReg()) in processBlock()
840 // This could happen, for example, when DefR = R4, but the used in processBlock()
805 Register DefR = MI->getOperand(0).getReg(); processBlock() local
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| H A D | HexagonBitTracker.cpp | 966 if (unsigned DefR = getUniqueDefVReg(MI)) { in evaluate() local
967 if (MRI.getRegClass(DefR) == &Hexagon::PredRegsRegClass) { in evaluate()
968 BT::RegisterRef PD(DefR, 0); in evaluate()
971 RegisterCell RC = RegisterCell::self(DefR, RW); in evaluate()
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