| /freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineCombiner.cpp | 154 MachineInstr *DefInstr = nullptr; in getOperandDef() local
157 DefInstr = MRI->getUniqueVRegDef(MO.getReg()); in getOperandDef()
158 return DefInstr; in getOperandDef()
228 MachineInstr *DefInstr = InsInstrs[II->second]; in getDepth()
229 assert(DefInstr && in getDepth()
233 DefInstr->findRegisterDefOperandIdx(MO.getReg(), /*TRI=*/nullptr); in getDepth()
236 LatencyOp = TSchedModel.computeOperandLatency(DefInstr, DefIdx, in getDepth()
239 MachineInstr *DefInstr = getOperandDef(MO); in getDepth()
240 if (DefInstr && (TII->getMachineCombinerTraceStrategy() != in getDepth() local
242 DefInstr in getDepth()
231 MachineInstr *DefInstr = InsInstrs[II->second]; getDepth() local
[all...] |
| H A D | LiveRangeShrink.cpp | 201 MachineInstr &DefInstr = *MRI.def_instr_begin(Reg); in runOnMachineFunction() local
202 if (!TII.isCopyInstr(DefInstr)) in runOnMachineFunction()
204 Insert = FindDominatedInstruction(DefInstr, Insert, IOM); in runOnMachineFunction()
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| H A D | MachineUniformityAnalysis.cpp | 145 auto *DefInstr = Def->getParent(); in isDivergentUse() local
147 return isTemporalDivergent(*UseInstr->getParent(), *DefInstr); in isDivergentUse()
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| H A D | ScheduleDAGInstrs.cpp | 317 MachineInstr *DefInstr = DefSU->getInstr(); in addPhysRegDeps() local
318 MachineOperand &DefMO = DefInstr->getOperand(I->OpIdx); in addPhysRegDeps()
324 SchedModel.computeOutputLatency(MI, OperIdx, DefInstr)); in addPhysRegDeps()
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SILowerControlFlow.cpp | 741 MachineInstr *DefInstr = MRI->getVRegDef(InputReg); lowerInitExec() local
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| H A D | AMDGPUMachineCFGStructurizer.cpp | 327 MachineInstr *DefInstr, const MachineRegisterInfo *MRI,
331 MachineInstr *DefInstr,
673 MachineInstr *DefInstr,
700 if ((&(*MII)) == DefInstr) { in storeLiveOutReg()
713 MachineInstr *DefInstr,
1928 MachineInstr *DefInstr = getDefInstr(SourceReg); in insertChainedPHI()
1929 if (DefInstr->isPHI() && DefInstr->getParent() == CodeBB && IsSingleBB) { in insertChainedPHI()
1938 storePHILinearizationInfoDest(DestReg, *DefInstr); in insertChainedPHI()
1942 DefInstr in insertChainedPHI()
675 storeLiveOutReg(MachineBasicBlock * MBB,Register Reg,MachineInstr * DefInstr,const MachineRegisterInfo * MRI,const TargetRegisterInfo * TRI,PHILinearize & PHIInfo) storeLiveOutReg() argument
715 storeLiveOutRegRegion(RegionMRT * Region,Register Reg,MachineInstr * DefInstr,const MachineRegisterInfo * MRI,const TargetRegisterInfo * TRI,PHILinearize & PHIInfo) storeLiveOutRegRegion() argument
1930 MachineInstr *DefInstr = getDefInstr(SourceReg); insertChainedPHI() local
[all...] |
| H A D | SIPeepholeSDWA.cpp | 299 MachineInstr *DefInstr = MRI->getUniqueVRegDef(Reg->getReg()); in findSingleRegDef()
300 if (!DefInstr) in findSingleRegDef()
303 for (auto &DefMO : DefInstr->defs()) { in findSingleRegDef()
292 MachineInstr *DefInstr = MRI->getUniqueVRegDef(Reg->getReg()); findSingleRegDef() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | UniformityAnalysis.cpp | 99 if (const auto *DefInstr = dyn_cast<Instruction>(V)) { in isDivergentUse() local
101 return isTemporalDivergent(*UseInstr->getParent(), *DefInstr); in isDivergentUse()
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVBuiltins.cpp | 2003 MachineInstr *DefInstr = MRI->getUniqueVRegDef(GlobalWorkSize); in parseTypeString()
2004 assert(DefInstr && isSpvIntrinsic(*DefInstr, Intrinsic::spv_gep) && in parseTypeString()
2005 DefInstr->getOperand(3).isReg()); in parseTypeString()
2006 Register GWSPtr = DefInstr->getOperand(3).getReg(); in parseTypeString()
1498 MachineInstr *DefInstr = MRI->getUniqueVRegDef(GlobalWorkSize); buildNDRange() local
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