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/freebsd-src/contrib/llvm-project/compiler-rt/lib/builtins/cpu_model/
H A Dx86.c379 // We select CPU strings to match the code in Host.cpp, but we don't use them in getIntelProcessorTypeAndSubtype()
381 const char *CPU = 0; in getIntelProcessorTypeAndSubtype()
393 CPU = "core2"; in getIntelProcessorTypeAndSubtype()
402 CPU = "penryn"; in getIntelProcessorTypeAndSubtype()
407 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. in getIntelProcessorTypeAndSubtype()
411 CPU = "nehalem"; in getIntelProcessorTypeAndSubtype()
419 CPU = "westmere"; in getIntelProcessorTypeAndSubtype()
426 CPU = "sandybridge"; in getIntelProcessorTypeAndSubtype()
432 CPU = "ivybridge"; in getIntelProcessorTypeAndSubtype()
442 CPU in getIntelProcessorTypeAndSubtype()
311 const char *CPU = 0; getIntelProcessorTypeAndSubtype() local
599 const char *CPU = 0; getAMDProcessorTypeAndSubtype() local
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/freebsd-src/contrib/llvm-project/llvm/lib/TargetParser/
H A DHost.cpp58 // Implementations of the CPU detection routines
164 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line in getHostCPUNameForARM()
169 // Look for the CPU implementer line. in getHostCPUNameForARM()
174 if (Lines[I].starts_with("CPU implementer")) in getHostCPUNameForARM()
178 if (Lines[I].starts_with("CPU part")) in getHostCPUNameForARM()
189 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The in getHostCPUNameForARM()
285 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The in getHostCPUNameForARM()
293 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The in getHostCPUNameForARM()
316 // Look for the CPU variant line, whose value is a 1 digit hexadecimal in getHostCPUNameForARM()
319 if (I.consume_front("CPU varian in getHostCPUNameForARM()
688 StringRef CPU; getIntelProcessorTypeAndSubtype() local
1054 StringRef CPU; getAMDProcessorTypeAndSubtype() local
1359 StringRef CPU; getHostCPUName() local
2030 std::string CPU = std::string(sys::getHostCPUName()); printDefaultTargetAndDetectedCPU() local
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H A DRISCVTargetParser.cpp46 static const CPUInfo *getCPUInfoByName(StringRef CPU) { in getCPUInfoByName()
48 if (C.Name == CPU) in hasFastUnalignedAccess() argument
53 bool hasFastScalarUnalignedAccess(StringRef CPU) { in parseCPU() argument
54 const CPUInfo *Info = getCPUInfoByName(CPU); in parseCPU()
58 bool hasFastVectorUnalignedAccess(StringRef CPU) { in parseCPU()
59 const CPUInfo *Info = getCPUInfoByName(CPU); in parseCPU()
63 bool parseCPU(StringRef CPU, bool IsRV64) { in parseTuneCPU()
64 const CPUInfo *Info = getCPUInfoByName(CPU); in parseTuneCPU()
81 // Fallback to parsing as a CPU.
85 StringRef getMArchFromMcpu(StringRef CPU) { in fillValidCPUArchList()
41 getCPUInfoByName(StringRef CPU) getCPUInfoByName() argument
75 getMArchFromMcpu(StringRef CPU) getMArchFromMcpu() argument
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFSubtarget.cpp46 BPFSubtarget &BPFSubtarget::initializeSubtargetDependencies(StringRef CPU, in initializeSubtargetDependencies() argument
49 initSubtargetFeatures(CPU, FS); in initializeSubtargetDependencies()
50 ParseSubtargetFeatures(CPU, /*TuneCPU*/ CPU, FS); in initializeSubtargetDependencies()
67 void BPFSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { in initSubtargetFeatures() argument
68 if (CPU == "probe") in initSubtargetFeatures()
69 CPU = sys::detail::getHostCPUNameForBPF(); in initSubtargetFeatures()
70 if (CPU == "generic" || CPU == "v1") in initSubtargetFeatures()
72 if (CPU == "v2") { in initSubtargetFeatures()
76 if (CPU == "v3") { in initSubtargetFeatures()
82 if (CPU == "v4") { in initSubtargetFeatures()
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRSubtarget.cpp30 AVRSubtarget::AVRSubtarget(const Triple &TT, const std::string &CPU, in AVRSubtarget() argument
32 : AVRGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), InstrInfo(*this), in AVRSubtarget()
33 TLInfo(TM, initializeSubtargetDependencies(CPU, FS, TM)) { in AVRSubtarget()
35 ParseSubtargetFeatures(CPU, /*TuneCPU*/ CPU, FS); in AVRSubtarget()
39 AVRSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS, in initializeSubtargetDependencies() argument
42 ParseSubtargetFeatures(CPU, /*TuneCPU*/ CPU, FS); in initializeSubtargetDependencies()
/freebsd-src/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblySubtarget.cpp28 WebAssemblySubtarget::initializeSubtargetDependencies(StringRef CPU, in initializeSubtargetDependencies() argument
33 if (CPU.empty()) in initializeSubtargetDependencies()
34 CPU = "generic"; in initializeSubtargetDependencies()
36 ParseSubtargetFeatures(CPU, /*TuneCPU*/ CPU, FS); in initializeSubtargetDependencies()
41 const std::string &CPU, in WebAssemblySubtarget() argument
44 : WebAssemblyGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), in WebAssemblySubtarget()
45 TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)), in WebAssemblySubtarget()
/freebsd-src/contrib/llvm-project/llvm/lib/MC/
H A DMCSubtargetInfo.cpp106 // Determine the length of the longest CPU and Feature entries. in Help()
110 // Print the CPU table. in Help()
112 for (auto &CPU : CPUTable) in Help() local
113 errs() << format(" %-*s - Select the %s processor.\n", MaxCPULen, CPU.Key, in Help()
114 CPU.Key); in Help()
138 // Print the CPU table. in cpuHelp()
140 for (auto &CPU : CPUTable) in cpuHelp() local
141 errs() << "\t" << CPU.Key << "\n"; in cpuHelp()
151 static FeatureBitset getFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS, in getFeatures() argument
159 assert(llvm::is_sorted(ProcDesc) && "CPU tabl in getFeatures()
209 InitMCProcessorInfo(StringRef CPU,StringRef TuneCPU,StringRef FS) InitMCProcessorInfo() argument
220 setDefaultFeatures(StringRef CPU,StringRef TuneCPU,StringRef FS) setDefaultFeatures() argument
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/freebsd-src/contrib/llvm-project/clang/lib/Basic/Targets/
H A DHexagon.cpp30 if (CPU == "hexagonv5") { in getTargetDefines()
37 } else if (CPU == "hexagonv55") { in getTargetDefines()
42 } else if (CPU == "hexagonv60") { in getTargetDefines()
48 } else if (CPU == "hexagonv62") { in getTargetDefines()
52 } else if (CPU == "hexagonv65") { in getTargetDefines()
56 } else if (CPU == "hexagonv66") { in getTargetDefines()
60 } else if (CPU == "hexagonv67") { in getTargetDefines()
63 } else if (CPU == "hexagonv67t") { in getTargetDefines()
66 } else if (CPU == "hexagonv68") { in getTargetDefines()
69 } else if (CPU in getTargetDefines()
111 initFeatureMap(llvm::StringMap<bool> & Features,DiagnosticsEngine & Diags,StringRef CPU,const std::vector<std::string> & FeaturesVec) const initFeatureMap() argument
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H A DMips.cpp32 return llvm::StringSwitch<bool>(CPU) in processorSupportsGPR64()
193 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); in getTargetDefines()
194 if (CPU == "octeon+") in getTargetDefines()
197 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); in getTargetDefines()
199 if (StringRef(CPU).starts_with("octeon")) in getTargetDefines()
202 if (CPU != "mips1") { in getTargetDefines()
242 Diags.Report(diag::err_target_unsupported_cpu_for_micromips) << CPU; in validateTarget()
246 // 64-bit ABI's require 64-bit CPU's. in validateTarget()
248 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; in validateTarget()
261 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfpxx" << CPU; in validateTarget()
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H A DMips.h43 std::string CPU; variable
78 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; in MipsTargetInfo()
85 return CPU == "mips32r6" || CPU == "mips64r6"; in isIEEE754_2008Default()
89 if (CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64") in isFP64Default()
91 else if (CPU == "mips1")
175 CPU = Name;
179 const std::string &getCPU() const { return CPU; } in initFeatureMap()
182 StringRef CPU, in initFeatureMap()
184 if (CPU in initFeatureMap()
177 initFeatureMap(llvm::StringMap<bool> & Features,DiagnosticsEngine & Diags,StringRef CPU,const std::vector<std::string> & FeaturesVec) initFeatureMap() argument
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H A DBPF.cpp33 std::string CPU = getTargetOpts().CPU; in getTargetDefines() local
34 if (CPU == "probe") { in getTargetDefines()
41 if (CPU.empty() || CPU == "generic" || CPU == "v1") { in getTargetDefines()
46 std::string CpuVerNumStr = CPU.substr(1); in getTargetDefines()
/freebsd-src/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchSubtarget.cpp28 const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, in initializeSubtargetDependencies() argument
31 if (CPU.empty() || CPU == "generic") in initializeSubtargetDependencies()
32 CPU = Is64Bit ? "generic-la64" : "generic-la32"; in initializeSubtargetDependencies()
35 TuneCPU = CPU; in initializeSubtargetDependencies()
37 ParseSubtargetFeatures(CPU, TuneCPU, FS); in initializeSubtargetDependencies()
59 // Initialize CPU specific properties. We should add a tablegen feature for in initializeProperties()
84 LoongArchSubtarget::LoongArchSubtarget(const Triple &TT, StringRef CPU, in LoongArchSubtarget() argument
88 : LoongArchGenSubtargetInfo(TT, CPU, TuneCPU, FS), in LoongArchSubtarget()
90 initializeSubtargetDependencies(TT, CPU, TuneCP in LoongArchSubtarget()
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCTargetDesc.cpp48 /// Select the Mips CPU for the given triple and cpu name.
49 StringRef MIPS_MC::selectMipsCPU(const Triple &TT, StringRef CPU) { in selectMipsCPU() argument
50 if (CPU.empty() || CPU == "generic") { in selectMipsCPU()
53 CPU = "mips32r6"; in selectMipsCPU()
55 CPU = "mips64r6"; in selectMipsCPU()
58 CPU = "mips32"; in selectMipsCPU()
60 CPU = "mips64"; in selectMipsCPU()
63 return CPU; in selectMipsCPU()
79 StringRef CPU, StringRe in createMipsMCSubtargetInfo() argument
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/freebsd-src/contrib/llvm-project/compiler-rt/lib/xray/
H A Dxray_fdr_controller.h147 uint16_t CPU) XRAY_NEVER_INSTRUMENT { in recordPreamble() argument
148 if (UNLIKELY(LatestCPU != CPU || LatestTSC == 0)) { in recordPreamble()
152 LatestCPU = CPU; in recordPreamble()
157 W.writeMetadata<MetadataRecord::RecordKinds::NewCPUId>(CPU, TSC); in recordPreamble()
161 DCHECK_EQ(LatestCPU, CPU); in recordPreamble()
182 uint16_t CPU) XRAY_NEVER_INSTRUMENT { in rewindRecords() argument
245 uint16_t CPU) XRAY_NEVER_INSTRUMENT { in functionEnter() argument
250 auto PreambleStatus = recordPreamble(TSC, CPU); in functionEnter()
269 uint16_t CPU) XRAY_NEVER_INSTRUMENT { in functionTailExit() argument
276 auto PreambleStatus = recordPreamble(TSC, CPU); in functionTailExit()
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/freebsd-src/contrib/llvm-project/clang/lib/Driver/ToolChains/Arch/
H A DM68k.cpp34 std::string CPU = std::string(llvm::sys::getHostCPUName()); in getM68kTargetCPU() local
35 if (!CPU.empty() && CPU != "generic") in getM68kTargetCPU()
36 return CPU; in getM68kTargetCPU()
79 std::string CPU = m68k::getM68kTargetCPU(Args); in addFloatABIFeatures() local
81 if ((A && (CPU == "M68000" || CPU == "M68010")) || in addFloatABIFeatures()
83 CPU == "M68020") in addFloatABIFeatures()
85 else if (CPU == "M68030" || CPU == "M68040" || CPU == "M68060") in addFloatABIFeatures()
H A DAArch64.cpp23 /// \returns true if the given triple can determine the default CPU type even
34 std::string CPU; in getAArch64TargetCPU() local
38 CPU = Mcpu.split("+").first.lower(); in getAArch64TargetCPU()
41 CPU = llvm::AArch64::resolveCPUAlias(CPU); in getAArch64TargetCPU()
43 // Handle CPU name is 'native'. in getAArch64TargetCPU()
44 if (CPU == "native") in getAArch64TargetCPU()
47 if (CPU.size()) in getAArch64TargetCPU()
48 return CPU; in getAArch64TargetCPU()
65 // Make sure we pick the appropriate Apple CPU whe in getAArch64TargetCPU()
93 DecodeAArch64Mcpu(const Driver & D,StringRef Mcpu,StringRef & CPU,llvm::AArch64::ExtensionSet & Extensions) DecodeAArch64Mcpu() argument
146 StringRef CPU; getAArch64ArchFeaturesFromMcpu() local
180 StringRef CPU; getAArch64MicroArchFeaturesFromMcpu() local
443 std::string CPU = getCPUName(D, Args, Triple); getAArch64TargetFeatures() local
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H A DRISCV.cpp62 // Try inverting Is64Bit in case the CPU is valid, but for the wrong target. in getRISCFeaturesFromMcpu()
86 StringRef CPU = A->getValue(); in getRISCVTargetFeatures() local
87 if (CPU == "native") in getRISCVTargetFeatures()
88 CPU = llvm::sys::getHostCPUName(); in getRISCVTargetFeatures()
90 getRISCFeaturesFromMcpu(D, A, Triple, CPU, Features); in getRISCVTargetFeatures()
92 if (llvm::RISCV::hasFastScalarUnalignedAccess(CPU)) in getRISCVTargetFeatures()
94 if (llvm::RISCV::hasFastVectorUnalignedAccess(CPU)) in getRISCVTargetFeatures()
178 // unaligned-scalar-mem is enabled if the CPU supports it or the target is in getRISCVTargetFeatures()
195 // unaligned-vector-mem is enabled if the CPU supports it or the target is in getRISCVABI()
300 // 2. Based on `-mcpu` if the target CPU ha in getRISCVArch()
278 StringRef CPU = A->getValue(); getRISCVArch() local
332 std::string CPU; getRISCVTargetCPU() local
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/VE/
H A DVESubtarget.cpp28 VESubtarget &VESubtarget::initializeSubtargetDependencies(StringRef CPU, in initializeSubtargetDependencies() argument
34 std::string CPUName = std::string(CPU); in initializeSubtargetDependencies()
39 ParseSubtargetFeatures(CPUName, /*TuneCPU=*/CPU, FS); in initializeSubtargetDependencies()
44 VESubtarget::VESubtarget(const Triple &TT, const std::string &CPU, in VESubtarget() argument
46 : VEGenSubtargetInfo(TT, CPU, /*TuneCPU=*/CPU, FS), TargetTriple(TT), in VESubtarget()
47 InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this), in VESubtarget()
/freebsd-src/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kSubtarget.cpp41 /// Select the M68k CPU for the given triple and cpu name.
42 static StringRef selectM68kCPU(Triple TT, StringRef CPU) { in selectM68kCPU() argument
43 if (CPU.empty() || CPU == "generic") { in selectM68kCPU()
44 CPU = "M68000"; in selectM68kCPU()
46 return CPU; in selectM68kCPU()
51 M68kSubtarget::M68kSubtarget(const Triple &TT, StringRef CPU, StringRef FS, in M68kSubtarget() argument
53 : M68kGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), TM(TM), TSInfo(), in M68kSubtarget()
54 InstrInfo(initializeSubtargetDependencies(CPU, T in M68kSubtarget()
88 initializeSubtargetDependencies(StringRef CPU,Triple TT,StringRef FS,const M68kTargetMachine & TM) initializeSubtargetDependencies() argument
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXSubtarget.cpp32 NVPTXSubtarget &NVPTXSubtarget::initializeSubtargetDependencies(StringRef CPU, in initializeSubtargetDependencies() argument
35 TargetName = std::string(CPU.empty() ? "sm_30" : CPU); in initializeSubtargetDependencies()
52 NVPTXSubtarget::NVPTXSubtarget(const Triple &TT, const std::string &CPU, in NVPTXSubtarget() argument
55 : NVPTXGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), PTXVersion(0), in NVPTXSubtarget()
57 TLInfo(TM, initializeSubtargetDependencies(CPU, FS)) {} in NVPTXSubtarget()
/freebsd-src/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZSubtarget.cpp32 StringRef CPU, StringRef TuneCPU, StringRef FS) { in initializeSubtargetDependencies() argument
33 if (CPU.empty()) in initializeSubtargetDependencies()
34 CPU = "generic"; in initializeSubtargetDependencies()
36 TuneCPU = CPU; in initializeSubtargetDependencies()
38 ParseSubtargetFeatures(CPU, TuneCPU, FS); in initializeSubtargetDependencies()
66 SystemZSubtarget::SystemZSubtarget(const Triple &TT, const std::string &CPU, in SystemZSubtarget() argument
70 : SystemZGenSubtargetInfo(TT, CPU, TuneCPU, FS), TargetTriple(TT), in SystemZSubtarget()
72 InstrInfo(initializeSubtargetDependencies(CPU, TuneCPU, FS)), in SystemZSubtarget()
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsTargetMachine.cpp73 static std::string computeDataLayout(const Triple &TT, StringRef CPU, in computeDataLayout() argument
77 MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions); in computeDataLayout()
122 StringRef CPU, StringRef FS, in MipsTargetMachine() argument
128 : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT, in MipsTargetMachine()
129 CPU, FS, Options, getEffectiveRelocModel(JIT, RM), in MipsTargetMachine()
132 ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)), in MipsTargetMachine()
134 DefaultSubtarget(TT, CPU, FS, isLittle, *this, std::nullopt), in MipsTargetMachine()
135 NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16", in MipsTargetMachine()
137 Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16", in MipsTargetMachine()
151 StringRef CPU, StringRe in MipsebTargetMachine() argument
161 MipselTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOptLevel OL,bool JIT) MipselTargetMachine() argument
173 std::string CPU = getSubtargetImpl() local
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/freebsd-src/sys/contrib/device-tree/src/arm64/marvell/
H A Dac5x-rd-carrier-cn9131.dts6 * Utilizing the CN913x COM Express CPU module board.
8 * only maintains a PCIe link with the CPU module,
13 * which would allow it to use an external CN9131 CPU COM Express module,
19 * When the board boots in the external CPU mode, the internal CPU is disabled,
21 * is no need to describe this internal (disabled CPU) in the device tree.
23 * There is no CPU booting in this mode on the carrier, only on the
24 * CN9131 COM Express CPU module.
25 * What runs the Linux is the CN9131 on the COM Express CPU module,
34 model = "Marvell Armada AC5X RD COM EXPRESS type 7 carrier board with CN9131 CPU module";
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcTargetMachine.cpp99 StringRef CPU, StringRef FS, in SparcTargetMachine() argument
105 : LLVMTargetMachine(T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options, in SparcTargetMachine()
122 std::string CPU = in getSubtargetImpl() local
125 TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU; in getSubtargetImpl()
137 auto &I = SubtargetMap[CPU + FS]; in getSubtargetImpl()
143 I = std::make_unique<SparcSubtarget>(CPU, TuneCPU, FS, *this, in getSubtargetImpl()
201 StringRef CPU, StringRef FS, in SparcV8TargetMachine() argument
206 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {} in SparcV8TargetMachine()
211 StringRef CPU, StringRef FS, in SparcV9TargetMachine() argument
216 : SparcTargetMachine(T, TT, CPU, F in SparcV9TargetMachine()
221 SparcelTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,std::optional<Reloc::Model> RM,std::optional<CodeModel::Model> CM,CodeGenOptLevel OL,bool JIT) SparcelTargetMachine() argument
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430Subtarget.cpp42 MSP430Subtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { in initializeSubtargetDependencies() argument
46 StringRef CPUName = CPU; in initializeSubtargetDependencies()
58 MSP430Subtarget::MSP430Subtarget(const Triple &TT, const std::string &CPU, in MSP430Subtarget() argument
60 : MSP430GenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), in MSP430Subtarget()
61 InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this), in MSP430Subtarget()

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