| /freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86LowerAMXType.cpp | 235 void combineLoadBitcast(LoadInst *LD, BitCastInst *Bitcast);
236 void combineBitcastStore(BitCastInst *Bitcast, StoreInst *ST);
237 bool transformBitcast(BitCastInst *Bitcast);
245 void X86LowerAMXType::combineLoadBitcast(LoadInst *LD, BitCastInst *Bitcast) { in combineLoadBitcast()
247 Use &U = *(Bitcast->use_begin()); in combineLoadBitcast()
251 IRBuilder<> Builder(Bitcast); in combineLoadBitcast()
259 Bitcast->replaceAllUsesWith(NewInst);
269 void X86LowerAMXType::combineBitcastStore(BitCastInst *Bitcast, StoreInst *ST) { in combineBitcastStore()
271 Value *Tile = Bitcast->getOperand(0); in combineBitcastStore()
285 if (Bitcast in combineBitcastStore()
238 combineLoadBitcast(LoadInst * LD,BitCastInst * Bitcast) combineLoadBitcast() argument
262 combineBitcastStore(BitCastInst * Bitcast,StoreInst * ST) combineBitcastStore() argument
294 transformBitcast(BitCastInst * Bitcast) transformBitcast() argument
359 auto *Bitcast = dyn_cast<BitCastInst>(&Inst); visit() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCInstrDesc.h | 164 Bitcast, enumerator
348 bool isBitcast() const { return Flags & (1ULL << MCID::Bitcast); } in isBitcast()
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUPreLegalizerCombiner.cpp | 199 auto Bitcast = B.buildBitcast({S32}, CvtPk); in applyClampI64ToI16()
203 {MinBoundaryDst.getReg(0), Bitcast.getReg(0), MaxBoundaryDst.getReg(0)}, in applyClampI64ToI16() local
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| H A D | AMDGPURegisterBankInfo.cpp | 1723 auto Bitcast = B.buildBitcast(S32, Src); in unpackV2S16ToS32()
1726 auto ExtLo = B.buildSExtInReg(S32, Bitcast, 16); in unpackV2S16ToS32()
1727 auto ShiftHi = B.buildAShr(S32, Bitcast, B.buildConstant(S32, 16)); in unpackV2S16ToS32()
1731 auto ShiftHi = B.buildLShr(S32, Bitcast, B.buildConstant(S32, 16)); in unpackV2S16ToS32()
1733 auto ExtLo = B.buildAnd(S32, Bitcast, B.buildConstant(S32, 0xffff)); in unpackV2S16ToS32()
1738 return std::pair(Bitcast.getReg(0), ShiftHi.getReg(0)); in unpackV2S16ToS32()
1724 auto Bitcast = B.buildBitcast(S32, Src); unpackV2S16ToS32() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerInfo.cpp | 54 case Bitcast: in operator <<()
55 OS << "Bitcast"; in operator <<()
178 case Bitcast: { in mutationIsSane()
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| H A D | LegacyLegalizerInfo.cpp | 45 case Bitcast: in operator <<()
260 case Bitcast: in findAction()
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsLegalizerInfo.cpp | 446 auto Bitcast = in legalizeCustom() local
453 MIRBuilder.buildFSub(Dst, Bitcast, TwoP52FP); in legalizeCustom()
455 MachineInstrBuilder ResF64 = MIRBuilder.buildFSub(s64, Bitcast, TwoP52FP); in legalizeCustom()
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| H A D | MipsISelLowering.cpp | 2402 // Bitcast to integer nodes. in lowerFCOPYSIGN64()
2500 // Bitcast to integer node. in lowerFABS()
5020 Register Bitcast = MRI.createVirtualRegister(&Mips::MSA128WRegClass); in emitSTR_D()
5023 BuildMI(*BB, I, DL, TII->get(Mips::COPY)).addDef(Bitcast).addUse(StoreVal); in emitSTR_D()
5026 .addUse(Bitcast) in emitSTR_D()
5030 .addUse(Bitcast) in emitSTR_D()
5005 Register Bitcast = MRI.createVirtualRegister(&Mips::MSA128WRegClass); emitSTR_D() local
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| /freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LegalizerInfo.h | 74 Bitcast, enumerator
173 case LegacyLegalizeActions::Bitcast: in LegalizeActionStep()
174 Action = LegalizeActions::Bitcast; in LegalizeActionStep()
661 return actionIf(LegalizeAction::Bitcast, Predicate, Mutation); in bitcastIf()
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| H A D | LegacyLegalizerInfo.h | 55 Bitcast, enumerator
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| /freebsd-src/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
| H A D | CodeExtractor.cpp | 549 Instruction *Bitcast = cast<Instruction>(U); in findAllocas() local
550 for (User *BU : Bitcast->users()) { in findAllocas()
562 << *Bitcast << " in out-of-region lifetime marker " in findAllocas()
582 Instruction *Bitcast = cast<Instruction>(U); in findAllocas() local
583 LifetimeMarkerInfo LMI = getLifetimeMarkers(CEAC, Bitcast, ExitBlock); in findAllocas()
585 Bitcasts.push_back(Bitcast); in findAllocas()
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| /freebsd-src/contrib/llvm-project/llvm/lib/Transforms/IPO/ |
| H A D | FunctionSpecialization.cpp | 484 if (auto *Bitcast = dyn_cast<BitCastInst>(User)) { in getPromotableAlloca() local
485 if (!Bitcast->hasOneUse() || *Bitcast->user_begin() != Call) in getPromotableAlloca()
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 1927 // Bitcast vector to appropriate type to ensure ISel pattern coverage
2485 SDValue Bitcast = N->getOperand(0);
2486 if (Bitcast.getOpcode() != ISD::BITCAST)
2490 SDValue CastOp = Bitcast.getOperand(0); in performVectorExtendToFPCombine()
2492 EVT DstType = Bitcast.getValueType(); in performVectorExtendToFPCombine()
2468 SDValue Bitcast = N->getOperand(0); performVECTOR_SHUFFLECombine() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCompares.cpp | 3261 auto *Bitcast = dyn_cast<BitCastInst>(Cmp.getOperand(0)); in foldICmpBitCast()
3262 if (!Bitcast) in foldICmpBitCast()
3267 Value *BCSrcOp = Bitcast->getOperand(0); in foldICmpBitCast()
3268 Type *SrcType = Bitcast->getSrcTy(); in foldICmpBitCast()
3269 Type *DstType = Bitcast->getType(); in foldICmpBitCast()
3306 if (match(Op1, m_APInt(C)) && Bitcast->hasOneUse()) { in foldICmpInstWithConstant()
3361 if (Cmp.isEquality() && C->isAllOnes() && Bitcast->hasOneUse()) { in foldICmpBinOpEqualityWithConstant()
3373 if (Cmp.isEquality() && C->isZero() && Bitcast->hasOneUse() && in foldICmpBinOpEqualityWithConstant()
3166 auto *Bitcast = dyn_cast<BitCastInst>(Cmp.getOperand(0)); foldICmpBitCast() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64LegalizerInfo.cpp | 1812 auto Bitcast = MIRBuilder.buildBitcast(NewTy, ValReg); in legalizeCTPOP()
1813 MIRBuilder.buildStore(Bitcast.getReg(0), MI.getOperand(1), MMO); in legalizeCTPOP()
1667 auto Bitcast = MIRBuilder.buildBitcast(NewTy, ValReg); legalizeLoadStore() local
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| /freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstr.h | 1037 return hasProperty(MCID::Bitcast, Type);
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| /freebsd-src/contrib/llvm-project/clang/include/clang/Basic/ |
| H A D | BuiltinsNVPTX.def | 587 // Bitcast
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrP10.td | 2409 (VINSDRX $vDi, InsertEltShift.Left3, Bitcast.DblToLong)>;
2456 (VINSDLX $vDi, InsertEltShift.Left3, Bitcast.DblToLong)>;
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| H A D | PPCISelLowering.cpp | 9385 // Bitcast the argument APInt to a double and convert it to a single precision in LowerBUILD_VECTOR()
16006 SDNode *Bitcast = *Trunc->use_begin(); in PerformDAGCombine()
16009 if (Bitcast->getOpcode() != ISD::BITCAST || in PerformDAGCombine()
16010 Bitcast->getValueType(0) != MVT::f32) in PerformDAGCombine()
16017 std::swap(Bitcast, Bitcast2); in PerformDAGCombine()
16019 // Bitcast has the second float (in memory-layout order) and Bitcast2 in PerformDAGCombine()
16051 DCI.CombineTo(Bitcast, FloatLoad2); in PerformDAGCombine()
18024 SDValue Bitcast = DCI.DAG.getBitcast(MVT::v2i64, Op0.getOperand(0)); in setAlignFlagsForFI()
18026 ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Bitcast, in setAlignFlagsForFI()
15793 SDNode *Bitcast = *Trunc->use_begin(); PerformDAGCombine() local
17812 SDValue Bitcast = DCI.DAG.getBitcast(MVT::v2i64, Op0.getOperand(0)); combineTRUNCATE() local
|
| H A D | PPCInstrVSX.td | 1815 def Bitcast {
3579 def : Pat<(i32 (bitconvert f32:$A)), Bitcast.FltToInt>;
3589 def : Pat<(i64 (bitconvert f64:$A)), Bitcast.DblToLong>;
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 2573 SDValue Bitcast = DAG.getNode(ISD::BITCAST, SL, MVT::i32, A); in LowerFROUND32()
2575 SDValue Sign = DAG.getNode(ISD::AND, SL, MVT::i32, Bitcast, in LowerFROUND32()
2560 SDValue Bitcast = DAG.getNode(ISD::BITCAST, SL, MVT::i32, A); LowerFROUND32() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstrVFP.td | 1202 // Bitcast i32 -> f32. NEON prefers to use VMOVDRR.
|
| H A D | ARMISelLowering.cpp | 6093 // Bitcast operand 1 to i32. in LowerFCOPYSIGN()
15486 // Bitcast an i64 load inserted into a vector to f64. in PerformInsertEltCombine()
16059 // stored value. Bitcast it to the aligned type. in TryCombineBaseUpdate()
16075 // value. Bitcast it to the expected result type.
16608 // Bitcast the original vector into a vector of store-size units in PerformTruncatingStoreCombine()
16859 // Bitcast an i64 store extracted from a vector to f64. in PerformSTORECombine()
18031 SDValue Bitcast = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, VQMOVN); in PerformMinMaxCombine()
18032 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Bitcast, in PerformMinMaxCombine()
18072 SDValue Bitcast = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, VQMOVN); in PerformCMOVToBFICombine()
18073 return DAG.getNode(ISD::AND, DL, VT, Bitcast, in PerformCMOVToBFICombine()
18008 SDValue Bitcast = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, VQMOVN); PerformMinMaxCombine() local
18049 SDValue Bitcast = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, VQMOVN); PerformMinMaxCombine() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 4579 // Bitcast the source vector from <m x n*2 x ty> -> <m x n x ty*2> in lowerBitreverseShuffle()
4818 // Bitcast the input vectors to integers in case they are FP in lowerVECTOR_SHUFFLE()
4874 // Bitcast from <vscale x n * ty*2> to <vscale x 2*n x ty> in lowerVECTOR_SHUFFLE()
5469 // Bitcast to integer and shift the exponent to the LSB. in lowerFMAXIMUM_FMINIMUM()
5471 SDValue Bitcast = DAG.getBitcast(IntVT, FloatVal); in lowerFMAXIMUM_FMINIMUM()
5477 Exp = DAG.getNode(ISD::VP_SRL, DL, IntVT, Bitcast, in lowerFMAXIMUM_FMINIMUM()
5481 Exp = DAG.getNode(ISD::SRL, DL, IntVT, Bitcast, in lowerFMAXIMUM_FMINIMUM()
8565 // Bitcast back to the right container type. in LowerINTRINSIC_WO_CHAIN()
8586 // Bitcast back to the right container type. in LowerINTRINSIC_WO_CHAIN()
12631 // scalar types in order to improve codegen. Bitcast th in combineDeMorganOfBoolean()
5184 SDValue Bitcast = DAG.getBitcast(IntVT, FloatVal); lowerCTLZ_CTTZ_ZERO_UNDEF() local
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | IntrinsicsNVVM.td | 1300 // Bitcast
|