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Searched refs:AddMI (Results 1 – 6 of 6) sorted by relevance

/freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCShuffler.cpp55 void HexagonMCShuffler::init(MCInst &MCB, MCInst const &AddMI, in init() argument
59 append(AddMI, nullptr, HexagonMCInstrInfo::getUnits(MCII, STI, AddMI)); in init()
72 append(AddMI, nullptr, HexagonMCInstrInfo::getUnits(MCII, STI, AddMI)); in init()
181 MCInst const &AddMI, int fixupCount) { in HexagonMCShuffle() argument
216 HexagonMCShuffler MCS(Context, false, MCII, STI, MCB, AddMI, false); in HexagonMCShuffle()
H A DHexagonMCShuffler.h40 MCInst &MCB, MCInst const &AddMI, bool InsertAtFront) in HexagonMCShuffler() argument
42 init(MCB, AddMI, InsertAtFront); in HexagonMCShuffler()
53 void init(MCInst &MCB, MCInst const &AddMI, bool InsertAtFront);
63 MCInst const &AddMI, int fixupCount);
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonOptAddrMode.cpp96 bool processAddUses(NodeAddr<StmtNode *> AddSN, MachineInstr *AddMI,
98 bool updateAddUses(MachineInstr *AddMI, MachineInstr *UseMI);
418 MachineInstr *AddMI, in processAddUses()
421 Register AddDefR = AddMI->getOperand(0).getReg(); in processAddUses()
422 Register BaseReg = AddMI->getOperand(1).getReg(); in processAddUses()
441 int64_t newOffset = OffsetOp.getImm() + AddMI->getOperand(2).getImm(); in processAddUses()
452 if (!isSafeToExtLR(AddSN, AddMI, BaseReg, UNodeList)) in processAddUses()
477 Changed |= updateAddUses(AddMI, UseMI); in processAddUses()
487 Deleted.insert(AddMI); in processAddUses()
492 bool HexagonOptAddrMode::updateAddUses(MachineInstr *AddMI, in updateAddUses()
416 processAddUses(NodeAddr<StmtNode * > AddSN,MachineInstr * AddMI,const NodeList & UNodeList) processAddUses() argument
490 updateAddUses(MachineInstr * AddMI,MachineInstr * UseMI) updateAddUses() argument
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CollectLOH.cpp398 const MachineInstr *AddMI = Info.MI0; in handleADRP() local
400 int OpIdx = mapRegToGPRIndex(AddMI->getOperand(0).getReg()); in handleADRP()
435 MachineInstr *AddMI = const_cast<MachineInstr *>(Info.MI1); in handleADRP() local
437 auto AddIt = MachineBasicBlock::iterator(AddMI); in handleADRP()
438 auto EndIt = AddMI->getParent()->end(); in handleADRP()
439 if (AddMI->getIterator() == EndIt || LdrMI != &*next_nodbg(AddIt, EndIt)) in handleADRP()
H A DAArch64InstrInfo.cpp6935 MachineInstr *AddMI = MRI.getUniqueVRegDef(Root.getOperand(2).getReg()); in genAlternativeCodeSequence()
6940 Register RegB = AddMI->getOperand(IdxOpd1).getReg(); in genAlternativeCodeSequence()
6941 bool RegBIsKill = AddMI->getOperand(IdxOpd1).isKill(); in genAlternativeCodeSequence()
6942 Register RegC = AddMI->getOperand(IdxOtherOpd).getReg(); in genAlternativeCodeSequence()
6943 bool RegCIsKill = AddMI->getOperand(IdxOtherOpd).isKill(); in genAlternativeCodeSequence()
6955 uint32_t Flags = Root.mergeFlagsWith(*AddMI); in genAlternativeCodeSequence()
6973 DelInstrs.push_back(AddMI); in genAlternativeCodeSequence()
6884 MachineInstr *AddMI = MRI.getUniqueVRegDef(Root.getOperand(2).getReg()); genSubAdd2SubSub() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DDelaySlotFiller.cpp377 MachineBasicBlock::iterator AddMI, in combineRestoreADD() argument
385 Register reg = AddMI->getOperand(0).getReg(); in combineRestoreADD()
393 AddMI->setDesc(TII->get((AddMI->getOpcode() == SP::ADDrr) in combineRestoreADD()
398 AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreADD()