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Searched refs:cycle (Results 1 – 17 of 17) sorted by relevance

/dpdk/app/test/
H A Dtest_member_perf.c74 unsigned int cycle; member
116 memcpy(temp_key, keys[i], hashtest_key_lens[params->cycle]); in shuffle_input_keys()
118 hashtest_key_lens[params->cycle]); in shuffle_input_keys()
120 hashtest_key_lens[params->cycle]); in shuffle_input_keys()
147 setup_keys_and_data(struct member_perf_params *params, unsigned int cycle, in setup_keys_and_data() argument
157 params->key_size = hashtest_key_lens[cycle]; in setup_keys_and_data()
158 params->cycle = cycle; in setup_keys_and_data()
313 cycles[type][params->cycle][ADD] = time_taken / KEYS_TO_ADD; in timed_adds()
345 cycles[type][params->cycle][ADD] = time_taken / NUM_ADDS; in timed_adds_sketch()
355 false_data[type][params->cycle] = 0; in timed_lookups()
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H A Dtest_efd_perf.c67 unsigned int cycle; member
104 memcpy(temp_key, keys[i], hashtest_key_lens[params->cycle]); in shuffle_input_keys()
107 memcpy(keys[i], keys[swap_idx], hashtest_key_lens[params->cycle]); in shuffle_input_keys()
110 memcpy(keys[swap_idx], temp_key, hashtest_key_lens[params->cycle]); in shuffle_input_keys()
128 setup_keys_and_data(struct efd_perf_params *params, unsigned int cycle) in setup_keys_and_data() argument
133 params->key_size = hashtest_key_lens[cycle]; in setup_keys_and_data()
134 params->cycle = cycle; in setup_keys_and_data()
200 cycles[params->cycle][ADD] = time_taken / KEYS_TO_ADD; in timed_adds()
233 cycles[params->cycle][LOOKUP] = time_taken / NUM_LOOKUPS; in timed_lookups()
277 cycles[params->cycle][LOOKUP_MULTI] = time_taken / NUM_LOOKUPS; in timed_lookups_multi()
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/dpdk/doc/guides/prog_guide/
H A Dprofile_app.rst74 High-resolution cycle counter
78 clock counter is through the ARMv8 PMU subsystem. The PMU cycle counter runs
79 at CPU frequency. However, access to the PMU cycle counter from user space is
81 cycle counter for user space access by configuring the PMU from the privileged
87 The example below shows the steps to configure the PMU based cycle counter on
H A Dservice_cores.rst53 cycle count collection is dynamically configurable, allowing any application to
H A Dtrace_lib.rst38 Typical trace overhead is ~20 cycles and instrumentation overhead is 1 cycle.
/dpdk/doc/guides/contributing/
H A Dstable.rst41 The duration of a stable is one complete release cycle (4 months). It can be
44 for one release cycle.
H A Dabi_policy.rst295 is then dropped for the duration of this release cycle.
297 and some amended rules apply during this cycle:
H A Dabi_versioning.rst123 at the start of each release cycle, and are managed at the project level.
/dpdk/doc/guides/tools/
H A Dtestbbdev.rst113 (a) *SW Enq Offload Cost*: Software only enqueue offload cost, the cycle
116 (b) *Acc Enq Offload Cost*: The cycle count and time (us) from the
119 (c) *SW Deq Offload Cost*: Software dequeue cost, the cycle counts and
121 (d) *Empty Queue Enq Offload Cost*: The cycle count and time (us)
H A Dcomp_perf.rst26 the trade-off between throughput and cycle-count.
/dpdk/doc/guides/rel_notes/
H A Drelease_18_08.rst40 * Add low cycle count Tx handler for no-offload Tx.
41 * Add low cycle count Rx handler for non-scattered Rx.
H A Drelease_20_02.rst197 * **Added cycle-count mode to the compression performance tool.**
199 Enhanced the compression performance tool by adding a cycle-count mode
H A Drelease_20_05.rst18 instrumentation overhead is 1 cycle. Added tracepoints in ``EAL``,
H A Drelease_16_04.rst270 * Added CPU utilization measurement and idle cycle rate computation.
H A Dknown_issues.rst101 but specific to an lcore and is a cycle reference, not a time reference.
H A Drelease_2_1.rst521 * **eal/ppc: Fix cpu cycle count for little endian.**
/dpdk/doc/guides/vdpadevs/
H A Dmlx5.rst83 A nonzero value defines the traffic off time, in polling cycle time units,