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Searched refs:mmDP0_DP_DPHY_CNTL (Results 1 – 7 of 7) sorted by relevance

/dflybsd-src/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h3117 #define mmDP0_DP_DPHY_CNTL 0x1CD0 macro
H A Ddce_8_0_d.h3868 #define mmDP0_DP_DPHY_CNTL 0x1cd0 macro
H A Ddce_11_0_d.h4478 #define mmDP0_DP_DPHY_CNTL 0x4aaf macro
H A Ddce_10_0_d.h4500 #define mmDP0_DP_DPHY_CNTL 0x4aaf macro
H A Ddce_11_2_d.h5710 #define mmDP0_DP_DPHY_CNTL 0x4aaf macro
H A Ddce_12_0_offset.h10226 #define mmDP0_DP_DPHY_CNTL … macro
/dflybsd-src/sys/dev/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_offset.h8369 #define mmDP0_DP_DPHY_CNTL … macro