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Searched refs:amdgpu_ring_write (Results 1 – 16 of 16) sorted by relevance

/dflybsd-src/sys/dev/drm/amd/amdgpu/
H A Dvcn_v1_0.c923 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_insert_start()
925 amdgpu_ring_write(ring, 0); in vcn_v1_0_dec_ring_insert_start()
926 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_insert_start()
928 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1); in vcn_v1_0_dec_ring_insert_start()
942 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_insert_end()
944 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1); in vcn_v1_0_dec_ring_insert_end()
962 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_emit_fence()
964 amdgpu_ring_write(ring, seq); in vcn_v1_0_dec_ring_emit_fence()
965 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_emit_fence()
967 amdgpu_ring_write(ring, addr & 0xffffffff); in vcn_v1_0_dec_ring_emit_fence()
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H A Duvd_v6_0.c186 amdgpu_ring_write(ring, HEVC_ENC_CMD_END); in uvd_v6_0_enc_ring_test_ring()
500 amdgpu_ring_write(ring, tmp); in uvd_v6_0_hw_init()
501 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v6_0_hw_init()
504 amdgpu_ring_write(ring, tmp); in uvd_v6_0_hw_init()
505 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v6_0_hw_init()
508 amdgpu_ring_write(ring, tmp); in uvd_v6_0_hw_init()
509 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v6_0_hw_init()
512 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v6_0_hw_init()
513 amdgpu_ring_write(ring, 0x8); in uvd_v6_0_hw_init()
515 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v6_0_hw_init()
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H A Duvd_v5_0.c175 amdgpu_ring_write(ring, tmp); in uvd_v5_0_hw_init()
176 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v5_0_hw_init()
179 amdgpu_ring_write(ring, tmp); in uvd_v5_0_hw_init()
180 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v5_0_hw_init()
183 amdgpu_ring_write(ring, tmp); in uvd_v5_0_hw_init()
184 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v5_0_hw_init()
187 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v5_0_hw_init()
188 amdgpu_ring_write(ring, 0x8); in uvd_v5_0_hw_init()
190 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v5_0_hw_init()
191 amdgpu_ring_write(ring, 3); in uvd_v5_0_hw_init()
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H A Duvd_v7_0.c194 amdgpu_ring_write(ring, HEVC_ENC_CMD_END); in uvd_v7_0_enc_ring_test_ring()
560 amdgpu_ring_write(ring, tmp); in uvd_v7_0_hw_init()
561 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v7_0_hw_init()
565 amdgpu_ring_write(ring, tmp); in uvd_v7_0_hw_init()
566 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v7_0_hw_init()
570 amdgpu_ring_write(ring, tmp); in uvd_v7_0_hw_init()
571 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v7_0_hw_init()
574 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init()
576 amdgpu_ring_write(ring, 0x8); in uvd_v7_0_hw_init()
578 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init()
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H A Dsdma_v2_4.c233 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v2_4_ring_insert_nop()
236 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v2_4_ring_insert_nop()
254 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v2_4_ring_emit_ib()
257 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v2_4_ring_emit_ib()
258 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v2_4_ring_emit_ib()
259 amdgpu_ring_write(ring, ib->length_dw); in sdma_v2_4_ring_emit_ib()
260 amdgpu_ring_write(ring, 0); in sdma_v2_4_ring_emit_ib()
261 amdgpu_ring_write(ring, 0); in sdma_v2_4_ring_emit_ib()
281 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | in sdma_v2_4_ring_emit_hdp_flush()
284 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); in sdma_v2_4_ring_emit_hdp_flush()
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H A Dsdma_v3_0.c408 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v3_0_ring_insert_nop()
411 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v3_0_ring_insert_nop()
429 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v3_0_ring_emit_ib()
432 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v3_0_ring_emit_ib()
433 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v3_0_ring_emit_ib()
434 amdgpu_ring_write(ring, ib->length_dw); in sdma_v3_0_ring_emit_ib()
435 amdgpu_ring_write(ring, 0); in sdma_v3_0_ring_emit_ib()
436 amdgpu_ring_write(ring, 0); in sdma_v3_0_ring_emit_ib()
456 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | in sdma_v3_0_ring_emit_hdp_flush()
459 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); in sdma_v3_0_ring_emit_hdp_flush()
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H A Dgfx_v9_0.c308 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v9_0_write_data_to_reg()
309 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | in gfx_v9_0_write_data_to_reg()
312 amdgpu_ring_write(ring, reg); in gfx_v9_0_write_data_to_reg()
313 amdgpu_ring_write(ring, 0); in gfx_v9_0_write_data_to_reg()
314 amdgpu_ring_write(ring, val); in gfx_v9_0_write_data_to_reg()
322 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v9_0_wait_reg_mem()
323 amdgpu_ring_write(ring, in gfx_v9_0_wait_reg_mem()
332 amdgpu_ring_write(ring, addr0); in gfx_v9_0_wait_reg_mem()
333 amdgpu_ring_write(ring, addr1); in gfx_v9_0_wait_reg_mem()
334 amdgpu_ring_write(ring, ref); in gfx_v9_0_wait_reg_mem()
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H A Dgfx_v8_0.c854 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v8_0_ring_test_ring()
855 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); in gfx_v8_0_ring_test_ring()
856 amdgpu_ring_write(ring, 0xDEADBEEF); in gfx_v8_0_ring_test_ring()
4394 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v8_0_cp_gfx_start()
4395 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v8_0_cp_gfx_start()
4397 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); in gfx_v8_0_cp_gfx_start()
4398 amdgpu_ring_write(ring, 0x80000000); in gfx_v8_0_cp_gfx_start()
4399 amdgpu_ring_write(ring, 0x80000000); in gfx_v8_0_cp_gfx_start()
4404 amdgpu_ring_write(ring, in gfx_v8_0_cp_gfx_start()
4407 amdgpu_ring_write(ring, in gfx_v8_0_cp_gfx_start()
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H A Dsdma_v4_0.c367 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v4_0_ring_insert_nop()
370 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v4_0_ring_insert_nop()
388 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v4_0_ring_emit_ib()
391 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v4_0_ring_emit_ib()
392 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v4_0_ring_emit_ib()
393 amdgpu_ring_write(ring, ib->length_dw); in sdma_v4_0_ring_emit_ib()
394 amdgpu_ring_write(ring, 0); in sdma_v4_0_ring_emit_ib()
395 amdgpu_ring_write(ring, 0); in sdma_v4_0_ring_emit_ib()
405 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | in sdma_v4_0_wait_reg_mem()
411 amdgpu_ring_write(ring, addr0); in sdma_v4_0_wait_reg_mem()
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H A Dvce_v3_0.c843 amdgpu_ring_write(ring, VCE_CMD_IB_VM); in vce_v3_0_ring_emit_ib()
844 amdgpu_ring_write(ring, vmid); in vce_v3_0_ring_emit_ib()
845 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in vce_v3_0_ring_emit_ib()
846 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in vce_v3_0_ring_emit_ib()
847 amdgpu_ring_write(ring, ib->length_dw); in vce_v3_0_ring_emit_ib()
853 amdgpu_ring_write(ring, VCE_CMD_UPDATE_PTB); in vce_v3_0_emit_vm_flush()
854 amdgpu_ring_write(ring, vmid); in vce_v3_0_emit_vm_flush()
855 amdgpu_ring_write(ring, pd_addr >> 12); in vce_v3_0_emit_vm_flush()
857 amdgpu_ring_write(ring, VCE_CMD_FLUSH_TLB); in vce_v3_0_emit_vm_flush()
858 amdgpu_ring_write(ring, vmid); in vce_v3_0_emit_vm_flush()
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H A Dvce_v4_0.c952 amdgpu_ring_write(ring, VCE_CMD_IB_VM); in vce_v4_0_ring_emit_ib()
953 amdgpu_ring_write(ring, vmid); in vce_v4_0_ring_emit_ib()
954 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in vce_v4_0_ring_emit_ib()
955 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in vce_v4_0_ring_emit_ib()
956 amdgpu_ring_write(ring, ib->length_dw); in vce_v4_0_ring_emit_ib()
964 amdgpu_ring_write(ring, VCE_CMD_FENCE); in vce_v4_0_ring_emit_fence()
965 amdgpu_ring_write(ring, addr); in vce_v4_0_ring_emit_fence()
966 amdgpu_ring_write(ring, upper_32_bits(addr)); in vce_v4_0_ring_emit_fence()
967 amdgpu_ring_write(ring, seq); in vce_v4_0_ring_emit_fence()
968 amdgpu_ring_write(ring, VCE_CMD_TRAP); in vce_v4_0_ring_emit_fence()
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H A Damdgpu_vce.c1038 amdgpu_ring_write(ring, VCE_CMD_IB); in amdgpu_vce_ring_emit_ib()
1039 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in amdgpu_vce_ring_emit_ib()
1040 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in amdgpu_vce_ring_emit_ib()
1041 amdgpu_ring_write(ring, ib->length_dw); in amdgpu_vce_ring_emit_ib()
1056 amdgpu_ring_write(ring, VCE_CMD_FENCE); in amdgpu_vce_ring_emit_fence()
1057 amdgpu_ring_write(ring, addr); in amdgpu_vce_ring_emit_fence()
1058 amdgpu_ring_write(ring, upper_32_bits(addr)); in amdgpu_vce_ring_emit_fence()
1059 amdgpu_ring_write(ring, seq); in amdgpu_vce_ring_emit_fence()
1060 amdgpu_ring_write(ring, VCE_CMD_TRAP); in amdgpu_vce_ring_emit_fence()
1061 amdgpu_ring_write(ring, VCE_CMD_END); in amdgpu_vce_ring_emit_fence()
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H A Damdgpu_vcn.c263 amdgpu_ring_write(ring, in amdgpu_vcn_dec_ring_test_ring()
265 amdgpu_ring_write(ring, 0xDEADBEEF); in amdgpu_vcn_dec_ring_test_ring()
447 amdgpu_ring_write(ring, VCN_ENC_CMD_END); in amdgpu_vcn_enc_ring_test_ring()
620 amdgpu_ring_write(ring, in amdgpu_vcn_jpeg_ring_test_ring()
622 amdgpu_ring_write(ring, 0xDEADBEEF); in amdgpu_vcn_jpeg_ring_test_ring()
H A Damdgpu_ring.h253 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) in amdgpu_ring_write() function
H A Damdgpu_ring.c97 amdgpu_ring_write(ring, ring->funcs->nop); in amdgpu_ring_insert_nop()
H A Damdgpu_amdkfd_gfx_v9.c849 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); in invalidate_tlbs_with_kiq()
850 amdgpu_ring_write(ring, in invalidate_tlbs_with_kiq()