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Searched refs:UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK (Results 1 – 6 of 6) sorted by relevance

/dflybsd-src/sys/dev/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h199 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK … macro
H A Duvd_4_0_sh_mask.h740 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L macro
H A Duvd_4_2_sh_mask.h97 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 macro
H A Duvd_6_0_sh_mask.h97 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 macro
H A Duvd_5_0_sh_mask.h97 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 macro
/dflybsd-src/sys/dev/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h396 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK … macro