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Searched refs:UVD_CGC_GATE__MPRD_MASK (Results 1 – 10 of 10) sorted by relevance

/dflybsd-src/sys/dev/drm/amd/amdgpu/
H A Duvd_v6_0.c643 UVD_CGC_GATE__MPRD_MASK |
676 UVD_CGC_GATE__MPRD_MASK |
1292 UVD_CGC_GATE__MPRD_MASK | in uvd_v6_0_enable_clock_gating()
1380 UVD_CGC_GATE__MPRD_MASK |
H A Duvd_v5_0.c631 UVD_CGC_GATE__MPRD_MASK | in uvd_v5_0_enable_clock_gating()
718 UVD_CGC_GATE__MPRD_MASK |
H A Dvcn_v1_0.c371 | UVD_CGC_GATE__MPRD_MASK in vcn_v1_0_disable_clock_gating()
H A Duvd_v7_0.c1652 UVD_CGC_GATE__MPRD_MASK |
/dflybsd-src/sys/dev/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h405 #define UVD_CGC_GATE__MPRD_MASK macro
H A Duvd_4_0_sh_mask.h92 #define UVD_CGC_GATE__MPRD_MASK 0x00000100L macro
H A Duvd_4_2_sh_mask.h139 #define UVD_CGC_GATE__MPRD_MASK 0x100 macro
H A Duvd_6_0_sh_mask.h153 #define UVD_CGC_GATE__MPRD_MASK 0x100 macro
H A Duvd_5_0_sh_mask.h151 #define UVD_CGC_GATE__MPRD_MASK 0x100 macro
/dflybsd-src/sys/dev/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h808 #define UVD_CGC_GATE__MPRD_MASK macro