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Searched refs:SDMA1_STATUS1_REG__CE_WR_IDLE_MASK (Results 1 – 5 of 5) sorted by relevance

/dflybsd-src/sys/dev/drm/amd/include/asic_reg/sdma1/
H A Dsdma1_4_0_sh_mask.h553 #define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L macro
/dflybsd-src/sys/dev/drm/amd/include/asic_reg/oss/
H A Doss_2_0_sh_mask.h1483 #define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x2 macro
H A Doss_2_4_sh_mask.h1647 #define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x2 macro
H A Doss_3_0_1_sh_mask.h2165 #define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x2 macro
H A Doss_3_0_sh_mask.h2469 #define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x2 macro