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Searched refs:RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK (Results 1 – 9 of 9) sorted by relevance

/dflybsd-src/sys/dev/drm/amd/amdgpu/
H A Dgfx_v9_0.c3574 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; in gfx_v9_0_update_medium_grain_clock_gating()
3603 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { in gfx_v9_0_update_medium_grain_clock_gating()
3604 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; in gfx_v9_0_update_medium_grain_clock_gating()
3832 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) in gfx_v9_0_get_clockgating_state()
H A Dgfx_v8_0.c5764 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) in gfx_v8_0_get_clockgating_state()
5955 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { in gfx_v8_0_update_medium_grain_clock_gating()
5956 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; in gfx_v8_0_update_medium_grain_clock_gating()
/dflybsd-src/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h7200 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x00000001L macro
H A Dgfx_7_2_sh_mask.h7729 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x1 macro
H A Dgfx_8_0_sh_mask.h8543 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x1 macro
H A Dgfx_8_1_sh_mask.h9095 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x1 macro
/dflybsd-src/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h22647 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK … macro
H A Dgc_9_1_sh_mask.h24063 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK … macro
H A Dgc_9_2_1_sh_mask.h24066 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK … macro