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Searched refs:PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE_MASK (Results 1 – 5 of 5) sorted by relevance

/dflybsd-src/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h8173 #define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE_MASK 0x20000000L macro
H A Ddce_8_0_sh_mask.h37 #define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE_MASK 0x20000000 macro
H A Ddce_11_0_sh_mask.h37 #define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE_MASK 0x20000000 macro
H A Ddce_10_0_sh_mask.h37 #define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE_MASK 0x20000000 macro
H A Ddce_11_2_sh_mask.h37 #define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE_MASK 0x20000000 macro