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Searched refs:PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT (Results 1 – 5 of 5) sorted by relevance

/dflybsd-src/sys/dev/drm/amd/include/asic_reg/bif/
H A Dbif_3_0_sh_mask.h7337 #define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x00000008 macro
H A Dbif_4_1_sh_mask.h3214 #define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 macro
H A Dbif_5_0_sh_mask.h10958 #define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 macro
H A Dbif_5_1_sh_mask.h4170 #define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 macro
/dflybsd-src/sys/dev/drm/amd/include/asic_reg/nbio/
H A Dnbio_6_1_sh_mask.h37962 #define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT … macro