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Searched refs:PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_EN__SHIFT (Results 1 – 3 of 3) sorted by relevance

/dflybsd-src/sys/dev/drm/amd/include/asic_reg/bif/
H A Dbif_3_0_sh_mask.h641 #define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_EN__SHIFT 0x00000000 macro
H A Dbif_4_1_sh_mask.h3730 #define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_EN__SHIFT 0x0 macro
H A Dbif_5_0_sh_mask.h4180 #define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_EN__SHIFT 0x0 macro