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Searched refs:PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK (Results 1 – 7 of 7) sorted by relevance

/dflybsd-src/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h6374 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x00000400L macro
H A Dgfx_7_2_sh_mask.h6565 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x400 macro
H A Dgfx_8_0_sh_mask.h7353 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x400 macro
H A Dgfx_8_1_sh_mask.h7889 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x400 macro
/dflybsd-src/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h1879 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK … macro
H A Dgc_9_1_sh_mask.h1836 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK … macro
H A Dgc_9_2_1_sh_mask.h1833 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK … macro