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Searched refs:DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT (Results 1 – 2 of 2) sorted by relevance

/dflybsd-src/sys/dev/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_sh_mask.h37891 #define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT … macro
/dflybsd-src/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_sh_mask.h43672 #define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT … macro