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Searched refs:CP_ROQ1_THRESHOLDS__RB2_START__SHIFT (Results 1 – 7 of 7) sorted by relevance

/dflybsd-src/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2875 #define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x00000008 macro
H A Dgfx_7_2_sh_mask.h3128 #define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8 macro
H A Dgfx_8_0_sh_mask.h3742 #define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8 macro
H A Dgfx_8_1_sh_mask.h4264 #define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8 macro
/dflybsd-src/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h1124 #define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT … macro
H A Dgc_9_1_sh_mask.h1122 #define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h1089 #define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT … macro