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Searched refs:BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__SHIFT (Results 1 – 3 of 3) sorted by relevance

/dflybsd-src/sys/dev/drm/amd/include/asic_reg/nbif/
H A Dnbif_6_1_sh_mask.h4059 #define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__SHIFT … macro
/dflybsd-src/sys/dev/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_0_sh_mask.h37651 #define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__SHIFT … macro
H A Dnbio_6_1_sh_mask.h22884 #define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__SHIFT … macro