1;; Copyright (C) 2012-2022 Free Software Foundation, Inc. 2;; 3;; This file is part of GCC. 4;; 5;; GCC is free software; you can redistribute it and/or modify 6;; it under the terms of the GNU General Public License as published by 7;; the Free Software Foundation; either version 3, or (at your option) 8;; any later version. 9;; 10;; GCC is distributed in the hope that it will be useful, 11;; but WITHOUT ANY WARRANTY; without even the implied warranty of 12;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13;; GNU General Public License for more details. 14;; 15;; You should have received a copy of the GNU General Public License 16;; along with GCC; see the file COPYING3. If not see 17;; <http://www.gnu.org/licenses/>. 18;; 19 20 21(define_attr "znver4_decode" "direct,vector,double" 22 (const_string "direct")) 23 24;; AMD znver4 Scheduling 25;; Modeling automatons for zen decoders, integer execution pipes, 26;; AGU pipes, branch, floating point execution and fp store units. 27(define_automaton "znver4, znver4_ieu, znver4_idiv, znver4_fdiv, znver4_agu, znver4_fpu, znver4_fp_store") 28 29;; Decoders unit has 4 decoders and all of them can decode fast path 30;; and vector type instructions. 31(define_cpu_unit "znver4-decode0" "znver4") 32(define_cpu_unit "znver4-decode1" "znver4") 33(define_cpu_unit "znver4-decode2" "znver4") 34(define_cpu_unit "znver4-decode3" "znver4") 35 36;; Currently blocking all decoders for vector path instructions as 37;; they are dispatched separetely as microcode sequence. 38(define_reservation "znver4-vector" "znver4-decode0+znver4-decode1+znver4-decode2+znver4-decode3") 39 40;; Direct instructions can be issued to any of the four decoders. 41(define_reservation "znver4-direct" "znver4-decode0|znver4-decode1|znver4-decode2|znver4-decode3") 42 43;; Fix me: Need to revisit this later to simulate fast path double behavior. 44(define_reservation "znver4-double" "znver4-direct") 45 46 47;; Integer unit 4 ALU pipes. 48(define_cpu_unit "znver4-ieu0" "znver4_ieu") 49(define_cpu_unit "znver4-ieu1" "znver4_ieu") 50(define_cpu_unit "znver4-ieu2" "znver4_ieu") 51(define_cpu_unit "znver4-ieu3" "znver4_ieu") 52;; Znver4 has an additional branch unit. 53(define_cpu_unit "znver4-bru0" "znver4_ieu") 54(define_reservation "znver4-ieu" "znver4-ieu0|znver4-ieu1|znver4-ieu2|znver4-ieu3") 55 56;; 3 AGU pipes in znver4 57(define_cpu_unit "znver4-agu0" "znver4_agu") 58(define_cpu_unit "znver4-agu1" "znver4_agu") 59(define_cpu_unit "znver4-agu2" "znver4_agu") 60(define_reservation "znver4-agu-reserve" "znver4-agu0|znver4-agu1|znver4-agu2") 61 62;; Load is 4 cycles. We do not model reservation of load unit. 63(define_reservation "znver4-load" "znver4-agu-reserve") 64(define_reservation "znver4-store" "znver4-agu-reserve") 65 66;; vectorpath (microcoded) instructions are single issue instructions. 67;; So, they occupy all the integer units. 68(define_reservation "znver4-ivector" "znver4-ieu0+znver4-ieu1 69 +znver4-ieu2+znver4-ieu3+znver4-bru0 70 +znver4-agu0+znver4-agu1+znver4-agu2") 71 72;; Floating point unit 4 FP pipes. 73(define_cpu_unit "znver4-fpu0" "znver4_fpu") 74(define_cpu_unit "znver4-fpu1" "znver4_fpu") 75(define_cpu_unit "znver4-fpu2" "znver4_fpu") 76(define_cpu_unit "znver4-fpu3" "znver4_fpu") 77 78(define_reservation "znver4-fpu" "znver4-fpu0|znver4-fpu1|znver4-fpu2|znver4-fpu3") 79 80(define_reservation "znver4-fvector" "znver4-fpu0+znver4-fpu1 81 +znver4-fpu2+znver4-fpu3 82 +znver4-agu0+znver4-agu1+znver4-agu2") 83 84;; DIV units 85(define_cpu_unit "znver4-idiv" "znver4_idiv") 86(define_cpu_unit "znver4-fdiv" "znver4_fdiv") 87 88;; Separate fp store and fp-to-int store. Although there are 2 store pipes, the 89;; throughput is limited to only one per cycle. 90(define_cpu_unit "znver4-fp-store" "znver4_fp_store") 91 92 93;; Integer Instructions 94;; Move instructions 95;; XCHG 96(define_insn_reservation "znver4_imov_double" 1 97 (and (eq_attr "cpu" "znver4") 98 (and (eq_attr "znver1_decode" "double") 99 (and (eq_attr "type" "imov") 100 (eq_attr "memory" "none")))) 101 "znver4-double,znver4-ieu") 102 103(define_insn_reservation "znver4_imov_double_load" 5 104 (and (eq_attr "cpu" "znver4") 105 (and (eq_attr "znver1_decode" "double") 106 (and (eq_attr "type" "imov") 107 (eq_attr "memory" "load")))) 108 "znver4-double,znver4-load,znver4-ieu") 109 110;; imov, imovx 111(define_insn_reservation "znver4_imov" 1 112 (and (eq_attr "cpu" "znver4") 113 (and (eq_attr "type" "imov,imovx") 114 (eq_attr "memory" "none"))) 115 "znver4-direct,znver4-ieu") 116 117(define_insn_reservation "znver4_imov_load" 5 118 (and (eq_attr "cpu" "znver4") 119 (and (eq_attr "type" "imov,imovx") 120 (eq_attr "memory" "load"))) 121 "znver4-direct,znver4-load,znver4-ieu") 122 123;; Push Instruction 124(define_insn_reservation "znver4_push" 1 125 (and (eq_attr "cpu" "znver4") 126 (and (eq_attr "type" "push") 127 (eq_attr "memory" "store"))) 128 "znver4-direct,znver4-store") 129 130(define_insn_reservation "znver4_push_mem" 5 131 (and (eq_attr "cpu" "znver4") 132 (and (eq_attr "type" "push") 133 (eq_attr "memory" "both"))) 134 "znver4-direct,znver4-load,znver4-store") 135 136;; Pop instruction 137(define_insn_reservation "znver4_pop" 4 138 (and (eq_attr "cpu" "znver4") 139 (and (eq_attr "type" "pop") 140 (eq_attr "memory" "load"))) 141 "znver4-direct,znver4-load") 142 143(define_insn_reservation "znver4_pop_mem" 5 144 (and (eq_attr "cpu" "znver4") 145 (and (eq_attr "type" "pop") 146 (eq_attr "memory" "both"))) 147 "znver4-direct,znver4-load,znver4-store") 148 149;; Integer Instructions or General instructions 150;; Multiplications 151(define_insn_reservation "znver4_imul" 3 152 (and (eq_attr "cpu" "znver4") 153 (and (eq_attr "type" "imul") 154 (eq_attr "memory" "none"))) 155 "znver4-direct,znver4-ieu1") 156 157(define_insn_reservation "znver4_imul_load" 7 158 (and (eq_attr "cpu" "znver4") 159 (and (eq_attr "type" "imul") 160 (eq_attr "memory" "load"))) 161 "znver4-direct,znver4-load,znver4-ieu1") 162 163;; Divisions 164(define_insn_reservation "znver4_idiv_DI" 18 165 (and (eq_attr "cpu" "znver4") 166 (and (eq_attr "type" "idiv") 167 (and (eq_attr "mode" "DI") 168 (eq_attr "memory" "none")))) 169 "znver4-double,znver4-idiv*10") 170 171(define_insn_reservation "znver4_idiv_SI" 12 172 (and (eq_attr "cpu" "znver4") 173 (and (eq_attr "type" "idiv") 174 (and (eq_attr "mode" "SI") 175 (eq_attr "memory" "none")))) 176 "znver4-double,znver4-idiv*6") 177 178(define_insn_reservation "znver4_idiv_HI" 10 179 (and (eq_attr "cpu" "znver4") 180 (and (eq_attr "type" "idiv") 181 (and (eq_attr "mode" "HI") 182 (eq_attr "memory" "none")))) 183 "znver4-double,znver4-idiv*4") 184 185(define_insn_reservation "znver4_idiv_QI" 9 186 (and (eq_attr "cpu" "znver4") 187 (and (eq_attr "type" "idiv") 188 (and (eq_attr "mode" "QI") 189 (eq_attr "memory" "none")))) 190 "znver4-double,znver4-idiv*4") 191 192(define_insn_reservation "znver4_idiv_DI_load" 22 193 (and (eq_attr "cpu" "znver4") 194 (and (eq_attr "type" "idiv") 195 (and (eq_attr "mode" "DI") 196 (eq_attr "memory" "load")))) 197 "znver4-double,znver4-load,znver4-idiv*10") 198 199(define_insn_reservation "znver4_idiv_SI_load" 16 200 (and (eq_attr "cpu" "znver4") 201 (and (eq_attr "type" "idiv") 202 (and (eq_attr "mode" "SI") 203 (eq_attr "memory" "load")))) 204 "znver4-double,znver4-load,znver4-idiv*6") 205 206(define_insn_reservation "znver4_idiv_HI_load" 14 207 (and (eq_attr "cpu" "znver4") 208 (and (eq_attr "type" "idiv") 209 (and (eq_attr "mode" "HI") 210 (eq_attr "memory" "load")))) 211 "znver4-double,znver4-load,znver4-idiv*4") 212 213(define_insn_reservation "znver4_idiv_QI_load" 13 214 (and (eq_attr "cpu" "znver4") 215 (and (eq_attr "type" "idiv") 216 (and (eq_attr "mode" "QI") 217 (eq_attr "memory" "load")))) 218 "znver4-double,znver4-load,znver4-idiv*4") 219 220;; INTEGER/GENERAL Instructions 221(define_insn_reservation "znver4_insn" 1 222 (and (eq_attr "cpu" "znver4") 223 (and (eq_attr "type" "alu,alu1,negnot,rotate1,ishift1,test,incdec,icmp") 224 (eq_attr "memory" "none,unknown"))) 225 "znver4-direct,znver4-ieu") 226 227(define_insn_reservation "znver4_insn_load" 5 228 (and (eq_attr "cpu" "znver4") 229 (and (eq_attr "type" "alu,alu1,negnot,rotate1,ishift1,test,incdec,icmp") 230 (eq_attr "memory" "load"))) 231 "znver4-direct,znver4-load,znver4-ieu") 232 233(define_insn_reservation "znver4_insn2" 1 234 (and (eq_attr "cpu" "znver4") 235 (and (eq_attr "type" "icmov,setcc") 236 (eq_attr "memory" "none,unknown"))) 237 "znver4-direct,znver4-ieu0|znver4-ieu3") 238 239(define_insn_reservation "znver4_insn2_load" 5 240 (and (eq_attr "cpu" "znver4") 241 (and (eq_attr "type" "icmov,setcc") 242 (eq_attr "memory" "load"))) 243 "znver4-direct,znver4-load,znver4-ieu0|znver4-ieu3") 244 245(define_insn_reservation "znver4_rotate" 1 246 (and (eq_attr "cpu" "znver4") 247 (and (eq_attr "type" "rotate") 248 (eq_attr "memory" "none,unknown"))) 249 "znver4-direct,znver4-ieu1|znver4-ieu2") 250 251(define_insn_reservation "znver4_rotate_load" 5 252 (and (eq_attr "cpu" "znver4") 253 (and (eq_attr "type" "rotate") 254 (eq_attr "memory" "load"))) 255 "znver4-direct,znver4-load,znver4-ieu1|znver4-ieu2") 256 257(define_insn_reservation "znver4_insn_store" 1 258 (and (eq_attr "cpu" "znver4") 259 (and (eq_attr "type" "alu,alu1,negnot,rotate1,ishift1,test,incdec,icmp") 260 (eq_attr "memory" "store"))) 261 "znver4-direct,znver4-ieu,znver4-store") 262 263(define_insn_reservation "znver4_insn2_store" 1 264 (and (eq_attr "cpu" "znver4") 265 (and (eq_attr "type" "icmov,setcc") 266 (eq_attr "memory" "store"))) 267 "znver4-direct,znver4-ieu0|znver4-ieu3,znver4-store") 268 269(define_insn_reservation "znver4_rotate_store" 1 270 (and (eq_attr "cpu" "znver4") 271 (and (eq_attr "type" "rotate") 272 (eq_attr "memory" "store"))) 273 "znver4-direct,znver4-ieu1|znver4-ieu2,znver4-store") 274 275;; alu1 instructions 276(define_insn_reservation "znver4_alu1_vector" 3 277 (and (eq_attr "cpu" "znver4") 278 (and (eq_attr "znver1_decode" "vector") 279 (and (eq_attr "type" "alu1") 280 (eq_attr "memory" "none,unknown")))) 281 "znver4-vector,znver4-ivector*3") 282 283(define_insn_reservation "znver4_alu1_vector_load" 7 284 (and (eq_attr "cpu" "znver4") 285 (and (eq_attr "znver1_decode" "vector") 286 (and (eq_attr "type" "alu1") 287 (eq_attr "memory" "load")))) 288 "znver4-vector,znver4-load,znver4-ivector*3") 289 290;; Call Instruction 291(define_insn_reservation "znver4_call" 1 292 (and (eq_attr "cpu" "znver4") 293 (eq_attr "type" "call,callv")) 294 "znver4-double,znver4-ieu0|znver4-bru0,znver4-store") 295 296;; Branches 297(define_insn_reservation "znver4_branch" 1 298 (and (eq_attr "cpu" "znver4") 299 (and (eq_attr "type" "ibr") 300 (eq_attr "memory" "none"))) 301 "znver4-direct,znver4-ieu0|znver4-bru0") 302 303(define_insn_reservation "znver4_branch_load" 5 304 (and (eq_attr "cpu" "znver4") 305 (and (eq_attr "type" "ibr") 306 (eq_attr "memory" "load"))) 307 "znver4-direct,znver4-load,znver4-ieu0|znver4-bru0") 308 309(define_insn_reservation "znver4_branch_vector" 2 310 (and (eq_attr "cpu" "znver4") 311 (and (eq_attr "type" "ibr") 312 (eq_attr "memory" "none,unknown"))) 313 "znver4-vector,znver4-ivector*2") 314 315(define_insn_reservation "znver4_branch_vector_load" 6 316 (and (eq_attr "cpu" "znver4") 317 (and (eq_attr "type" "ibr") 318 (eq_attr "memory" "load"))) 319 "znver4-vector,znver4-load,znver4-ivector*2") 320 321;; LEA instruction with simple addressing 322(define_insn_reservation "znver4_lea" 1 323 (and (eq_attr "cpu" "znver4") 324 (eq_attr "type" "lea")) 325 "znver4-direct,znver4-ieu") 326 327;; Leave 328(define_insn_reservation "znver4_leave" 1 329 (and (eq_attr "cpu" "znver4") 330 (eq_attr "type" "leave")) 331 "znver4-double,znver4-ieu,znver4-store") 332 333;; STR and ISHIFT are microcoded. 334(define_insn_reservation "znver4_str" 3 335 (and (eq_attr "cpu" "znver4") 336 (and (eq_attr "type" "str") 337 (eq_attr "memory" "none"))) 338 "znver4-vector,znver4-ivector*3") 339 340(define_insn_reservation "znver4_str_load" 7 341 (and (eq_attr "cpu" "znver4") 342 (and (eq_attr "type" "str") 343 (eq_attr "memory" "load"))) 344 "znver4-vector,znver4-load,znver4-ivector*3") 345 346(define_insn_reservation "znver4_ishift" 2 347 (and (eq_attr "cpu" "znver4") 348 (and (eq_attr "type" "ishift") 349 (eq_attr "memory" "none"))) 350 "znver4-vector,znver4-ivector*2") 351 352(define_insn_reservation "znver4_ishift_load" 6 353 (and (eq_attr "cpu" "znver4") 354 (and (eq_attr "type" "ishift") 355 (eq_attr "memory" "load"))) 356 "znver4-vector,znver4-load,znver4-ivector*2") 357 358;; Other vector type 359(define_insn_reservation "znver4_ieu_vector" 5 360 (and (eq_attr "cpu" "znver4") 361 (and (eq_attr "type" "other,multi") 362 (eq_attr "memory" "none,unknown"))) 363 "znver4-vector,znver4-ivector*5") 364 365(define_insn_reservation "znver4_ieu_vector_load" 9 366 (and (eq_attr "cpu" "znver4") 367 (and (eq_attr "type" "other,multi") 368 (eq_attr "memory" "load"))) 369 "znver4-vector,znver4-load,znver4-ivector*5") 370 371;; Floating Point 372;; FP movs 373(define_insn_reservation "znver4_fp_cmov" 4 374 (and (eq_attr "cpu" "znver4") 375 (eq_attr "type" "fcmov")) 376 "znver4-vector,znver4-fvector*3") 377 378(define_insn_reservation "znver4_fp_mov_direct" 1 379 (and (eq_attr "cpu" "znver4") 380 (eq_attr "type" "fmov")) 381 "znver4-direct,znver4-fpu0|znver4-fpu1") 382 383;;FLD 384(define_insn_reservation "znver4_fp_mov_direct_load" 6 385 (and (eq_attr "cpu" "znver4") 386 (and (eq_attr "znver1_decode" "direct") 387 (and (eq_attr "type" "fmov") 388 (eq_attr "memory" "load")))) 389 "znver4-direct,znver4-load,znver4-fpu0|znver4-fpu1") 390 391;;FST 392(define_insn_reservation "znver4_fp_mov_direct_store" 6 393 (and (eq_attr "cpu" "znver4") 394 (and (eq_attr "znver1_decode" "direct") 395 (and (eq_attr "type" "fmov") 396 (eq_attr "memory" "store")))) 397 "znver4-direct,znver4-fpu0|znver4-fpu1,znver4-fp-store") 398 399;;FILD 400(define_insn_reservation "znver4_fp_mov_double_load" 13 401 (and (eq_attr "cpu" "znver4") 402 (and (eq_attr "znver1_decode" "double") 403 (and (eq_attr "type" "fmov") 404 (eq_attr "memory" "load")))) 405 "znver4-direct,znver4-load,znver4-fpu1") 406 407;;FIST 408(define_insn_reservation "znver4_fp_mov_double_store" 7 409 (and (eq_attr "cpu" "znver4") 410 (and (eq_attr "znver1_decode" "double") 411 (and (eq_attr "type" "fmov") 412 (eq_attr "memory" "store")))) 413 "znver4-double,znver4-fpu1,znver4-fp-store") 414 415;; FSQRT 416(define_insn_reservation "znver4_fsqrt" 22 417 (and (eq_attr "cpu" "znver4") 418 (and (eq_attr "type" "fpspc") 419 (and (eq_attr "mode" "XF") 420 (eq_attr "memory" "none")))) 421 "znver4-direct,znver4-fdiv*10") 422 423;; FPSPC instructions 424(define_insn_reservation "znver4_fp_spc" 6 425 (and (eq_attr "cpu" "znver4") 426 (and (eq_attr "type" "fpspc") 427 (eq_attr "memory" "none"))) 428 "znver4-vector,znver4-fvector*6") 429 430(define_insn_reservation "znver4_fp_insn_vector" 6 431 (and (eq_attr "cpu" "znver4") 432 (and (eq_attr "znver1_decode" "vector") 433 (eq_attr "type" "mmxcvt,sselog1,ssemov"))) 434 "znver4-vector,znver4-fvector*6") 435 436;; FADD, FSUB, FMUL 437(define_insn_reservation "znver4_fp_op_mul" 7 438 (and (eq_attr "cpu" "znver4") 439 (and (eq_attr "type" "fop,fmul") 440 (eq_attr "memory" "none"))) 441 "znver4-direct,znver4-fpu0") 442 443(define_insn_reservation "znver4_fp_op_mul_load" 12 444 (and (eq_attr "cpu" "znver4") 445 (and (eq_attr "type" "fop,fmul") 446 (eq_attr "memory" "load"))) 447 "znver4-direct,znver4-load,znver4-fpu0") 448 449;; FDIV 450(define_insn_reservation "znver4_fp_div" 15 451 (and (eq_attr "cpu" "znver4") 452 (and (eq_attr "type" "fdiv") 453 (eq_attr "memory" "none"))) 454 "znver4-direct,znver4-fdiv*6") 455 456(define_insn_reservation "znver4_fp_div_load" 20 457 (and (eq_attr "cpu" "znver4") 458 (and (eq_attr "type" "fdiv") 459 (eq_attr "memory" "load"))) 460 "znver4-direct,znver4-load,znver4-fdiv*6") 461 462(define_insn_reservation "znver4_fp_idiv_load" 24 463 (and (eq_attr "cpu" "znver4") 464 (and (eq_attr "type" "fdiv") 465 (and (eq_attr "fp_int_src" "true") 466 (eq_attr "memory" "load")))) 467 "znver4-double,znver4-load,znver4-fdiv*6") 468 469;; FABS, FCHS 470(define_insn_reservation "znver4_fp_fsgn" 1 471 (and (eq_attr "cpu" "znver4") 472 (eq_attr "type" "fsgn")) 473 "znver4-direct,znver4-fpu0|znver4-fpu1") 474 475;; FCMP 476(define_insn_reservation "znver4_fp_fcmp" 3 477 (and (eq_attr "cpu" "znver4") 478 (and (eq_attr "type" "fcmp") 479 (eq_attr "memory" "none"))) 480 "znver4-direct,znver4-fpu1") 481 482(define_insn_reservation "znver4_fp_fcmp_double" 4 483 (and (eq_attr "cpu" "znver4") 484 (and (eq_attr "type" "fcmp") 485 (and (eq_attr "znver1_decode" "double") 486 (eq_attr "memory" "none")))) 487 "znver4-double,znver4-fpu1,znver4-fpu2") 488 489;; MMX, SSE, SSEn.n instructions 490(define_insn_reservation "znver4_fp_mmx " 1 491 (and (eq_attr "cpu" "znver4") 492 (eq_attr "type" "mmx")) 493 "znver4-direct,znver4-fpu1|znver4-fpu2") 494 495(define_insn_reservation "znver4_mmx_add_cmp" 1 496 (and (eq_attr "cpu" "znver4") 497 (and (eq_attr "type" "mmxadd,mmxcmp") 498 (eq_attr "memory" "none"))) 499 "znver4-direct,znver4-fpu") 500 501(define_insn_reservation "znver4_mmx_add_cmp_load" 6 502 (and (eq_attr "cpu" "znver4") 503 (and (eq_attr "type" "mmxadd,mmxcmp") 504 (eq_attr "memory" "load"))) 505 "znver4-direct,znver4-load,znver4-fpu") 506 507(define_insn_reservation "znver4_mmx_insn" 1 508 (and (eq_attr "cpu" "znver4") 509 (and (eq_attr "type" "mmxcvt,sseshuf,sseshuf1,mmxshft") 510 (eq_attr "memory" "none"))) 511 "znver4-direct,znver4-fpu1|znver4-fpu2") 512 513(define_insn_reservation "znver4_mmx_insn_load" 6 514 (and (eq_attr "cpu" "znver4") 515 (and (eq_attr "type" "mmxcvt,sseshuf,sseshuf1,mmxshft") 516 (eq_attr "memory" "load"))) 517 "znver4-direct,znver4-load,znver4-fpu1|znver4-fpu2") 518 519(define_insn_reservation "znver4_mmx_mov" 1 520 (and (eq_attr "cpu" "znver4") 521 (and (eq_attr "type" "mmxmov") 522 (eq_attr "memory" "store"))) 523 "znver4-direct,znver4-fp-store") 524 525(define_insn_reservation "znver4_mmx_mov_load" 6 526 (and (eq_attr "cpu" "znver4") 527 (and (eq_attr "type" "mmxmov") 528 (eq_attr "memory" "both"))) 529 "znver4-direct,znver4-load,znver4-fp-store") 530 531(define_insn_reservation "znver4_mmx_mul" 3 532 (and (eq_attr "cpu" "znver4") 533 (and (eq_attr "type" "mmxmul") 534 (eq_attr "memory" "none"))) 535 "znver4-direct,znver4-fpu0|znver4-fpu3") 536 537(define_insn_reservation "znver4_mmx_mul_load" 8 538 (and (eq_attr "cpu" "znver4") 539 (and (eq_attr "type" "mmxmul") 540 (eq_attr "memory" "load"))) 541 "znver4-direct,znver4-load,znver4-fpu0|znver4-fpu3") 542 543;; AVX instructions 544(define_insn_reservation "znver4_sse_log" 1 545 (and (eq_attr "cpu" "znver4") 546 (and (eq_attr "type" "sselog") 547 (and (eq_attr "mode" "V4SF,V8SF,V2DF,V4DF,QI,HI,SI,DI,TI,OI") 548 (eq_attr "memory" "none")))) 549 "znver4-direct,znver4-fpu") 550 551(define_insn_reservation "znver4_sse_log_load" 6 552 (and (eq_attr "cpu" "znver4") 553 (and (eq_attr "type" "sselog") 554 (and (eq_attr "mode" "V4SF,V8SF,V2DF,V4DF,QI,HI,SI,DI,TI,OI") 555 (eq_attr "memory" "load")))) 556 "znver4-direct,znver4-load,znver4-fpu") 557 558(define_insn_reservation "znver4_sse_log1" 1 559 (and (eq_attr "cpu" "znver4") 560 (and (eq_attr "type" "sselog1") 561 (and (eq_attr "mode" "V4SF,V8SF,V2DF,V4DF,QI,HI,SI,DI,TI,OI") 562 (eq_attr "memory" "store")))) 563 "znver4-direct,znver4-fpu1|znver4-fpu2,znver4-fp-store") 564 565(define_insn_reservation "znver4_sse_log1_load" 6 566 (and (eq_attr "cpu" "znver4") 567 (and (eq_attr "type" "sselog1") 568 (and (eq_attr "mode" "V4SF,V8SF,V2DF,V4DF,QI,HI,SI,DI,TI,OI") 569 (eq_attr "memory" "both")))) 570 "znver4-direct,znver4-load,znver4-fpu1|znver4-fpu2,znver4-fp-store") 571 572(define_insn_reservation "znver4_sse_comi" 1 573 (and (eq_attr "cpu" "znver4") 574 (and (eq_attr "type" "ssecomi") 575 (eq_attr "memory" "store"))) 576 "znver4-double,znver4-fpu2|znver4-fpu3,znver4-fp-store") 577 578(define_insn_reservation "znver4_sse_comi_load" 6 579 (and (eq_attr "cpu" "znver4") 580 (and (eq_attr "type" "ssecomi") 581 (eq_attr "memory" "both"))) 582 "znver4-double,znver4-load,znver4-fpu2|znver4-fpu3,znver4-fp-store") 583 584(define_insn_reservation "znver4_sse_test" 1 585 (and (eq_attr "cpu" "znver4") 586 (and (eq_attr "prefix_extra" "1") 587 (and (eq_attr "type" "ssecomi") 588 (eq_attr "memory" "none")))) 589 "znver4-direct,znver4-fpu1|znver4-fpu2") 590 591(define_insn_reservation "znver4_sse_test_load" 6 592 (and (eq_attr "cpu" "znver4") 593 (and (eq_attr "prefix_extra" "1") 594 (and (eq_attr "type" "ssecomi") 595 (eq_attr "memory" "load")))) 596 "znver4-direct,znver4-load,znver4-fpu1|znver4-fpu2") 597 598(define_insn_reservation "znver4_sse_imul" 3 599 (and (eq_attr "cpu" "znver4") 600 (and (eq_attr "type" "sseimul") 601 (and (eq_attr "mode" "QI,HI,SI,DI,TI,OI") 602 (eq_attr "memory" "none")))) 603 "znver4-direct,znver4-fpu0|znver4-fpu3") 604 605(define_insn_reservation "znver4_sse_imul_load" 8 606 (and (eq_attr "cpu" "znver4") 607 (and (eq_attr "type" "sseimul") 608 (and (eq_attr "mode" "QI,HI,SI,DI,TI,OI") 609 (eq_attr "memory" "load")))) 610 "znver4-direct,znver4-load,znver4-fpu0|znver4-fpu1") 611 612(define_insn_reservation "znver4_sse_mov" 1 613 (and (eq_attr "cpu" "znver4") 614 (and (eq_attr "type" "ssemov") 615 (and (eq_attr "mode" "QI,HI,SI,DI,TI,OI") 616 (eq_attr "memory" "none")))) 617 "znver4-direct,znver4-fpu1|znver4-fpu2") 618 619(define_insn_reservation "znver4_sse_mov_load" 6 620 (and (eq_attr "cpu" "znver4") 621 (and (eq_attr "type" "ssemov") 622 (and (eq_attr "mode" "QI,HI,SI,DI,TI,OI") 623 (eq_attr "memory" "load")))) 624 "znver4-direct,znver4-load,znver4-fpu1|znver4-fpu2") 625 626(define_insn_reservation "znver4_sse_mov_store" 1 627 (and (eq_attr "cpu" "znver4") 628 (and (eq_attr "type" "ssemov") 629 (and (eq_attr "mode" "QI,HI,SI,DI,TI,OI") 630 (eq_attr "memory" "store")))) 631 "znver4-direct,znver4-fpu1|znver4-fpu2,znver4-fp-store") 632 633(define_insn_reservation "znver4_sse_mov_fp" 1 634 (and (eq_attr "cpu" "znver4") 635 (and (eq_attr "type" "ssemov") 636 (and (eq_attr "mode" "V16SF,V8DF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF") 637 (eq_attr "memory" "none")))) 638 "znver4-direct,znver4-fpu") 639 640(define_insn_reservation "znver4_sse_mov_fp_load" 6 641 (and (eq_attr "cpu" "znver4") 642 (and (eq_attr "type" "ssemov") 643 (and (eq_attr "mode" "V16SF,V8DF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF") 644 (eq_attr "memory" "load")))) 645 "znver4-direct,znver4-load,znver4-fpu") 646 647(define_insn_reservation "znver4_sse_mov_fp_store" 1 648 (and (eq_attr "cpu" "znver4") 649 (and (eq_attr "type" "ssemov") 650 (and (eq_attr "mode" "V16SF,V8DF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF") 651 (eq_attr "memory" "store")))) 652 "znver4-direct,znver4-fp-store") 653 654(define_insn_reservation "znver4_sse_add" 3 655 (and (eq_attr "cpu" "znver4") 656 (and (eq_attr "type" "sseadd") 657 (and (eq_attr "mode" "V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF") 658 (eq_attr "memory" "none")))) 659 "znver4-direct,znver4-fpu2|znver4-fpu3") 660 661(define_insn_reservation "znver4_sse_add_load" 8 662 (and (eq_attr "cpu" "znver4") 663 (and (eq_attr "type" "sseadd") 664 (and (eq_attr "mode" "V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF") 665 (eq_attr "memory" "load")))) 666 "znver4-direct,znver4-load,znver4-fpu2|znver4-fpu3") 667 668(define_insn_reservation "znver4_sse_add1" 4 669 (and (eq_attr "cpu" "znver4") 670 (and (eq_attr "type" "sseadd1") 671 (and (eq_attr "mode" "V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF") 672 (eq_attr "memory" "none")))) 673 "znver4-vector,znver4-fvector*2") 674 675(define_insn_reservation "znver4_sse_add1_load" 9 676 (and (eq_attr "cpu" "znver4") 677 (and (eq_attr "type" "sseadd1") 678 (and (eq_attr "mode" "V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF") 679 (eq_attr "memory" "load")))) 680 "znver4-vector,znver4-load,znver4-fvector*2") 681 682(define_insn_reservation "znver4_sse_iadd" 1 683 (and (eq_attr "cpu" "znver4") 684 (and (eq_attr "type" "sseiadd") 685 (and (eq_attr "mode" "QI,HI,SI,DI,TI,OI") 686 (eq_attr "memory" "none")))) 687 "znver4-direct,znver4-fpu") 688 689(define_insn_reservation "znver4_sse_iadd_load" 6 690 (and (eq_attr "cpu" "znver4") 691 (and (eq_attr "type" "sseiadd") 692 (and (eq_attr "mode" "QI,HI,SI,DI,TI,OI") 693 (eq_attr "memory" "load")))) 694 "znver4-direct,znver4-load,znver4-fpu") 695 696(define_insn_reservation "znver4_sse_mul" 3 697 (and (eq_attr "cpu" "znver4") 698 (and (eq_attr "type" "ssemul") 699 (and (eq_attr "mode" "V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF") 700 (eq_attr "memory" "none")))) 701 "znver4-direct,znver4-fpu0|znver4-fpu1") 702 703(define_insn_reservation "znver4_sse_mul_load" 8 704 (and (eq_attr "cpu" "znver4") 705 (and (eq_attr "type" "ssemul") 706 (and (eq_attr "mode" "V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF") 707 (eq_attr "memory" "load")))) 708 "znver4-direct,znver4-load,znver4-fpu0|znver4-fpu1") 709 710(define_insn_reservation "znver4_sse_div_pd" 13 711 (and (eq_attr "cpu" "znver4") 712 (and (eq_attr "type" "ssediv") 713 (and (eq_attr "mode" "V4DF,V2DF,V1DF") 714 (eq_attr "memory" "none")))) 715 "znver4-direct,znver4-fdiv*5") 716 717(define_insn_reservation "znver4_sse_div_ps" 10 718 (and (eq_attr "cpu" "znver4") 719 (and (eq_attr "type" "ssediv") 720 (and (eq_attr "mode" "V8SF,V4SF,V2SF,SF") 721 (eq_attr "memory" "none")))) 722 "znver4-direct,znver4-fdiv*3") 723 724(define_insn_reservation "znver4_sse_div_pd_load" 18 725 (and (eq_attr "cpu" "znver4") 726 (and (eq_attr "type" "ssediv") 727 (and (eq_attr "mode" "V4DF,V2DF,V1DF") 728 (eq_attr "memory" "load")))) 729 "znver4-direct,znver4-load,znver4-fdiv*5") 730 731(define_insn_reservation "znver4_sse_div_ps_load" 15 732 (and (eq_attr "cpu" "znver4") 733 (and (eq_attr "type" "ssediv") 734 (and (eq_attr "mode" "V8SF,V4SF,V2SF,SF") 735 (eq_attr "memory" "load")))) 736 "znver4-direct,znver4-load,znver4-fdiv*3") 737 738(define_insn_reservation "znver4_sse_cmp_avx" 1 739 (and (eq_attr "cpu" "znver4") 740 (and (eq_attr "type" "ssecmp") 741 (and (eq_attr "prefix" "vex") 742 (eq_attr "memory" "none")))) 743 "znver4-direct,znver4-fpu0|znver4-fpu1") 744 745(define_insn_reservation "znver4_sse_cmp_avx_load" 6 746 (and (eq_attr "cpu" "znver4") 747 (and (eq_attr "type" "ssecmp") 748 (and (eq_attr "prefix" "vex") 749 (eq_attr "memory" "load")))) 750 "znver4-direct,znver4-load,znver4-fpu0|znver4-fpu1") 751 752(define_insn_reservation "znver4_sse_comi_avx" 1 753 (and (eq_attr "cpu" "znver4") 754 (and (eq_attr "type" "ssecomi") 755 (eq_attr "memory" "store"))) 756 "znver4-direct,znver4-fpu2+znver4-fpu3,znver4-fp-store") 757 758(define_insn_reservation "znver4_sse_comi_avx_load" 6 759 (and (eq_attr "cpu" "znver4") 760 (and (eq_attr "type" "ssecomi") 761 (eq_attr "memory" "both"))) 762 "znver4-direct,znver4-load,znver4-fpu2+znver4-fpu3,znver4-fp-store") 763 764(define_insn_reservation "znver4_sse_cvt" 3 765 (and (eq_attr "cpu" "znver4") 766 (and (eq_attr "type" "ssecvt") 767 (and (eq_attr "mode" "V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF") 768 (eq_attr "memory" "none")))) 769 "znver4-direct,znver4-fpu2|znver4-fpu3") 770 771(define_insn_reservation "znver4_sse_cvt_load" 8 772 (and (eq_attr "cpu" "znver4") 773 (and (eq_attr "type" "ssecvt") 774 (and (eq_attr "mode" "V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF") 775 (eq_attr "memory" "load")))) 776 "znver4-direct,znver4-load,znver4-fpu2|znver4-fpu3") 777 778(define_insn_reservation "znver4_sse_icvt" 3 779 (and (eq_attr "cpu" "znver4") 780 (and (eq_attr "type" "ssecvt") 781 (and (eq_attr "mode" "SI") 782 (eq_attr "memory" "none")))) 783 "znver4-direct,znver4-fpu2|znver4-fpu3") 784 785(define_insn_reservation "znver4_sse_icvt_store" 4 786 (and (eq_attr "cpu" "znver4") 787 (and (eq_attr "type" "ssecvt") 788 (and (eq_attr "mode" "SI") 789 (eq_attr "memory" "store")))) 790 "znver4-double,znver4-fpu2|znver4-fpu3,znver4-fp-store") 791 792(define_insn_reservation "znver4_sse_shuf" 1 793 (and (eq_attr "cpu" "znver4") 794 (and (eq_attr "type" "sseshuf") 795 (and (eq_attr "mode" "V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF") 796 (eq_attr "memory" "none")))) 797 "znver4-direct,znver4-fpu1|znver4-fpu2") 798 799(define_insn_reservation "znver4_sse_shuf_load" 6 800 (and (eq_attr "cpu" "znver4") 801 (and (eq_attr "type" "sseshuf") 802 (and (eq_attr "mode" "V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF") 803 (eq_attr "memory" "load")))) 804 "znver4-direct,znver4-load,znver4-fpu") 805 806(define_insn_reservation "znver4_sse_ishuf" 3 807 (and (eq_attr "cpu" "znver4") 808 (and (eq_attr "type" "sseshuf") 809 (and (eq_attr "mode" "OI") 810 (eq_attr "memory" "none")))) 811 "znver4-direct,znver4-fpu1|znver4-fpu2") 812 813(define_insn_reservation "znver4_sse_ishuf_load" 8 814 (and (eq_attr "cpu" "znver4") 815 (and (eq_attr "type" "sseshuf") 816 (and (eq_attr "mode" "OI") 817 (eq_attr "memory" "load")))) 818 "znver4-direct,znver4-load,znver4-fpu1|znver4-fpu2") 819 820;; AVX512 instructions 821(define_insn_reservation "znver4_sse_log_evex" 1 822 (and (eq_attr "cpu" "znver4") 823 (and (eq_attr "type" "sselog") 824 (and (eq_attr "mode" "V16SF,V8DF,XI") 825 (eq_attr "memory" "none")))) 826 "znver4-direct,znver4-fpu0*2|znver4-fpu1*2|znver4-fpu2*2|znver4-fpu3*2") 827 828(define_insn_reservation "znver4_sse_log_evex_load" 7 829 (and (eq_attr "cpu" "znver4") 830 (and (eq_attr "type" "sselog") 831 (and (eq_attr "mode" "V16SF,V8DF,XI") 832 (eq_attr "memory" "load")))) 833 "znver4-direct,znver4-load,znver4-fpu0*2|znver4-fpu1*2|znver4-fpu2*2|znver4-fpu3*2") 834 835(define_insn_reservation "znver4_sse_log1_evex" 1 836 (and (eq_attr "cpu" "znver4") 837 (and (eq_attr "type" "sselog1") 838 (and (eq_attr "mode" "V16SF,V8DF,XI") 839 (eq_attr "memory" "none")))) 840 "znver4-direct,znver4-fpu1*2|znver4-fpu2*2,znver4-fp-store") 841 842(define_insn_reservation "znver4_sse_log1_evex_load" 7 843 (and (eq_attr "cpu" "znver4") 844 (and (eq_attr "type" "sselog1") 845 (and (eq_attr "mode" "V16SF,V8DF,XI") 846 (eq_attr "memory" "load")))) 847 "znver4-direct,znver4-load,znver4-fpu1*2|znver4-fpu2*2,znver4-fp-store") 848 849(define_insn_reservation "znver4_sse_mul_evex" 3 850 (and (eq_attr "cpu" "znver4") 851 (and (eq_attr "type" "ssemul") 852 (and (eq_attr "mode" "V16SF,V8DF") 853 (eq_attr "memory" "none")))) 854 "znver4-direct,znver4-fpu0*2|znver4-fpu1*2") 855 856(define_insn_reservation "znver4_sse_mul_evex_load" 9 857 (and (eq_attr "cpu" "znver4") 858 (and (eq_attr "type" "ssemul") 859 (and (eq_attr "mode" "V16SF,V8DF") 860 (eq_attr "memory" "load")))) 861 "znver4-direct,znver4-load,znver4-fpu0*2|znver4-fpu1*2") 862 863(define_insn_reservation "znver4_sse_imul_evex" 3 864 (and (eq_attr "cpu" "znver4") 865 (and (eq_attr "type" "sseimul") 866 (and (eq_attr "mode" "XI") 867 (eq_attr "memory" "none")))) 868 "znver4-direct,znver4-fpu0*2|znver4-fpu3*2") 869 870(define_insn_reservation "znver4_sse_imul_evex_load" 9 871 (and (eq_attr "cpu" "znver4") 872 (and (eq_attr "type" "sseimul") 873 (and (eq_attr "mode" "XI") 874 (eq_attr "memory" "load")))) 875 "znver4-direct,znver4-load,znver4-fpu0*2|znver4-fpu1*2") 876 877(define_insn_reservation "znver4_sse_mov_evex" 4 878 (and (eq_attr "cpu" "znver4") 879 (and (eq_attr "type" "ssemov") 880 (and (eq_attr "mode" "XI") 881 (eq_attr "memory" "none")))) 882 "znver4-direct,znver4-fpu1*2|znver4-fpu2*2") 883 884(define_insn_reservation "znver4_sse_mov_evex_load" 10 885 (and (eq_attr "cpu" "znver4") 886 (and (eq_attr "type" "ssemov") 887 (and (eq_attr "mode" "XI") 888 (eq_attr "memory" "load")))) 889 "znver4-direct,znver4-load,znver4-fpu1*2|znver4-fpu2*2") 890 891(define_insn_reservation "znver4_sse_mov_evex_store" 5 892 (and (eq_attr "cpu" "znver4") 893 (and (eq_attr "type" "ssemov") 894 (and (eq_attr "mode" "XI") 895 (eq_attr "memory" "store")))) 896 "znver4-direct,znver4-fpu1*2|znver4-fpu2*2,znver4-fp-store") 897 898(define_insn_reservation "znver4_sse_add_evex" 3 899 (and (eq_attr "cpu" "znver4") 900 (and (eq_attr "type" "sseadd") 901 (and (eq_attr "mode" "V16SF,V8DF") 902 (eq_attr "memory" "none")))) 903 "znver4-direct,znver4-fpu2*2|znver4-fpu3*2") 904 905(define_insn_reservation "znver4_sse_add_evex_load" 9 906 (and (eq_attr "cpu" "znver4") 907 (and (eq_attr "type" "sseadd") 908 (and (eq_attr "mode" "V16SF,V8DF") 909 (eq_attr "memory" "load")))) 910 "znver4-direct,znver4-load,znver4-fpu2*2|znver4-fpu3*2") 911 912(define_insn_reservation "znver4_sse_iadd_evex" 1 913 (and (eq_attr "cpu" "znver4") 914 (and (eq_attr "type" "sseiadd") 915 (and (eq_attr "mode" "XI") 916 (eq_attr "memory" "none")))) 917 "znver4-direct,znver4-fpu0*2|znver4-fpu1*2|znver4-fpu2*2|znver4-fpu3*2") 918 919(define_insn_reservation "znver4_sse_iadd_evex_load" 7 920 (and (eq_attr "cpu" "znver4") 921 (and (eq_attr "type" "sseiadd") 922 (and (eq_attr "mode" "XI") 923 (eq_attr "memory" "load")))) 924 "znver4-direct,znver4-load,znver4-fpu0*2|znver4-fpu1*2|znver4-fpu2*2|znver4-fpu3*2") 925 926(define_insn_reservation "znver4_sse_div_pd_evex" 13 927 (and (eq_attr "cpu" "znver4") 928 (and (eq_attr "type" "ssediv") 929 (and (eq_attr "mode" "V8DF") 930 (eq_attr "memory" "none")))) 931 "znver4-direct,znver4-fdiv*9") 932 933(define_insn_reservation "znver4_sse_div_ps_evex" 10 934 (and (eq_attr "cpu" "znver4") 935 (and (eq_attr "type" "ssediv") 936 (and (eq_attr "mode" "V16SF") 937 (eq_attr "memory" "none")))) 938 "znver4-direct,znver4-fdiv*6") 939 940(define_insn_reservation "znver4_sse_div_pd_evex_load" 19 941 (and (eq_attr "cpu" "znver4") 942 (and (eq_attr "type" "ssediv") 943 (and (eq_attr "mode" "V8DF") 944 (eq_attr "memory" "load")))) 945 "znver4-direct,znver4-load,znver4-fdiv*9") 946 947(define_insn_reservation "znver4_sse_div_ps_evex_load" 16 948 (and (eq_attr "cpu" "znver4") 949 (and (eq_attr "type" "ssediv") 950 (and (eq_attr "mode" "V16SF") 951 (eq_attr "memory" "load")))) 952 "znver4-direct,znver4-load,znver4-fdiv*6") 953 954(define_insn_reservation "znver4_sse_cmp_avx128" 3 955 (and (eq_attr "cpu" "znver4") 956 (and (eq_attr "type" "ssecmp") 957 (and (eq_attr "mode" "V4SF,V2DF,V2SF,V1DF,SF") 958 (and (eq_attr "prefix" "evex") 959 (eq_attr "memory" "none"))))) 960 "znver4-direct,znver4-fpu0*2|znver4-fpu1*2") 961 962(define_insn_reservation "znver4_sse_cmp_avx128_load" 9 963 (and (eq_attr "cpu" "znver4") 964 (and (eq_attr "type" "ssecmp") 965 (and (eq_attr "mode" "V4SF,V2DF,V2SF,V1DF,SF") 966 (and (eq_attr "prefix" "evex") 967 (eq_attr "memory" "load"))))) 968 "znver4-direct,znver4-load,znver4-fpu0*2|znver4-fpu1*2") 969 970(define_insn_reservation "znver4_sse_cmp_avx256" 4 971 (and (eq_attr "cpu" "znver4") 972 (and (eq_attr "type" "ssecmp") 973 (and (eq_attr "mode" "V8SF,V4DF") 974 (and (eq_attr "prefix" "evex") 975 (eq_attr "memory" "none"))))) 976 "znver4-direct,znver4-fpu0*2|znver4-fpu1*2") 977 978(define_insn_reservation "znver4_sse_cmp_avx256_load" 10 979 (and (eq_attr "cpu" "znver4") 980 (and (eq_attr "type" "ssecmp") 981 (and (eq_attr "mode" "V8SF,V4DF") 982 (and (eq_attr "prefix" "evex") 983 (eq_attr "memory" "load"))))) 984 "znver4-direct,znver4-load,znver4-fpu0*2|znver4-fpu1*2") 985 986(define_insn_reservation "znver4_sse_cmp_avx512" 5 987 (and (eq_attr "cpu" "znver4") 988 (and (eq_attr "type" "ssecmp") 989 (and (eq_attr "mode" "V16SF,V8DF") 990 (and (eq_attr "prefix" "evex") 991 (eq_attr "memory" "none"))))) 992 "znver4-direct,znver4-fpu0*2|znver4-fpu1*2") 993 994(define_insn_reservation "znver4_sse_cmp_avx512_load" 11 995 (and (eq_attr "cpu" "znver4") 996 (and (eq_attr "type" "ssecmp") 997 (and (eq_attr "mode" "V16SF,V8DF") 998 (and (eq_attr "prefix" "evex") 999 (eq_attr "memory" "load"))))) 1000 "znver4-direct,znver4-load,znver4-fpu0*2|znver4-fpu1*2") 1001 1002(define_insn_reservation "znver4_sse_cvt_evex" 6 1003 (and (eq_attr "cpu" "znver4") 1004 (and (eq_attr "type" "ssecvt") 1005 (and (eq_attr "mode" "V16SF,V8DF") 1006 (eq_attr "memory" "none")))) 1007 "znver4-direct,znver4-fpu1*2|znver4-fpu2*2,znver4-fpu2*2|znver4-fpu3*2") 1008 1009(define_insn_reservation "znver4_sse_cvt_evex_load" 12 1010 (and (eq_attr "cpu" "znver4") 1011 (and (eq_attr "type" "ssecvt") 1012 (and (eq_attr "mode" "V16SF,V8DF") 1013 (eq_attr "memory" "load")))) 1014 "znver4-direct,znver4-load,znver4-fpu1*2|znver4-fpu2*2,znver4-fpu2*2|znver4-fpu3*2") 1015 1016(define_insn_reservation "znver4_sse_shuf_evex" 1 1017 (and (eq_attr "cpu" "znver4") 1018 (and (eq_attr "type" "sseshuf") 1019 (and (eq_attr "mode" "V16SF,V8DF") 1020 (eq_attr "memory" "none")))) 1021 "znver4-direct,znver4-fpu0*2|znver4-fpu1*2|znver4-fpu2*2|znver4-fpu3*2") 1022 1023(define_insn_reservation "znver4_sse_shuf_evex_load" 7 1024 (and (eq_attr "cpu" "znver4") 1025 (and (eq_attr "type" "sseshuf") 1026 (and (eq_attr "mode" "V16SF,V8DF") 1027 (eq_attr "memory" "load")))) 1028 "znver4-direct,znver4-load,znver4-fpu0*2|znver4-fpu1*2|znver4-fpu2*2|znver4-fpu3*2") 1029 1030(define_insn_reservation "znver4_sse_ishuf_evex" 4 1031 (and (eq_attr "cpu" "znver4") 1032 (and (eq_attr "type" "sseshuf") 1033 (and (eq_attr "mode" "XI") 1034 (eq_attr "memory" "none")))) 1035 "znver4-direct,znver4-fpu1*2|znver4-fpu2*2") 1036 1037(define_insn_reservation "znver4_sse_ishuf_evex_load" 10 1038 (and (eq_attr "cpu" "znver4") 1039 (and (eq_attr "type" "sseshuf") 1040 (and (eq_attr "mode" "XI") 1041 (eq_attr "memory" "load")))) 1042 "znver4-direct,znver4-load,znver4-fpu1*2|znver4-fpu2*2") 1043 1044(define_insn_reservation "znver4_sse_muladd" 4 1045 (and (eq_attr "cpu" "znver4") 1046 (and (eq_attr "type" "ssemuladd") 1047 (eq_attr "memory" "none"))) 1048 "znver4-direct,znver4-fpu0*2|znver4-fpu1*2") 1049 1050(define_insn_reservation "znver4_sse_muladd_load" 10 1051 (and (eq_attr "cpu" "znver4") 1052 (and (eq_attr "type" "sseshuf") 1053 (eq_attr "memory" "load"))) 1054 "znver4-direct,znver4-load,znver4-fpu0*2|znver4-fpu1*2") 1055 1056;; AVX512 mask instructions 1057 1058(define_insn_reservation "znver4_sse_mskmov" 2 1059 (and (eq_attr "cpu" "znver4") 1060 (and (eq_attr "type" "mskmov") 1061 (eq_attr "memory" "none"))) 1062 "znver4-direct,znver4-fpu0*2|znver4-fpu1*2") 1063 1064(define_insn_reservation "znver4_sse_msklog" 1 1065 (and (eq_attr "cpu" "znver4") 1066 (and (eq_attr "type" "msklog") 1067 (eq_attr "memory" "none"))) 1068 "znver4-direct,znver4-fpu2*2|znver4-fpu3*2") 1069