1 //===-- x86_64 floating point env manipulation functions --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #ifndef LLVM_LIBC_SRC___SUPPORT_FPUTIL_X86_64_FENVIMPL_H 10 #define LLVM_LIBC_SRC___SUPPORT_FPUTIL_X86_64_FENVIMPL_H 11 12 #include "src/__support/macros/attributes.h" // LIBC_INLINE 13 #include "src/__support/macros/config.h" 14 #include "src/__support/macros/properties/architectures.h" 15 16 #if !defined(LIBC_TARGET_ARCH_IS_X86) 17 #error "Invalid include" 18 #endif 19 20 #include <stdint.h> 21 22 #include "hdr/types/fenv_t.h" 23 #include "src/__support/macros/sanitizer.h" 24 25 namespace LIBC_NAMESPACE_DECL { 26 namespace fputil { 27 28 namespace internal { 29 30 // Normally, one should be able to define FE_* macros to the exact rounding mode 31 // encodings. However, since we want LLVM libc to be compiled against headers 32 // from other libcs, we cannot assume that FE_* macros are always defined in 33 // such a manner. So, we will define enums corresponding to the x86_64 bit 34 // encodings. The implementations can map from FE_* to the corresponding enum 35 // values. 36 37 // The rounding control values in the x87 control register and the MXCSR 38 // register have the same 2-bit enoding but have different bit positions. 39 // See below for the bit positions. 40 struct RoundingControlValue { 41 static constexpr uint16_t TO_NEAREST = 0x0; 42 static constexpr uint16_t DOWNWARD = 0x1; 43 static constexpr uint16_t UPWARD = 0x2; 44 static constexpr uint16_t TOWARD_ZERO = 0x3; 45 }; 46 47 static constexpr uint16_t X87_ROUNDING_CONTROL_BIT_POSITION = 10; 48 static constexpr uint16_t MXCSR_ROUNDING_CONTROL_BIT_POSITION = 13; 49 50 // The exception flags in the x87 status register and the MXCSR have the same 51 // encoding as well as the same bit positions. 52 struct ExceptionFlags { 53 static constexpr uint16_t INVALID_F = 0x1; 54 // Some libcs define __FE_DENORM corresponding to the denormal input 55 // exception and include it in FE_ALL_EXCEPTS. We define and use it to 56 // support compiling against headers provided by such libcs. 57 static constexpr uint16_t DENORMAL_F = 0x2; 58 static constexpr uint16_t DIV_BY_ZERO_F = 0x4; 59 static constexpr uint16_t OVERFLOW_F = 0x8; 60 static constexpr uint16_t UNDERFLOW_F = 0x10; 61 static constexpr uint16_t INEXACT_F = 0x20; 62 }; 63 64 // The exception control bits occupy six bits, one bit for each exception. 65 // In the x87 control word, they occupy the first 6 bits. In the MXCSR 66 // register, they occupy bits 7 to 12. 67 static constexpr uint16_t X87_EXCEPTION_CONTROL_BIT_POSITION = 0; 68 static constexpr uint16_t X87_EXCEPTION_CONTROL_BIT_POSITION_HIGH = 24; 69 static constexpr uint16_t MXCSR_EXCEPTION_CONTOL_BIT_POISTION = 7; 70 71 // Exception flags are individual bits in the corresponding registers. 72 // So, we just OR the bit values to get the full set of exceptions. 73 LIBC_INLINE uint16_t get_status_value_for_except(int excepts) { 74 // We will make use of the fact that exception control bits are single 75 // bit flags in the control registers. 76 return ((excepts & FE_INVALID) ? ExceptionFlags::INVALID_F : 0) | 77 #ifdef __FE_DENORM 78 ((excepts & __FE_DENORM) ? ExceptionFlags::DENORMAL_F : 0) | 79 #endif // __FE_DENORM 80 ((excepts & FE_DIVBYZERO) ? ExceptionFlags::DIV_BY_ZERO_F : 0) | 81 ((excepts & FE_OVERFLOW) ? ExceptionFlags::OVERFLOW_F : 0) | 82 ((excepts & FE_UNDERFLOW) ? ExceptionFlags::UNDERFLOW_F : 0) | 83 ((excepts & FE_INEXACT) ? ExceptionFlags::INEXACT_F : 0); 84 } 85 86 LIBC_INLINE int exception_status_to_macro(uint16_t status) { 87 return ((status & ExceptionFlags::INVALID_F) ? FE_INVALID : 0) | 88 #ifdef __FE_DENORM 89 ((status & ExceptionFlags::DENORMAL_F) ? __FE_DENORM : 0) | 90 #endif // __FE_DENORM 91 ((status & ExceptionFlags::DIV_BY_ZERO_F) ? FE_DIVBYZERO : 0) | 92 ((status & ExceptionFlags::OVERFLOW_F) ? FE_OVERFLOW : 0) | 93 ((status & ExceptionFlags::UNDERFLOW_F) ? FE_UNDERFLOW : 0) | 94 ((status & ExceptionFlags::INEXACT_F) ? FE_INEXACT : 0); 95 } 96 97 struct X87StateDescriptor { 98 uint16_t control_word; 99 uint16_t unused1; 100 uint16_t status_word; 101 uint16_t unused2; 102 // TODO: Elaborate the remaining 20 bytes as required. 103 uint32_t _[5]; 104 }; 105 106 LIBC_INLINE uint16_t get_x87_control_word() { 107 uint16_t w; 108 __asm__ __volatile__("fnstcw %0" : "=m"(w)::); 109 MSAN_UNPOISON(&w, sizeof(w)); 110 return w; 111 } 112 113 LIBC_INLINE void write_x87_control_word(uint16_t w) { 114 __asm__ __volatile__("fldcw %0" : : "m"(w) :); 115 } 116 117 LIBC_INLINE uint16_t get_x87_status_word() { 118 uint16_t w; 119 __asm__ __volatile__("fnstsw %0" : "=m"(w)::); 120 MSAN_UNPOISON(&w, sizeof(w)); 121 return w; 122 } 123 124 LIBC_INLINE void clear_x87_exceptions() { 125 __asm__ __volatile__("fnclex" : : :); 126 } 127 128 LIBC_INLINE uint32_t get_mxcsr() { 129 uint32_t w; 130 __asm__ __volatile__("stmxcsr %0" : "=m"(w)::); 131 MSAN_UNPOISON(&w, sizeof(w)); 132 return w; 133 } 134 135 LIBC_INLINE void write_mxcsr(uint32_t w) { 136 __asm__ __volatile__("ldmxcsr %0" : : "m"(w) :); 137 } 138 139 LIBC_INLINE void get_x87_state_descriptor(X87StateDescriptor &s) { 140 __asm__ __volatile__("fnstenv %0" : "=m"(s)); 141 MSAN_UNPOISON(&s, sizeof(s)); 142 } 143 144 LIBC_INLINE void write_x87_state_descriptor(const X87StateDescriptor &s) { 145 __asm__ __volatile__("fldenv %0" : : "m"(s) :); 146 } 147 148 LIBC_INLINE void fwait() { __asm__ __volatile__("fwait"); } 149 150 } // namespace internal 151 152 LIBC_INLINE int enable_except(int excepts) { 153 // In the x87 control word and in MXCSR, an exception is blocked 154 // if the corresponding bit is set. That is the reason for all the 155 // bit-flip operations below as we need to turn the bits to zero 156 // to enable them. 157 158 uint16_t bit_mask = internal::get_status_value_for_except(excepts); 159 160 uint16_t x87_cw = internal::get_x87_control_word(); 161 uint16_t old_excepts = ~x87_cw & 0x3F; // Save previously enabled exceptions. 162 x87_cw &= ~bit_mask; 163 internal::write_x87_control_word(x87_cw); 164 165 // Enabling SSE exceptions via MXCSR is a nice thing to do but 166 // might not be of much use practically as SSE exceptions and the x87 167 // exceptions are independent of each other. 168 uint32_t mxcsr = internal::get_mxcsr(); 169 mxcsr &= ~(bit_mask << internal::MXCSR_EXCEPTION_CONTOL_BIT_POISTION); 170 internal::write_mxcsr(mxcsr); 171 172 // Since the x87 exceptions and SSE exceptions are independent of each, 173 // it doesn't make much sence to report both in the return value. Most 174 // often, the standard floating point functions deal with FPU operations 175 // so we will retrun only the old x87 exceptions. 176 return internal::exception_status_to_macro(old_excepts); 177 } 178 179 LIBC_INLINE int disable_except(int excepts) { 180 // In the x87 control word and in MXCSR, an exception is blocked 181 // if the corresponding bit is set. 182 183 uint16_t bit_mask = internal::get_status_value_for_except(excepts); 184 185 uint16_t x87_cw = internal::get_x87_control_word(); 186 uint16_t old_excepts = ~x87_cw & 0x3F; // Save previously enabled exceptions. 187 x87_cw |= bit_mask; 188 internal::write_x87_control_word(x87_cw); 189 190 // Just like in enable_except, it is not clear if disabling SSE exceptions 191 // is required. But, we will still do it only as a "nice thing to do". 192 uint32_t mxcsr = internal::get_mxcsr(); 193 mxcsr |= (bit_mask << internal::MXCSR_EXCEPTION_CONTOL_BIT_POISTION); 194 internal::write_mxcsr(mxcsr); 195 196 return internal::exception_status_to_macro(old_excepts); 197 } 198 199 LIBC_INLINE int get_except() { 200 uint16_t mxcsr = static_cast<uint16_t>(internal::get_mxcsr()); 201 uint16_t enabled_excepts = ~(mxcsr >> 7) & 0x3F; 202 return internal::exception_status_to_macro(enabled_excepts); 203 } 204 205 LIBC_INLINE int clear_except(int excepts) { 206 internal::X87StateDescriptor state; 207 internal::get_x87_state_descriptor(state); 208 state.status_word &= 209 static_cast<uint16_t>(~internal::get_status_value_for_except(excepts)); 210 internal::write_x87_state_descriptor(state); 211 212 uint32_t mxcsr = internal::get_mxcsr(); 213 mxcsr &= ~internal::get_status_value_for_except(excepts); 214 internal::write_mxcsr(mxcsr); 215 return 0; 216 } 217 218 LIBC_INLINE int test_except(int excepts) { 219 uint16_t status_word = internal::get_x87_status_word(); 220 uint32_t mxcsr = internal::get_mxcsr(); 221 // Check both x87 status word and MXCSR. 222 uint16_t status_value = internal::get_status_value_for_except(excepts); 223 return internal::exception_status_to_macro( 224 static_cast<uint16_t>(status_value & (status_word | mxcsr))); 225 } 226 227 // Sets the exception flags but does not trigger the exception handler. 228 LIBC_INLINE int set_except(int excepts) { 229 uint16_t status_value = internal::get_status_value_for_except(excepts); 230 internal::X87StateDescriptor state; 231 internal::get_x87_state_descriptor(state); 232 state.status_word |= status_value; 233 internal::write_x87_state_descriptor(state); 234 235 uint32_t mxcsr = internal::get_mxcsr(); 236 mxcsr |= status_value; 237 internal::write_mxcsr(mxcsr); 238 239 return 0; 240 } 241 242 LIBC_INLINE int raise_except(int excepts) { 243 uint16_t status_value = internal::get_status_value_for_except(excepts); 244 245 // We set the status flag for exception one at a time and call the 246 // fwait instruction to actually get the processor to raise the 247 // exception by calling the exception handler. This scheme is per 248 // the description in "8.6 X87 FPU EXCEPTION SYNCHRONIZATION" 249 // of the "Intel 64 and IA-32 Architectures Software Developer's 250 // Manual, Vol 1". 251 252 // FPU status word is read for each exception separately as the 253 // exception handler can potentially write to it (typically to clear 254 // the corresponding exception flag). By reading it separately, we 255 // ensure that the writes by the exception handler are maintained 256 // when raising the next exception. 257 258 auto raise_helper = [](uint16_t singleExceptFlag) { 259 internal::X87StateDescriptor state; 260 uint32_t mxcsr = 0; 261 internal::get_x87_state_descriptor(state); 262 mxcsr = internal::get_mxcsr(); 263 state.status_word |= singleExceptFlag; 264 mxcsr |= singleExceptFlag; 265 internal::write_x87_state_descriptor(state); 266 internal::write_mxcsr(mxcsr); 267 internal::fwait(); 268 }; 269 270 if (status_value & internal::ExceptionFlags::INVALID_F) 271 raise_helper(internal::ExceptionFlags::INVALID_F); 272 if (status_value & internal::ExceptionFlags::DIV_BY_ZERO_F) 273 raise_helper(internal::ExceptionFlags::DIV_BY_ZERO_F); 274 if (status_value & internal::ExceptionFlags::OVERFLOW_F) 275 raise_helper(internal::ExceptionFlags::OVERFLOW_F); 276 if (status_value & internal::ExceptionFlags::UNDERFLOW_F) 277 raise_helper(internal::ExceptionFlags::UNDERFLOW_F); 278 if (status_value & internal::ExceptionFlags::INEXACT_F) 279 raise_helper(internal::ExceptionFlags::INEXACT_F); 280 #ifdef __FE_DENORM 281 if (status_value & internal::ExceptionFlags::DENORMAL_F) { 282 raise_helper(internal::ExceptionFlags::DENORMAL_F); 283 } 284 #endif // __FE_DENORM 285 286 // There is no special synchronization scheme available to 287 // raise SEE exceptions. So, we will ignore that for now. 288 // Just plain writing to the MXCSR register does not guarantee 289 // the exception handler will be called. 290 291 return 0; 292 } 293 294 LIBC_INLINE int get_round() { 295 uint16_t bit_value = 296 (internal::get_mxcsr() >> internal::MXCSR_ROUNDING_CONTROL_BIT_POSITION) & 297 0x3; 298 switch (bit_value) { 299 case internal::RoundingControlValue::TO_NEAREST: 300 return FE_TONEAREST; 301 case internal::RoundingControlValue::DOWNWARD: 302 return FE_DOWNWARD; 303 case internal::RoundingControlValue::UPWARD: 304 return FE_UPWARD; 305 case internal::RoundingControlValue::TOWARD_ZERO: 306 return FE_TOWARDZERO; 307 default: 308 return -1; // Error value. 309 } 310 } 311 312 LIBC_INLINE int set_round(int mode) { 313 uint16_t bit_value; 314 switch (mode) { 315 case FE_TONEAREST: 316 bit_value = internal::RoundingControlValue::TO_NEAREST; 317 break; 318 case FE_DOWNWARD: 319 bit_value = internal::RoundingControlValue::DOWNWARD; 320 break; 321 case FE_UPWARD: 322 bit_value = internal::RoundingControlValue::UPWARD; 323 break; 324 case FE_TOWARDZERO: 325 bit_value = internal::RoundingControlValue::TOWARD_ZERO; 326 break; 327 default: 328 return 1; // To indicate failure 329 } 330 331 uint16_t x87_value = static_cast<uint16_t>( 332 bit_value << internal::X87_ROUNDING_CONTROL_BIT_POSITION); 333 uint16_t x87_control = internal::get_x87_control_word(); 334 x87_control = static_cast<uint16_t>( 335 (x87_control & 336 ~(uint16_t(0x3) << internal::X87_ROUNDING_CONTROL_BIT_POSITION)) | 337 x87_value); 338 internal::write_x87_control_word(x87_control); 339 340 uint32_t mxcsr_value = bit_value 341 << internal::MXCSR_ROUNDING_CONTROL_BIT_POSITION; 342 uint32_t mxcsr_control = internal::get_mxcsr(); 343 mxcsr_control = (mxcsr_control & 344 ~(0x3 << internal::MXCSR_ROUNDING_CONTROL_BIT_POSITION)) | 345 mxcsr_value; 346 internal::write_mxcsr(mxcsr_control); 347 348 return 0; 349 } 350 351 namespace internal { 352 353 #if defined(_WIN32) 354 // MSVC fenv.h defines a very simple representation of the floating point state 355 // which just consists of control and status words of the x87 unit. 356 struct FPState { 357 uint32_t control_word; 358 uint32_t status_word; 359 }; 360 #elif defined(__APPLE__) 361 struct FPState { 362 uint16_t control_word; 363 uint16_t status_word; 364 uint32_t mxcsr; 365 uint8_t reserved[8]; 366 }; 367 #else 368 struct FPState { 369 X87StateDescriptor x87_status; 370 uint32_t mxcsr; 371 }; 372 #endif // _WIN32 373 374 } // namespace internal 375 376 static_assert( 377 sizeof(fenv_t) == sizeof(internal::FPState), 378 "Internal floating point state does not match the public fenv_t type."); 379 380 #ifdef _WIN32 381 382 // The exception flags in the Windows FEnv struct and the MXCSR have almost 383 // reversed bit positions. 384 struct WinExceptionFlags { 385 static constexpr uint32_t INEXACT_WIN = 0x01; 386 static constexpr uint32_t UNDERFLOW_WIN = 0x02; 387 static constexpr uint32_t OVERFLOW_WIN = 0x04; 388 static constexpr uint32_t DIV_BY_ZERO_WIN = 0x08; 389 static constexpr uint32_t INVALID_WIN = 0x10; 390 static constexpr uint32_t DENORMAL_WIN = 0x20; 391 392 // The Windows FEnv struct has a second copy of all of these bits in the high 393 // byte of the 32 bit control word. These are used as the source of truth when 394 // calling fesetenv. 395 static constexpr uint32_t HIGH_OFFSET = 24; 396 397 static constexpr uint32_t HIGH_INEXACT = INEXACT_WIN << HIGH_OFFSET; 398 static constexpr uint32_t HIGH_UNDERFLOW = UNDERFLOW_WIN << HIGH_OFFSET; 399 static constexpr uint32_t HIGH_OVERFLOW = OVERFLOW_WIN << HIGH_OFFSET; 400 static constexpr uint32_t HIGH_DIV_BY_ZERO = DIV_BY_ZERO_WIN << HIGH_OFFSET; 401 static constexpr uint32_t HIGH_INVALID = INVALID_WIN << HIGH_OFFSET; 402 static constexpr uint32_t HIGH_DENORMAL = DENORMAL_WIN << HIGH_OFFSET; 403 }; 404 405 /* 406 fenv_t control word format: 407 408 Windows (at least for x64) uses a 4 byte control fenv control word stored in 409 a 32 bit integer. The first byte contains just the rounding mode and the 410 exception masks, while the last two bytes contain that same information as 411 well as the flush-to-zero and denormals-are-zero flags. The flags are 412 represented with a truth table: 413 414 00 - No flags set 415 01 - Flush-to-zero and Denormals-are-zero set 416 11 - Flush-to-zero set 417 10 - Denormals-are-zero set 418 419 U represents unused. 420 421 +-----Rounding Mode-----+ 422 | | 423 ++ ++ 424 || || 425 RRMMMMMM UUUUUUUU UUUUFFRR UUMMMMMM 426 | | || | | 427 +----+ flags---++ +----+ 428 | | 429 +------Exception Masks-----+ 430 431 432 fenv_t status word format: 433 434 The status word is a lot simpler for this conversion, since only the 435 exception flags are used in the MXCSR. 436 437 +----+---Exception Flags---+----+ 438 | | | | 439 UUEEEEEE UUUUUUUU UUUUUUUU UUEEEEEE 440 441 442 443 MXCSR Format: 444 445 The MXCSR format is the same information, just organized differently. Since 446 the fenv_t struct for windows doesn't include the mxcsr bits, they must be 447 generated from the control word bits. 448 449 Exception Masks---+ +---Exception Flags 450 | | 451 Flush-to-zero---+ +----+ +----+ 452 | | | | | 453 FRRMMMMMMDEEEEEE 454 || | 455 ++ +---Denormals-are-zero 456 | 457 +---Rounding Mode 458 459 460 The mask and flag order is as follows: 461 462 fenv_t mxcsr 463 464 denormal inexact 465 invalid underflow 466 div by 0 overflow 467 overflow div by 0 468 underflow denormal 469 inexact invalid 470 471 This is almost reverse, except for denormal and invalid which are in the 472 same order in both. 473 */ 474 475 LIBC_INLINE int get_env(fenv_t *envp) { 476 internal::FPState *state = reinterpret_cast<internal::FPState *>(envp); 477 478 uint32_t status_word = 0; 479 uint32_t control_word = 0; 480 481 uint32_t mxcsr = internal::get_mxcsr(); 482 483 // Set exception flags in the status word 484 status_word |= (mxcsr & (internal::ExceptionFlags::INVALID_F | 485 internal::ExceptionFlags::DENORMAL_F)) 486 << 4; 487 status_word |= (mxcsr & internal::ExceptionFlags::DIV_BY_ZERO_F) << 1; 488 status_word |= (mxcsr & internal::ExceptionFlags::OVERFLOW_F) >> 1; 489 status_word |= (mxcsr & internal::ExceptionFlags::UNDERFLOW_F) >> 3; 490 status_word |= (mxcsr & internal::ExceptionFlags::INEXACT_F) >> 5; 491 status_word |= status_word << WinExceptionFlags::HIGH_OFFSET; 492 493 // Set exception masks in bits 0-5 and 24-29 494 control_word |= (mxcsr & ((internal::ExceptionFlags::INVALID_F | 495 internal::ExceptionFlags::DENORMAL_F) 496 << 7)) >> 497 3; 498 control_word |= (mxcsr & (internal::ExceptionFlags::DIV_BY_ZERO_F << 7)) >> 6; 499 control_word |= (mxcsr & (internal::ExceptionFlags::OVERFLOW_F << 7)) >> 8; 500 control_word |= (mxcsr & (internal::ExceptionFlags::UNDERFLOW_F << 7)) >> 10; 501 control_word |= (mxcsr & (internal::ExceptionFlags::INEXACT_F << 7)) >> 12; 502 control_word |= control_word << WinExceptionFlags::HIGH_OFFSET; 503 504 // Set rounding in bits 8-9 and 30-31 505 control_word |= (mxcsr & 0x6000) >> 5; 506 control_word |= (mxcsr & 0x6000) << 17; 507 508 // Set flush-to-zero in bit 10 509 control_word |= (mxcsr & 0x8000) >> 5; 510 511 // Set denormals-are-zero xor flush-to-zero in bit 11 512 control_word |= (((mxcsr & 0x8000) >> 9) ^ (mxcsr & 0x0040)) << 5; 513 514 state->control_word = control_word; 515 state->status_word = status_word; 516 return 0; 517 } 518 519 LIBC_INLINE int set_env(const fenv_t *envp) { 520 const internal::FPState *state = 521 reinterpret_cast<const internal::FPState *>(envp); 522 523 uint32_t mxcsr = 0; 524 525 // Set exception flags from the status word 526 mxcsr |= static_cast<uint16_t>( 527 (state->status_word & 528 (WinExceptionFlags::HIGH_DENORMAL | WinExceptionFlags::HIGH_INVALID)) >> 529 28); 530 mxcsr |= static_cast<uint16_t>( 531 (state->status_word & WinExceptionFlags::HIGH_DIV_BY_ZERO) >> 25); 532 mxcsr |= static_cast<uint16_t>( 533 (state->status_word & WinExceptionFlags::HIGH_OVERFLOW) >> 23); 534 mxcsr |= static_cast<uint16_t>( 535 (state->status_word & WinExceptionFlags::HIGH_UNDERFLOW) >> 21); 536 mxcsr |= static_cast<uint16_t>( 537 (state->status_word & WinExceptionFlags::HIGH_INEXACT) >> 19); 538 539 // Set denormals-are-zero from bit 10 xor bit 11 540 mxcsr |= static_cast<uint16_t>( 541 (((state->control_word & 0x800) >> 1) ^ (state->control_word & 0x400)) >> 542 4); 543 544 // Set exception masks from bits 24-29 545 mxcsr |= static_cast<uint16_t>( 546 (state->control_word & 547 (WinExceptionFlags::HIGH_DENORMAL | WinExceptionFlags::HIGH_INVALID)) >> 548 21); 549 mxcsr |= static_cast<uint16_t>( 550 (state->control_word & WinExceptionFlags::HIGH_DIV_BY_ZERO) >> 18); 551 mxcsr |= static_cast<uint16_t>( 552 (state->control_word & WinExceptionFlags::HIGH_OVERFLOW) >> 16); 553 mxcsr |= static_cast<uint16_t>( 554 (state->control_word & WinExceptionFlags::HIGH_UNDERFLOW) >> 14); 555 mxcsr |= static_cast<uint16_t>( 556 (state->control_word & WinExceptionFlags::HIGH_INEXACT) >> 12); 557 558 // Set rounding from bits 30-31 559 mxcsr |= static_cast<uint16_t>((state->control_word & 0xc0000000) >> 17); 560 561 // Set flush-to-zero from bit 10 562 mxcsr |= static_cast<uint16_t>((state->control_word & 0x400) << 5); 563 564 internal::write_mxcsr(mxcsr); 565 return 0; 566 } 567 #else 568 LIBC_INLINE int get_env(fenv_t *envp) { 569 internal::FPState *state = reinterpret_cast<internal::FPState *>(envp); 570 #ifdef __APPLE__ 571 internal::X87StateDescriptor x87_status; 572 internal::get_x87_state_descriptor(x87_status); 573 state->control_word = x87_status.control_word; 574 state->status_word = x87_status.status_word; 575 #else 576 internal::get_x87_state_descriptor(state->x87_status); 577 #endif // __APPLE__ 578 state->mxcsr = internal::get_mxcsr(); 579 return 0; 580 } 581 582 LIBC_INLINE int set_env(const fenv_t *envp) { 583 // envp contains everything including pieces like the current 584 // top of FPU stack. We cannot arbitrarily change them. So, we first 585 // read the current status and update only those pieces which are 586 // not disruptive. 587 internal::X87StateDescriptor x87_status; 588 internal::get_x87_state_descriptor(x87_status); 589 590 if (envp == FE_DFL_ENV) { 591 // Reset the exception flags in the status word. 592 x87_status.status_word &= ~uint16_t(0x3F); 593 // Reset other non-sensitive parts of the status word. 594 for (int i = 0; i < 5; i++) 595 x87_status._[i] = 0; 596 // In the control word, we do the following: 597 // 1. Mask all exceptions 598 // 2. Set rounding mode to round-to-nearest 599 // 3. Set the internal precision to double extended precision. 600 x87_status.control_word |= uint16_t(0x3F); // Mask all exceptions. 601 x87_status.control_word &= ~(uint16_t(0x3) << 10); // Round to nearest. 602 x87_status.control_word |= (uint16_t(0x3) << 8); // Extended precision. 603 internal::write_x87_state_descriptor(x87_status); 604 605 // We take the exact same approach MXCSR register as well. 606 // MXCSR has two additional fields, "flush-to-zero" and 607 // "denormals-are-zero". We reset those bits. Also, MXCSR does not 608 // have a field which controls the precision of internal operations. 609 uint32_t mxcsr = internal::get_mxcsr(); 610 mxcsr &= ~uint16_t(0x3F); // Clear exception flags. 611 mxcsr &= ~(uint16_t(0x1) << 6); // Reset denormals-are-zero 612 mxcsr |= (uint16_t(0x3F) << 7); // Mask exceptions 613 mxcsr &= ~(uint16_t(0x3) << 13); // Round to nearest. 614 mxcsr &= ~(uint16_t(0x1) << 15); // Reset flush-to-zero 615 internal::write_mxcsr(mxcsr); 616 617 return 0; 618 } 619 620 const internal::FPState *fpstate = 621 reinterpret_cast<const internal::FPState *>(envp); 622 623 // Copy the exception status flags from envp. 624 x87_status.status_word &= ~uint16_t(0x3F); 625 #ifdef __APPLE__ 626 x87_status.status_word |= (fpstate->status_word & 0x3F); 627 // We can set the x87 control word as is as there no sensitive bits. 628 x87_status.control_word = fpstate->control_word; 629 #else 630 x87_status.status_word |= (fpstate->x87_status.status_word & 0x3F); 631 // Copy other non-sensitive parts of the status word. 632 for (int i = 0; i < 5; i++) 633 x87_status._[i] = fpstate->x87_status._[i]; 634 // We can set the x87 control word as is as there no sensitive bits. 635 x87_status.control_word = fpstate->x87_status.control_word; 636 #endif // __APPLE__ 637 internal::write_x87_state_descriptor(x87_status); 638 639 // We can write the MXCSR state as is as there are no sensitive bits. 640 internal::write_mxcsr(fpstate->mxcsr); 641 return 0; 642 } 643 #endif 644 645 } // namespace fputil 646 } // namespace LIBC_NAMESPACE_DECL 647 648 #endif // LLVM_LIBC_SRC___SUPPORT_FPUTIL_X86_64_FENVIMPL_H 649