1 /* $NetBSD: wzero3_machdep.c,v 1.2 2011/06/23 12:40:32 nonaka Exp $ */
2
3 /*
4 * Copyright (c) 1994-1998 Mark Brinicombe.
5 * Copyright (c) 1994 Brini.
6 * All rights reserved.
7 *
8 * This code is derived from software written for Brini by Mark Brinicombe
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by Brini.
21 * 4. The name of the company nor the name of the author may be used to
22 * endorse or promote products derived from this software without specific
23 * prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 */
37
38 #include <sys/cdefs.h>
39 __KERNEL_RCSID(0, "$NetBSD: wzero3_machdep.c,v 1.2 2011/06/23 12:40:32 nonaka Exp $");
40
41 #include <sys/systm.h>
42 #include <sys/param.h>
43 #include <sys/termios.h>
44
45 #include <uvm/uvm.h>
46
47 #include <machine/bootconfig.h>
48 #include <machine/bootinfo.h>
49 #include <machine/platid.h>
50 #include <machine/platid_mask.h>
51
52 #include <arm/xscale/pxa2x0reg.h>
53 #include <arm/xscale/pxa2x0var.h>
54 #include <arm/xscale/pxa2x0_gpio.h>
55
56 #include "com.h"
57 #if (NCOM > 0)
58 #include "opt_com.h"
59 #include <dev/ic/comvar.h>
60 #endif /* NCOM > 0 */
61 #include "lcd.h"
62 #include "wzero3lcd.h"
63
64 #if (NCOM > 0) && defined(COM_PXA2X0)
65 #ifndef CONSPEED
66 #define CONSPEED 9600
67 #endif
68 #ifndef CONMODE
69 #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */
70 #endif
71
72 int comcnspeed = CONSPEED;
73 int comcnmode = CONMODE;
74
75 #if defined(HWUARTCONSOLE)
76 #define CONADDR PXA2X0_HWUART_BASE
77 #elsif defined(BTUARTCONSOLE)
78 #define CONADDR PXA2X0_BTUART_BASE
79 #elsif defined(STUARTCONSOLE)
80 #define CONADDR PXA2X0_STUART_BASE
81 #else
82 #define CONADDR PXA2X0_FFUART_BASE
83 #endif
84
85 bus_addr_t comcnaddr = CONADDR;
86 #endif /* NCOM > 0 && COM_PXA2X0 */
87
88 const struct pmap_devmap machdep_devmap[] = { { 0, 0, 0, 0, 0, } };
89
90 void pxa2x0_machdep_init(void);
91
92
93 static void
ws003sh_cpu_reset(void)94 ws003sh_cpu_reset(void)
95 {
96 uint32_t rv;
97
98 rv = pxa2x0_memctl_read(MEMCTL_MSC0);
99 if ((rv & 0xffff0000) == 0x7ff00000) {
100 pxa2x0_memctl_write(MEMCTL_MSC0, (rv & 0xffff) | 0x7ee00000);
101 }
102
103 pxa2x0_gpio_set_function(89, GPIO_OUT | GPIO_SET);
104 for (;;)
105 continue;
106 }
107
108 static struct pxa2x0_gpioconf ws003sh_boarddep_gpioconf[] = {
109 /* FFUART */
110 { 98, GPIO_ALT_FN_3_OUT }, /* FFRTS */
111 { 99, GPIO_ALT_FN_3_OUT }, /* FFTXD */
112 /* SSP3 */
113 { 34, GPIO_ALT_FN_3_OUT }, /* SSPSCLK3 */
114 { 38, GPIO_ALT_FN_1_OUT }, /* SSPTXD3 */
115 { 82, GPIO_ALT_FN_1_IN }, /* SSPRXD3 */
116
117 { -1 }
118 };
119
120 static struct pxa2x0_gpioconf ws007sh_boarddep_gpioconf[] = {
121 /* FFUART */
122 { 98, GPIO_ALT_FN_3_OUT }, /* FFRTS */
123 { 99, GPIO_ALT_FN_3_OUT }, /* FFTXD */
124 /* SSP2 */
125 { 19, GPIO_ALT_FN_1_OUT }, /* SSPSCLK2 */
126 { 86, GPIO_ALT_FN_1_IN }, /* SSPRXD2 */
127 { 87, GPIO_ALT_FN_1_OUT }, /* SSPTXD2 */
128 /* SSP3 */
129 { 38, GPIO_ALT_FN_1_OUT }, /* SSPTXD3 */
130 { 52, GPIO_ALT_FN_2_OUT }, /* SSPSCLK3 */
131 { 89, GPIO_ALT_FN_1_IN }, /* SSPRXD3 */
132
133 { -1 }
134 };
135
136 static struct pxa2x0_gpioconf ws011sh_boarddep_gpioconf[] = {
137 /* FFUART */
138 { 98, GPIO_ALT_FN_3_OUT }, /* FFRTS */
139 { 99, GPIO_ALT_FN_3_OUT }, /* FFTXD */
140 /* SSP2 */
141 { 19, GPIO_ALT_FN_1_OUT }, /* SSPSCLK2 */
142 { 86, GPIO_ALT_FN_1_IN }, /* SSPRXD2 */
143 { 87, GPIO_ALT_FN_1_OUT }, /* SSPTXD2 */
144
145 { -1 }
146 };
147
148 static struct pxa2x0_gpioconf *ws003sh_gpioconf[] = {
149 pxa27x_com_ffuart_gpioconf,
150 pxa27x_pxamci_gpioconf,
151 pxa27x_ohci_gpioconf,
152 ws003sh_boarddep_gpioconf,
153 NULL
154 };
155
156 static struct pxa2x0_gpioconf *ws007sh_gpioconf[] = {
157 pxa27x_com_ffuart_gpioconf,
158 pxa27x_pxamci_gpioconf,
159 pxa27x_ohci_gpioconf,
160 ws007sh_boarddep_gpioconf,
161 NULL
162 };
163
164 static struct pxa2x0_gpioconf *ws011sh_gpioconf[] = {
165 pxa27x_com_ffuart_gpioconf,
166 pxa27x_pxamci_gpioconf,
167 pxa27x_ohci_gpioconf,
168 ws011sh_boarddep_gpioconf,
169 NULL
170 };
171
172 void
pxa2x0_machdep_init(void)173 pxa2x0_machdep_init(void)
174 {
175 extern void (*__cpu_reset)(void);
176 extern BootConfig bootconfig; /* Boot config storage */
177
178 if (platid_match(&platid, &platid_mask_MACH_SHARP_WZERO3_WS003SH)
179 || platid_match(&platid, &platid_mask_MACH_SHARP_WZERO3_WS004SH)) {
180 pxa2x0_gpio_config(ws003sh_gpioconf);
181 __cpu_reset = ws003sh_cpu_reset;
182 } else if (platid_match(&platid, &platid_mask_MACH_SHARP_WZERO3_WS007SH)) {
183 pxa2x0_gpio_config(ws007sh_gpioconf);
184 } else if (platid_match(&platid, &platid_mask_MACH_SHARP_WZERO3_WS011SH)) {
185 pxa2x0_gpio_config(ws011sh_gpioconf);
186 }
187 pxa2x0_clkman_config(CKEN_FFUART, 1);
188 pxa2x0_clkman_config(CKEN_OST, 1);
189 pxa2x0_clkman_config(CKEN_USBHC, 0);
190 pxa2x0_clkman_config(CKEN_USBDC, 0);
191 pxa2x0_clkman_config(CKEN_AC97, 0);
192 pxa2x0_clkman_config(CKEN_SSP, 0);
193 pxa2x0_clkman_config(CKEN_HWUART, 0);
194 pxa2x0_clkman_config(CKEN_STUART, 0);
195 pxa2x0_clkman_config(CKEN_BTUART, 0);
196 pxa2x0_clkman_config(CKEN_I2S, 0);
197 pxa2x0_clkman_config(CKEN_MMC, 0);
198 pxa2x0_clkman_config(CKEN_FICP, 0);
199 pxa2x0_clkman_config(CKEN_I2C, 0);
200 pxa2x0_clkman_config(CKEN_PWM1, 0);
201 if (!platid_match(&platid, &platid_mask_MACH_SHARP_WZERO3_WS011SH)) {
202 pxa2x0_clkman_config(CKEN_PWM0, 0); /* WS011SH: DON'T DISABLE */
203 }
204
205 if (platid_match(&platid, &platid_mask_MACH_SHARP_WZERO3_WS003SH)
206 || platid_match(&platid, &platid_mask_MACH_SHARP_WZERO3_WS004SH)
207 || platid_match(&platid, &platid_mask_MACH_SHARP_WZERO3_WS007SH)) {
208 bootconfig.dram[0].pages = 16384; /* 64MiB */
209 } else
210 if (platid_match(&platid, &platid_mask_MACH_SHARP_WZERO3_WS011SH)
211 || platid_match(&platid, &platid_mask_MACH_SHARP_WZERO3_WS020SH)) {
212 bootconfig.dram[0].pages = 32768; /* 128MiB */
213 }
214 }
215
216 void
consinit(void)217 consinit(void)
218 {
219 static int consinit_called = 0;
220
221 if (consinit_called != 0)
222 return;
223
224 consinit_called = 1;
225
226 if (bootinfo->bi_cnuse == BI_CNUSE_SERIAL) {
227 #if (NCOM > 0) && defined(COM_PXA2X0)
228 comcnattach(&pxa2x0_a4x_bs_tag, comcnaddr, comcnspeed,
229 PXA2X0_COM_FREQ, COM_TYPE_PXA2x0, comcnmode);
230 #endif
231 } else {
232 #if (NLCD > 0)
233 #if NWZERO3LCD > 0
234 extern void wzero3lcd_cnattach(void);
235 wzero3lcd_cnattach();
236 return;
237 #endif
238 #endif
239 }
240 }
241