1 /* $NetBSD: vcn_v2_0.h,v 1.2 2021/12/18 23:44:59 riastradh Exp $ */ 2 3 /* 4 * Copyright 2018 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #ifndef __VCN_V2_0_H__ 27 #define __VCN_V2_0_H__ 28 29 extern void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring); 30 extern void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring); 31 extern void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); 32 extern void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 33 unsigned flags); 34 extern void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job, 35 struct amdgpu_ib *ib, uint32_t flags); 36 extern void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 37 uint32_t val, uint32_t mask); 38 extern void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 39 unsigned vmid, uint64_t pd_addr); 40 extern void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, 41 uint32_t reg, uint32_t val); 42 extern int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring); 43 44 extern void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring); 45 extern void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 46 u64 seq, unsigned flags); 47 extern void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job, 48 struct amdgpu_ib *ib, uint32_t flags); 49 extern void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 50 uint32_t val, uint32_t mask); 51 extern void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 52 unsigned int vmid, uint64_t pd_addr); 53 extern void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val); 54 55 extern const struct amdgpu_ip_block_version vcn_v2_0_ip_block; 56 57 #endif /* __VCN_V2_0_H__ */ 58