1 /* $NetBSD: vcn_2_0_0_sh_mask.h,v 1.2 2021/12/18 23:45:24 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2019 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef _vcn_2_0_0_SH_MASK_HEADER 24 #define _vcn_2_0_0_SH_MASK_HEADER 25 26 27 // addressBlock: uvd0_mmsch_dec 28 //MMSCH_UCODE_ADDR 29 #define MMSCH_UCODE_ADDR__UCODE_ADDR__SHIFT 0x2 30 #define MMSCH_UCODE_ADDR__UCODE_LOCK__SHIFT 0x1f 31 #define MMSCH_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFCL 32 #define MMSCH_UCODE_ADDR__UCODE_LOCK_MASK 0x80000000L 33 //MMSCH_UCODE_DATA 34 #define MMSCH_UCODE_DATA__UCODE_DATA__SHIFT 0x0 35 #define MMSCH_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL 36 //MMSCH_SRAM_ADDR 37 #define MMSCH_SRAM_ADDR__SRAM_ADDR__SHIFT 0x2 38 #define MMSCH_SRAM_ADDR__SRAM_LOCK__SHIFT 0x1f 39 #define MMSCH_SRAM_ADDR__SRAM_ADDR_MASK 0x00001FFCL 40 #define MMSCH_SRAM_ADDR__SRAM_LOCK_MASK 0x80000000L 41 //MMSCH_SRAM_DATA 42 #define MMSCH_SRAM_DATA__SRAM_DATA__SHIFT 0x0 43 #define MMSCH_SRAM_DATA__SRAM_DATA_MASK 0xFFFFFFFFL 44 //MMSCH_VF_SRAM_OFFSET 45 #define MMSCH_VF_SRAM_OFFSET__VF_SRAM_OFFSET__SHIFT 0x2 46 #define MMSCH_VF_SRAM_OFFSET__VF_SRAM_NUM_DW_PER_VF__SHIFT 0x10 47 #define MMSCH_VF_SRAM_OFFSET__VF_SRAM_OFFSET_MASK 0x00001FFCL 48 #define MMSCH_VF_SRAM_OFFSET__VF_SRAM_NUM_DW_PER_VF_MASK 0x00FF0000L 49 //MMSCH_DB_SRAM_OFFSET 50 #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_OFFSET__SHIFT 0x2 51 #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_ENG__SHIFT 0x10 52 #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_RING_PER_ENG__SHIFT 0x18 53 #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_OFFSET_MASK 0x00001FFCL 54 #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_ENG_MASK 0x00FF0000L 55 #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_RING_PER_ENG_MASK 0xFF000000L 56 //MMSCH_CTX_SRAM_OFFSET 57 #define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_OFFSET__SHIFT 0x2 58 #define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_SIZE__SHIFT 0x10 59 #define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_OFFSET_MASK 0x00001FFCL 60 #define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_SIZE_MASK 0xFFFF0000L 61 //MMSCH_CTL 62 #define MMSCH_CTL__P_RUNSTALL__SHIFT 0x0 63 #define MMSCH_CTL__P_RESET__SHIFT 0x1 64 #define MMSCH_CTL__VFID_FIFO_EN__SHIFT 0x4 65 #define MMSCH_CTL__P_LOCK__SHIFT 0x1f 66 #define MMSCH_CTL__P_RUNSTALL_MASK 0x00000001L 67 #define MMSCH_CTL__P_RESET_MASK 0x00000002L 68 #define MMSCH_CTL__VFID_FIFO_EN_MASK 0x00000010L 69 #define MMSCH_CTL__P_LOCK_MASK 0x80000000L 70 //MMSCH_INTR 71 #define MMSCH_INTR__INTR__SHIFT 0x0 72 #define MMSCH_INTR__INTR_MASK 0x00001FFFL 73 //MMSCH_INTR_ACK 74 #define MMSCH_INTR_ACK__INTR__SHIFT 0x0 75 #define MMSCH_INTR_ACK__INTR_MASK 0x00001FFFL 76 //MMSCH_INTR_STATUS 77 #define MMSCH_INTR_STATUS__INTR__SHIFT 0x0 78 #define MMSCH_INTR_STATUS__INTR_MASK 0x00001FFFL 79 //MMSCH_VF_VMID 80 #define MMSCH_VF_VMID__VF_CTX_VMID__SHIFT 0x0 81 #define MMSCH_VF_VMID__VF_GPCOM_VMID__SHIFT 0x5 82 #define MMSCH_VF_VMID__VF_CTX_VMID_MASK 0x0000001FL 83 #define MMSCH_VF_VMID__VF_GPCOM_VMID_MASK 0x000003E0L 84 //MMSCH_VF_CTX_ADDR_LO 85 #define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO__SHIFT 0x6 86 #define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO_MASK 0xFFFFFFC0L 87 //MMSCH_VF_CTX_ADDR_HI 88 #define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI__SHIFT 0x0 89 #define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI_MASK 0xFFFFFFFFL 90 //MMSCH_VF_CTX_SIZE 91 #define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE__SHIFT 0x0 92 #define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE_MASK 0xFFFFFFFFL 93 //MMSCH_VF_GPCOM_ADDR_LO 94 #define MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO__SHIFT 0x6 95 #define MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO_MASK 0xFFFFFFC0L 96 //MMSCH_VF_GPCOM_ADDR_HI 97 #define MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI__SHIFT 0x0 98 #define MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI_MASK 0xFFFFFFFFL 99 //MMSCH_VF_GPCOM_SIZE 100 #define MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE__SHIFT 0x0 101 #define MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE_MASK 0xFFFFFFFFL 102 //MMSCH_VF_MAILBOX_HOST 103 #define MMSCH_VF_MAILBOX_HOST__DATA__SHIFT 0x0 104 #define MMSCH_VF_MAILBOX_HOST__DATA_MASK 0xFFFFFFFFL 105 //MMSCH_VF_MAILBOX_RESP 106 #define MMSCH_VF_MAILBOX_RESP__RESP__SHIFT 0x0 107 #define MMSCH_VF_MAILBOX_RESP__RESP_MASK 0xFFFFFFFFL 108 //MMSCH_VF_MAILBOX_0 109 #define MMSCH_VF_MAILBOX_0__DATA__SHIFT 0x0 110 #define MMSCH_VF_MAILBOX_0__DATA_MASK 0xFFFFFFFFL 111 //MMSCH_VF_MAILBOX_0_RESP 112 #define MMSCH_VF_MAILBOX_0_RESP__RESP__SHIFT 0x0 113 #define MMSCH_VF_MAILBOX_0_RESP__RESP_MASK 0xFFFFFFFFL 114 //MMSCH_VF_MAILBOX_1 115 #define MMSCH_VF_MAILBOX_1__DATA__SHIFT 0x0 116 #define MMSCH_VF_MAILBOX_1__DATA_MASK 0xFFFFFFFFL 117 //MMSCH_VF_MAILBOX_1_RESP 118 #define MMSCH_VF_MAILBOX_1_RESP__RESP__SHIFT 0x0 119 #define MMSCH_VF_MAILBOX_1_RESP__RESP_MASK 0xFFFFFFFFL 120 //MMSCH_CNTL 121 #define MMSCH_CNTL__CLK_EN__SHIFT 0x0 122 #define MMSCH_CNTL__ED_ENABLE__SHIFT 0x1 123 #define MMSCH_CNTL__MMSCH_IRQ_ERR__SHIFT 0x5 124 #define MMSCH_CNTL__MMSCH_NACK_INTR_EN__SHIFT 0x9 125 #define MMSCH_CNTL__MMSCH_DB_BUSY_INTR_EN__SHIFT 0xa 126 #define MMSCH_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 127 #define MMSCH_CNTL__TIMEOUT_DIS__SHIFT 0x1c 128 #define MMSCH_CNTL__CLK_EN_MASK 0x00000001L 129 #define MMSCH_CNTL__ED_ENABLE_MASK 0x00000002L 130 #define MMSCH_CNTL__MMSCH_IRQ_ERR_MASK 0x000001E0L 131 #define MMSCH_CNTL__MMSCH_NACK_INTR_EN_MASK 0x00000200L 132 #define MMSCH_CNTL__MMSCH_DB_BUSY_INTR_EN_MASK 0x00000400L 133 #define MMSCH_CNTL__PRB_TIMEOUT_VAL_MASK 0x0FF00000L 134 #define MMSCH_CNTL__TIMEOUT_DIS_MASK 0x10000000L 135 //MMSCH_NONCACHE_OFFSET0 136 #define MMSCH_NONCACHE_OFFSET0__OFFSET__SHIFT 0x0 137 #define MMSCH_NONCACHE_OFFSET0__OFFSET_MASK 0x0FFFFFFFL 138 //MMSCH_NONCACHE_SIZE0 139 #define MMSCH_NONCACHE_SIZE0__SIZE__SHIFT 0x0 140 #define MMSCH_NONCACHE_SIZE0__SIZE_MASK 0x00FFFFFFL 141 //MMSCH_NONCACHE_OFFSET1 142 #define MMSCH_NONCACHE_OFFSET1__OFFSET__SHIFT 0x0 143 #define MMSCH_NONCACHE_OFFSET1__OFFSET_MASK 0x0FFFFFFFL 144 //MMSCH_NONCACHE_SIZE1 145 #define MMSCH_NONCACHE_SIZE1__SIZE__SHIFT 0x0 146 #define MMSCH_NONCACHE_SIZE1__SIZE_MASK 0x00FFFFFFL 147 //MMSCH_PROC_STATE1 148 #define MMSCH_PROC_STATE1__PC__SHIFT 0x0 149 #define MMSCH_PROC_STATE1__PC_MASK 0xFFFFFFFFL 150 //MMSCH_LAST_MC_ADDR 151 #define MMSCH_LAST_MC_ADDR__MC_ADDR__SHIFT 0x0 152 #define MMSCH_LAST_MC_ADDR__RW__SHIFT 0x1f 153 #define MMSCH_LAST_MC_ADDR__MC_ADDR_MASK 0x0FFFFFFFL 154 #define MMSCH_LAST_MC_ADDR__RW_MASK 0x80000000L 155 //MMSCH_LAST_MEM_ACCESS_HI 156 #define MMSCH_LAST_MEM_ACCESS_HI__PROC_CMD__SHIFT 0x0 157 #define MMSCH_LAST_MEM_ACCESS_HI__FIFO_RPTR__SHIFT 0x8 158 #define MMSCH_LAST_MEM_ACCESS_HI__FIFO_WPTR__SHIFT 0xc 159 #define MMSCH_LAST_MEM_ACCESS_HI__PROC_CMD_MASK 0x00000007L 160 #define MMSCH_LAST_MEM_ACCESS_HI__FIFO_RPTR_MASK 0x00000700L 161 #define MMSCH_LAST_MEM_ACCESS_HI__FIFO_WPTR_MASK 0x00007000L 162 //MMSCH_LAST_MEM_ACCESS_LO 163 #define MMSCH_LAST_MEM_ACCESS_LO__PROC_ADDR__SHIFT 0x0 164 #define MMSCH_LAST_MEM_ACCESS_LO__PROC_ADDR_MASK 0xFFFFFFFFL 165 //MMSCH_IOV_ACTIVE_FCN_ID 166 #define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_VF_ID__SHIFT 0x0 167 #define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_PF_VF__SHIFT 0x1f 168 #define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_VF_ID_MASK 0x0000001FL 169 #define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_PF_VF_MASK 0x80000000L 170 //MMSCH_SCRATCH_0 171 #define MMSCH_SCRATCH_0__SCRATCH_0__SHIFT 0x0 172 #define MMSCH_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL 173 //MMSCH_SCRATCH_1 174 #define MMSCH_SCRATCH_1__SCRATCH_1__SHIFT 0x0 175 #define MMSCH_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL 176 //MMSCH_GPUIOV_SCH_BLOCK_0 177 #define MMSCH_GPUIOV_SCH_BLOCK_0__ID__SHIFT 0x0 178 #define MMSCH_GPUIOV_SCH_BLOCK_0__VERSION__SHIFT 0x4 179 #define MMSCH_GPUIOV_SCH_BLOCK_0__SIZE__SHIFT 0x8 180 #define MMSCH_GPUIOV_SCH_BLOCK_0__ID_MASK 0x0000000FL 181 #define MMSCH_GPUIOV_SCH_BLOCK_0__VERSION_MASK 0x000000F0L 182 #define MMSCH_GPUIOV_SCH_BLOCK_0__SIZE_MASK 0x0000FF00L 183 //MMSCH_GPUIOV_CMD_CONTROL_0 184 #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_TYPE__SHIFT 0x0 185 #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE__SHIFT 0x4 186 #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_INTR_EN__SHIFT 0x5 187 #define MMSCH_GPUIOV_CMD_CONTROL_0__VM_BUSY_INTR_EN__SHIFT 0x6 188 #define MMSCH_GPUIOV_CMD_CONTROL_0__FUNCTINO_ID__SHIFT 0x8 189 #define MMSCH_GPUIOV_CMD_CONTROL_0__NEXT_FUNCTINO_ID__SHIFT 0x10 190 #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_TYPE_MASK 0x0000000FL 191 #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_MASK 0x00000010L 192 #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_INTR_EN_MASK 0x00000020L 193 #define MMSCH_GPUIOV_CMD_CONTROL_0__VM_BUSY_INTR_EN_MASK 0x00000040L 194 #define MMSCH_GPUIOV_CMD_CONTROL_0__FUNCTINO_ID_MASK 0x0000FF00L 195 #define MMSCH_GPUIOV_CMD_CONTROL_0__NEXT_FUNCTINO_ID_MASK 0x00FF0000L 196 //MMSCH_GPUIOV_CMD_STATUS_0 197 #define MMSCH_GPUIOV_CMD_STATUS_0__CMD_STATUS__SHIFT 0x0 198 #define MMSCH_GPUIOV_CMD_STATUS_0__CMD_STATUS_MASK 0x0000000FL 199 //MMSCH_GPUIOV_VM_BUSY_STATUS_0 200 #define MMSCH_GPUIOV_VM_BUSY_STATUS_0__BUSY__SHIFT 0x0 201 #define MMSCH_GPUIOV_VM_BUSY_STATUS_0__BUSY_MASK 0xFFFFFFFFL 202 //MMSCH_GPUIOV_ACTIVE_FCNS_0 203 #define MMSCH_GPUIOV_ACTIVE_FCNS_0__ACTIVE_FCNS__SHIFT 0x0 204 #define MMSCH_GPUIOV_ACTIVE_FCNS_0__ACTIVE_FCNS_MASK 0xFFFFFFFFL 205 //MMSCH_GPUIOV_ACTIVE_FCN_ID_0 206 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID__SHIFT 0x0 207 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_STATUS__SHIFT 0x8 208 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_MASK 0x000000FFL 209 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_STATUS_MASK 0x00000F00L 210 //MMSCH_GPUIOV_DW6_0 211 #define MMSCH_GPUIOV_DW6_0__DATA__SHIFT 0x0 212 #define MMSCH_GPUIOV_DW6_0__DATA_MASK 0xFFFFFFFFL 213 //MMSCH_GPUIOV_DW7_0 214 #define MMSCH_GPUIOV_DW7_0__DATA__SHIFT 0x0 215 #define MMSCH_GPUIOV_DW7_0__DATA_MASK 0xFFFFFFFFL 216 //MMSCH_GPUIOV_DW8_0 217 #define MMSCH_GPUIOV_DW8_0__DATA__SHIFT 0x0 218 #define MMSCH_GPUIOV_DW8_0__DATA_MASK 0xFFFFFFFFL 219 //MMSCH_GPUIOV_SCH_BLOCK_1 220 #define MMSCH_GPUIOV_SCH_BLOCK_1__ID__SHIFT 0x0 221 #define MMSCH_GPUIOV_SCH_BLOCK_1__VERSION__SHIFT 0x4 222 #define MMSCH_GPUIOV_SCH_BLOCK_1__SIZE__SHIFT 0x8 223 #define MMSCH_GPUIOV_SCH_BLOCK_1__ID_MASK 0x0000000FL 224 #define MMSCH_GPUIOV_SCH_BLOCK_1__VERSION_MASK 0x000000F0L 225 #define MMSCH_GPUIOV_SCH_BLOCK_1__SIZE_MASK 0x0000FF00L 226 //MMSCH_GPUIOV_CMD_CONTROL_1 227 #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_TYPE__SHIFT 0x0 228 #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE__SHIFT 0x4 229 #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_INTR_EN__SHIFT 0x5 230 #define MMSCH_GPUIOV_CMD_CONTROL_1__VM_BUSY_INTR_EN__SHIFT 0x6 231 #define MMSCH_GPUIOV_CMD_CONTROL_1__FUNCTINO_ID__SHIFT 0x8 232 #define MMSCH_GPUIOV_CMD_CONTROL_1__NEXT_FUNCTINO_ID__SHIFT 0x10 233 #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_TYPE_MASK 0x0000000FL 234 #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_MASK 0x00000010L 235 #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_INTR_EN_MASK 0x00000020L 236 #define MMSCH_GPUIOV_CMD_CONTROL_1__VM_BUSY_INTR_EN_MASK 0x00000040L 237 #define MMSCH_GPUIOV_CMD_CONTROL_1__FUNCTINO_ID_MASK 0x0000FF00L 238 #define MMSCH_GPUIOV_CMD_CONTROL_1__NEXT_FUNCTINO_ID_MASK 0x00FF0000L 239 //MMSCH_GPUIOV_CMD_STATUS_1 240 #define MMSCH_GPUIOV_CMD_STATUS_1__CMD_STATUS__SHIFT 0x0 241 #define MMSCH_GPUIOV_CMD_STATUS_1__CMD_STATUS_MASK 0x0000000FL 242 //MMSCH_GPUIOV_VM_BUSY_STATUS_1 243 #define MMSCH_GPUIOV_VM_BUSY_STATUS_1__BUSY__SHIFT 0x0 244 #define MMSCH_GPUIOV_VM_BUSY_STATUS_1__BUSY_MASK 0xFFFFFFFFL 245 //MMSCH_GPUIOV_ACTIVE_FCNS_1 246 #define MMSCH_GPUIOV_ACTIVE_FCNS_1__ACTIVE_FCNS__SHIFT 0x0 247 #define MMSCH_GPUIOV_ACTIVE_FCNS_1__ACTIVE_FCNS_MASK 0xFFFFFFFFL 248 //MMSCH_GPUIOV_ACTIVE_FCN_ID_1 249 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID__SHIFT 0x0 250 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_STATUS__SHIFT 0x8 251 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_MASK 0x000000FFL 252 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_STATUS_MASK 0x00000F00L 253 //MMSCH_GPUIOV_DW6_1 254 #define MMSCH_GPUIOV_DW6_1__DATA__SHIFT 0x0 255 #define MMSCH_GPUIOV_DW6_1__DATA_MASK 0xFFFFFFFFL 256 //MMSCH_GPUIOV_DW7_1 257 #define MMSCH_GPUIOV_DW7_1__DATA__SHIFT 0x0 258 #define MMSCH_GPUIOV_DW7_1__DATA_MASK 0xFFFFFFFFL 259 //MMSCH_GPUIOV_DW8_1 260 #define MMSCH_GPUIOV_DW8_1__DATA__SHIFT 0x0 261 #define MMSCH_GPUIOV_DW8_1__DATA_MASK 0xFFFFFFFFL 262 //MMSCH_GPUIOV_CNTXT 263 #define MMSCH_GPUIOV_CNTXT__CNTXT_SIZE__SHIFT 0x0 264 #define MMSCH_GPUIOV_CNTXT__CNTXT_LOCATION__SHIFT 0x7 265 #define MMSCH_GPUIOV_CNTXT__CNTXT_OFFSET__SHIFT 0xa 266 #define MMSCH_GPUIOV_CNTXT__CNTXT_SIZE_MASK 0x0000007FL 267 #define MMSCH_GPUIOV_CNTXT__CNTXT_LOCATION_MASK 0x00000080L 268 #define MMSCH_GPUIOV_CNTXT__CNTXT_OFFSET_MASK 0xFFFFFC00L 269 //MMSCH_SCRATCH_2 270 #define MMSCH_SCRATCH_2__SCRATCH_2__SHIFT 0x0 271 #define MMSCH_SCRATCH_2__SCRATCH_2_MASK 0xFFFFFFFFL 272 //MMSCH_SCRATCH_3 273 #define MMSCH_SCRATCH_3__SCRATCH_3__SHIFT 0x0 274 #define MMSCH_SCRATCH_3__SCRATCH_3_MASK 0xFFFFFFFFL 275 //MMSCH_SCRATCH_4 276 #define MMSCH_SCRATCH_4__SCRATCH_4__SHIFT 0x0 277 #define MMSCH_SCRATCH_4__SCRATCH_4_MASK 0xFFFFFFFFL 278 //MMSCH_SCRATCH_5 279 #define MMSCH_SCRATCH_5__SCRATCH_5__SHIFT 0x0 280 #define MMSCH_SCRATCH_5__SCRATCH_5_MASK 0xFFFFFFFFL 281 //MMSCH_SCRATCH_6 282 #define MMSCH_SCRATCH_6__SCRATCH_6__SHIFT 0x0 283 #define MMSCH_SCRATCH_6__SCRATCH_6_MASK 0xFFFFFFFFL 284 //MMSCH_SCRATCH_7 285 #define MMSCH_SCRATCH_7__SCRATCH_7__SHIFT 0x0 286 #define MMSCH_SCRATCH_7__SCRATCH_7_MASK 0xFFFFFFFFL 287 //MMSCH_VFID_FIFO_HEAD_0 288 #define MMSCH_VFID_FIFO_HEAD_0__HEAD__SHIFT 0x0 289 #define MMSCH_VFID_FIFO_HEAD_0__HEAD_MASK 0x0000003FL 290 //MMSCH_VFID_FIFO_TAIL_0 291 #define MMSCH_VFID_FIFO_TAIL_0__TAIL__SHIFT 0x0 292 #define MMSCH_VFID_FIFO_TAIL_0__TAIL_MASK 0x0000003FL 293 //MMSCH_VFID_FIFO_HEAD_1 294 #define MMSCH_VFID_FIFO_HEAD_1__HEAD__SHIFT 0x0 295 #define MMSCH_VFID_FIFO_HEAD_1__HEAD_MASK 0x0000003FL 296 //MMSCH_VFID_FIFO_TAIL_1 297 #define MMSCH_VFID_FIFO_TAIL_1__TAIL__SHIFT 0x0 298 #define MMSCH_VFID_FIFO_TAIL_1__TAIL_MASK 0x0000003FL 299 //MMSCH_NACK_STATUS 300 #define MMSCH_NACK_STATUS__WR_NACK_STATUS__SHIFT 0x0 301 #define MMSCH_NACK_STATUS__RD_NACK_STATUS__SHIFT 0x2 302 #define MMSCH_NACK_STATUS__WR_NACK_STATUS_MASK 0x00000003L 303 #define MMSCH_NACK_STATUS__RD_NACK_STATUS_MASK 0x0000000CL 304 //MMSCH_VF_MAILBOX0_DATA 305 #define MMSCH_VF_MAILBOX0_DATA__DATA__SHIFT 0x0 306 #define MMSCH_VF_MAILBOX0_DATA__DATA_MASK 0xFFFFFFFFL 307 //MMSCH_VF_MAILBOX1_DATA 308 #define MMSCH_VF_MAILBOX1_DATA__DATA__SHIFT 0x0 309 #define MMSCH_VF_MAILBOX1_DATA__DATA_MASK 0xFFFFFFFFL 310 //MMSCH_GPUIOV_SCH_BLOCK_IP_0 311 #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__ID__SHIFT 0x0 312 #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__VERSION__SHIFT 0x4 313 #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__SIZE__SHIFT 0x8 314 #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__ID_MASK 0x0000000FL 315 #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__VERSION_MASK 0x000000F0L 316 #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__SIZE_MASK 0x0000FF00L 317 //MMSCH_GPUIOV_CMD_STATUS_IP_0 318 #define MMSCH_GPUIOV_CMD_STATUS_IP_0__CMD_STATUS__SHIFT 0x0 319 #define MMSCH_GPUIOV_CMD_STATUS_IP_0__CMD_STATUS_MASK 0x0000000FL 320 //MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0 321 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID__SHIFT 0x0 322 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_STATUS__SHIFT 0x8 323 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_MASK 0x000000FFL 324 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_STATUS_MASK 0x00000F00L 325 //MMSCH_GPUIOV_SCH_BLOCK_IP_1 326 #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__ID__SHIFT 0x0 327 #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__VERSION__SHIFT 0x4 328 #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__SIZE__SHIFT 0x8 329 #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__ID_MASK 0x0000000FL 330 #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__VERSION_MASK 0x000000F0L 331 #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__SIZE_MASK 0x0000FF00L 332 //MMSCH_GPUIOV_CMD_STATUS_IP_1 333 #define MMSCH_GPUIOV_CMD_STATUS_IP_1__CMD_STATUS__SHIFT 0x0 334 #define MMSCH_GPUIOV_CMD_STATUS_IP_1__CMD_STATUS_MASK 0x0000000FL 335 //MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1 336 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID__SHIFT 0x0 337 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_STATUS__SHIFT 0x8 338 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_MASK 0x000000FFL 339 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_STATUS_MASK 0x00000F00L 340 //MMSCH_GPUIOV_CNTXT_IP 341 #define MMSCH_GPUIOV_CNTXT_IP__CNTXT_SIZE__SHIFT 0x0 342 #define MMSCH_GPUIOV_CNTXT_IP__CNTXT_LOCATION__SHIFT 0x7 343 #define MMSCH_GPUIOV_CNTXT_IP__CNTXT_SIZE_MASK 0x0000007FL 344 #define MMSCH_GPUIOV_CNTXT_IP__CNTXT_LOCATION_MASK 0x00000080L 345 //MMSCH_GPUIOV_SCH_BLOCK_2 346 #define MMSCH_GPUIOV_SCH_BLOCK_2__ID__SHIFT 0x0 347 #define MMSCH_GPUIOV_SCH_BLOCK_2__VERSION__SHIFT 0x4 348 #define MMSCH_GPUIOV_SCH_BLOCK_2__SIZE__SHIFT 0x8 349 #define MMSCH_GPUIOV_SCH_BLOCK_2__ID_MASK 0x0000000FL 350 #define MMSCH_GPUIOV_SCH_BLOCK_2__VERSION_MASK 0x000000F0L 351 #define MMSCH_GPUIOV_SCH_BLOCK_2__SIZE_MASK 0x0000FF00L 352 //MMSCH_GPUIOV_CMD_CONTROL_2 353 #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_TYPE__SHIFT 0x0 354 #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE__SHIFT 0x4 355 #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_INTR_EN__SHIFT 0x5 356 #define MMSCH_GPUIOV_CMD_CONTROL_2__VM_BUSY_INTR_EN__SHIFT 0x6 357 #define MMSCH_GPUIOV_CMD_CONTROL_2__FUNCTINO_ID__SHIFT 0x8 358 #define MMSCH_GPUIOV_CMD_CONTROL_2__NEXT_FUNCTINO_ID__SHIFT 0x10 359 #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_TYPE_MASK 0x0000000FL 360 #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_MASK 0x00000010L 361 #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_INTR_EN_MASK 0x00000020L 362 #define MMSCH_GPUIOV_CMD_CONTROL_2__VM_BUSY_INTR_EN_MASK 0x00000040L 363 #define MMSCH_GPUIOV_CMD_CONTROL_2__FUNCTINO_ID_MASK 0x0000FF00L 364 #define MMSCH_GPUIOV_CMD_CONTROL_2__NEXT_FUNCTINO_ID_MASK 0x00FF0000L 365 //MMSCH_GPUIOV_CMD_STATUS_2 366 #define MMSCH_GPUIOV_CMD_STATUS_2__CMD_STATUS__SHIFT 0x0 367 #define MMSCH_GPUIOV_CMD_STATUS_2__CMD_STATUS_MASK 0x0000000FL 368 //MMSCH_GPUIOV_VM_BUSY_STATUS_2 369 #define MMSCH_GPUIOV_VM_BUSY_STATUS_2__BUSY__SHIFT 0x0 370 #define MMSCH_GPUIOV_VM_BUSY_STATUS_2__BUSY_MASK 0xFFFFFFFFL 371 //MMSCH_GPUIOV_ACTIVE_FCNS_2 372 #define MMSCH_GPUIOV_ACTIVE_FCNS_2__ACTIVE_FCNS__SHIFT 0x0 373 #define MMSCH_GPUIOV_ACTIVE_FCNS_2__ACTIVE_FCNS_MASK 0xFFFFFFFFL 374 //MMSCH_GPUIOV_ACTIVE_FCN_ID_2 375 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID__SHIFT 0x0 376 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_STATUS__SHIFT 0x8 377 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_MASK 0x000000FFL 378 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_STATUS_MASK 0x00000F00L 379 //MMSCH_GPUIOV_DW6_2 380 #define MMSCH_GPUIOV_DW6_2__DATA__SHIFT 0x0 381 #define MMSCH_GPUIOV_DW6_2__DATA_MASK 0xFFFFFFFFL 382 //MMSCH_GPUIOV_DW7_2 383 #define MMSCH_GPUIOV_DW7_2__DATA__SHIFT 0x0 384 #define MMSCH_GPUIOV_DW7_2__DATA_MASK 0xFFFFFFFFL 385 //MMSCH_GPUIOV_DW8_2 386 #define MMSCH_GPUIOV_DW8_2__DATA__SHIFT 0x0 387 #define MMSCH_GPUIOV_DW8_2__DATA_MASK 0xFFFFFFFFL 388 //MMSCH_GPUIOV_SCH_BLOCK_IP_2 389 #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__ID__SHIFT 0x0 390 #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__VERSION__SHIFT 0x4 391 #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE__SHIFT 0x8 392 #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__ID_MASK 0x0000000FL 393 #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__VERSION_MASK 0x000000F0L 394 #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE_MASK 0x0000FF00L 395 //MMSCH_GPUIOV_CMD_STATUS_IP_2 396 #define MMSCH_GPUIOV_CMD_STATUS_IP_2__CMD_STATUS__SHIFT 0x0 397 #define MMSCH_GPUIOV_CMD_STATUS_IP_2__CMD_STATUS_MASK 0x0000000FL 398 //MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2 399 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID__SHIFT 0x0 400 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_STATUS__SHIFT 0x8 401 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_MASK 0x000000FFL 402 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_STATUS_MASK 0x00000F00L 403 //MMSCH_VFID_FIFO_HEAD_2 404 #define MMSCH_VFID_FIFO_HEAD_2__HEAD__SHIFT 0x0 405 #define MMSCH_VFID_FIFO_HEAD_2__HEAD_MASK 0x0000003FL 406 //MMSCH_VFID_FIFO_TAIL_2 407 #define MMSCH_VFID_FIFO_TAIL_2__TAIL__SHIFT 0x0 408 #define MMSCH_VFID_FIFO_TAIL_2__TAIL_MASK 0x0000003FL 409 //MMSCH_VM_BUSY_STATUS_0 410 #define MMSCH_VM_BUSY_STATUS_0__BUSY__SHIFT 0x0 411 #define MMSCH_VM_BUSY_STATUS_0__BUSY_MASK 0xFFFFFFFFL 412 //MMSCH_VM_BUSY_STATUS_1 413 #define MMSCH_VM_BUSY_STATUS_1__BUSY__SHIFT 0x0 414 #define MMSCH_VM_BUSY_STATUS_1__BUSY_MASK 0xFFFFFFFFL 415 //MMSCH_VM_BUSY_STATUS_2 416 #define MMSCH_VM_BUSY_STATUS_2__BUSY__SHIFT 0x0 417 #define MMSCH_VM_BUSY_STATUS_2__BUSY_MASK 0xFFFFFFFFL 418 419 420 // addressBlock: uvd0_jpegnpdec 421 //UVD_JPEG_CNTL 422 #define UVD_JPEG_CNTL__REQUEST_EN__SHIFT 0x1 423 #define UVD_JPEG_CNTL__ERR_RST_EN__SHIFT 0x2 424 #define UVD_JPEG_CNTL__HUFF_SPEED_EN__SHIFT 0x3 425 #define UVD_JPEG_CNTL__HUFF_SPEED_STATUS__SHIFT 0x4 426 #define UVD_JPEG_CNTL__REQUEST_EN_MASK 0x00000002L 427 #define UVD_JPEG_CNTL__ERR_RST_EN_MASK 0x00000004L 428 #define UVD_JPEG_CNTL__HUFF_SPEED_EN_MASK 0x00000008L 429 #define UVD_JPEG_CNTL__HUFF_SPEED_STATUS_MASK 0x00000010L 430 //UVD_JPEG_RB_BASE 431 #define UVD_JPEG_RB_BASE__RB_BYTE_OFF__SHIFT 0x0 432 #define UVD_JPEG_RB_BASE__RB_BASE__SHIFT 0x6 433 #define UVD_JPEG_RB_BASE__RB_BYTE_OFF_MASK 0x0000003FL 434 #define UVD_JPEG_RB_BASE__RB_BASE_MASK 0xFFFFFFC0L 435 //UVD_JPEG_RB_WPTR 436 #define UVD_JPEG_RB_WPTR__RB_WPTR__SHIFT 0x4 437 #define UVD_JPEG_RB_WPTR__RB_WPTR_MASK 0x3FFFFFF0L 438 //UVD_JPEG_RB_RPTR 439 #define UVD_JPEG_RB_RPTR__RB_RPTR__SHIFT 0x4 440 #define UVD_JPEG_RB_RPTR__RB_RPTR_MASK 0x3FFFFFF0L 441 //UVD_JPEG_RB_SIZE 442 #define UVD_JPEG_RB_SIZE__RB_SIZE__SHIFT 0x4 443 #define UVD_JPEG_RB_SIZE__RB_SIZE_MASK 0x3FFFFFF0L 444 //UVD_JPEG_DEC_SCRATCH0 445 #define UVD_JPEG_DEC_SCRATCH0__SCRATCH0__SHIFT 0x0 446 #define UVD_JPEG_DEC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 447 //UVD_JPEG_INT_EN 448 #define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN__SHIFT 0x0 449 #define UVD_JPEG_INT_EN__JOB_AVAIL_EN__SHIFT 0x1 450 #define UVD_JPEG_INT_EN__FENCE_VAL_EN__SHIFT 0x2 451 #define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN__SHIFT 0x6 452 #define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN__SHIFT 0x7 453 #define UVD_JPEG_INT_EN__EOI_ERR_EN__SHIFT 0x8 454 #define UVD_JPEG_INT_EN__HFM_ERR_EN__SHIFT 0x9 455 #define UVD_JPEG_INT_EN__RST_ERR_EN__SHIFT 0xa 456 #define UVD_JPEG_INT_EN__ECS_MK_ERR_EN__SHIFT 0xb 457 #define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN__SHIFT 0xc 458 #define UVD_JPEG_INT_EN__MARKER_ERR_EN__SHIFT 0xd 459 #define UVD_JPEG_INT_EN__FMT_ERR_EN__SHIFT 0xe 460 #define UVD_JPEG_INT_EN__PROFILE_ERR_EN__SHIFT 0xf 461 #define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN_MASK 0x00000001L 462 #define UVD_JPEG_INT_EN__JOB_AVAIL_EN_MASK 0x00000002L 463 #define UVD_JPEG_INT_EN__FENCE_VAL_EN_MASK 0x00000004L 464 #define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN_MASK 0x00000040L 465 #define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN_MASK 0x00000080L 466 #define UVD_JPEG_INT_EN__EOI_ERR_EN_MASK 0x00000100L 467 #define UVD_JPEG_INT_EN__HFM_ERR_EN_MASK 0x00000200L 468 #define UVD_JPEG_INT_EN__RST_ERR_EN_MASK 0x00000400L 469 #define UVD_JPEG_INT_EN__ECS_MK_ERR_EN_MASK 0x00000800L 470 #define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN_MASK 0x00001000L 471 #define UVD_JPEG_INT_EN__MARKER_ERR_EN_MASK 0x00002000L 472 #define UVD_JPEG_INT_EN__FMT_ERR_EN_MASK 0x00004000L 473 #define UVD_JPEG_INT_EN__PROFILE_ERR_EN_MASK 0x00008000L 474 //UVD_JPEG_INT_STAT 475 #define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT__SHIFT 0x0 476 #define UVD_JPEG_INT_STAT__JOB_AVAIL_INT__SHIFT 0x1 477 #define UVD_JPEG_INT_STAT__FENCE_VAL_INT__SHIFT 0x2 478 #define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT__SHIFT 0x6 479 #define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT__SHIFT 0x7 480 #define UVD_JPEG_INT_STAT__EOI_ERR_INT__SHIFT 0x8 481 #define UVD_JPEG_INT_STAT__HFM_ERR_INT__SHIFT 0x9 482 #define UVD_JPEG_INT_STAT__RST_ERR_INT__SHIFT 0xa 483 #define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT__SHIFT 0xb 484 #define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT__SHIFT 0xc 485 #define UVD_JPEG_INT_STAT__MARKER_ERR_INT__SHIFT 0xd 486 #define UVD_JPEG_INT_STAT__FMT_ERR_INT__SHIFT 0xe 487 #define UVD_JPEG_INT_STAT__PROFILE_ERR_INT__SHIFT 0xf 488 #define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT_MASK 0x00000001L 489 #define UVD_JPEG_INT_STAT__JOB_AVAIL_INT_MASK 0x00000002L 490 #define UVD_JPEG_INT_STAT__FENCE_VAL_INT_MASK 0x00000004L 491 #define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT_MASK 0x00000040L 492 #define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT_MASK 0x00000080L 493 #define UVD_JPEG_INT_STAT__EOI_ERR_INT_MASK 0x00000100L 494 #define UVD_JPEG_INT_STAT__HFM_ERR_INT_MASK 0x00000200L 495 #define UVD_JPEG_INT_STAT__RST_ERR_INT_MASK 0x00000400L 496 #define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT_MASK 0x00000800L 497 #define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT_MASK 0x00001000L 498 #define UVD_JPEG_INT_STAT__MARKER_ERR_INT_MASK 0x00002000L 499 #define UVD_JPEG_INT_STAT__FMT_ERR_INT_MASK 0x00004000L 500 #define UVD_JPEG_INT_STAT__PROFILE_ERR_INT_MASK 0x00008000L 501 //UVD_JPEG_PITCH 502 #define UVD_JPEG_PITCH__PITCH__SHIFT 0x0 503 #define UVD_JPEG_PITCH__PITCH_MASK 0xFFFFFFFFL 504 //UVD_JPEG_UV_PITCH 505 #define UVD_JPEG_UV_PITCH__UV_PITCH__SHIFT 0x0 506 #define UVD_JPEG_UV_PITCH__UV_PITCH_MASK 0xFFFFFFFFL 507 //JPEG_DEC_Y_GFX8_TILING_SURFACE 508 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_WIDTH__SHIFT 0x0 509 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_HEIGHT__SHIFT 0x2 510 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT__SHIFT 0x4 511 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__NUM_BANKS__SHIFT 0x6 512 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__PIPE_CONFIG__SHIFT 0x8 513 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__TILE_SPLIT__SHIFT 0xd 514 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__ARRAY_MODE__SHIFT 0x10 515 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_WIDTH_MASK 0x00000003L 516 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_HEIGHT_MASK 0x0000000CL 517 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT_MASK 0x00000030L 518 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__NUM_BANKS_MASK 0x000000C0L 519 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__PIPE_CONFIG_MASK 0x00001F00L 520 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__TILE_SPLIT_MASK 0x0000E000L 521 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__ARRAY_MODE_MASK 0x000F0000L 522 //JPEG_DEC_UV_GFX8_TILING_SURFACE 523 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_WIDTH__SHIFT 0x0 524 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_HEIGHT__SHIFT 0x2 525 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT__SHIFT 0x4 526 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__NUM_BANKS__SHIFT 0x6 527 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__PIPE_CONFIG__SHIFT 0x8 528 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__TILE_SPLIT__SHIFT 0xd 529 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__ARRAY_MODE__SHIFT 0x10 530 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_WIDTH_MASK 0x00000003L 531 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_HEIGHT_MASK 0x0000000CL 532 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT_MASK 0x00000030L 533 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__NUM_BANKS_MASK 0x000000C0L 534 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__PIPE_CONFIG_MASK 0x00001F00L 535 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__TILE_SPLIT_MASK 0x0000E000L 536 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__ARRAY_MODE_MASK 0x000F0000L 537 //JPEG_DEC_GFX8_ADDR_CONFIG 538 #define JPEG_DEC_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 539 #define JPEG_DEC_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L 540 //JPEG_DEC_Y_GFX10_TILING_SURFACE 541 #define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 542 #define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 543 //JPEG_DEC_UV_GFX10_TILING_SURFACE 544 #define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 545 #define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 546 //JPEG_DEC_GFX10_ADDR_CONFIG 547 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 548 #define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 549 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 550 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 551 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 552 #define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 553 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 554 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 555 //JPEG_DEC_ADDR_MODE 556 #define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y__SHIFT 0x0 557 #define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV__SHIFT 0x2 558 #define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL__SHIFT 0xc 559 #define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y_MASK 0x00000003L 560 #define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV_MASK 0x0000000CL 561 #define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL_MASK 0x00007000L 562 //UVD_JPEG_GPCOM_CMD 563 #define UVD_JPEG_GPCOM_CMD__CMD__SHIFT 0x1 564 #define UVD_JPEG_GPCOM_CMD__CMD_MASK 0x0000000EL 565 //UVD_JPEG_GPCOM_DATA0 566 #define UVD_JPEG_GPCOM_DATA0__DATA0__SHIFT 0x0 567 #define UVD_JPEG_GPCOM_DATA0__DATA0_MASK 0xFFFFFFFFL 568 //UVD_JPEG_GPCOM_DATA1 569 #define UVD_JPEG_GPCOM_DATA1__DATA1__SHIFT 0x0 570 #define UVD_JPEG_GPCOM_DATA1__DATA1_MASK 0xFFFFFFFFL 571 //UVD_JPEG_SCRATCH1 572 #define UVD_JPEG_SCRATCH1__SCRATCH1__SHIFT 0x0 573 #define UVD_JPEG_SCRATCH1__SCRATCH1_MASK 0xFFFFFFFFL 574 //UVD_JPEG_DEC_SOFT_RST 575 #define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET__SHIFT 0x0 576 #define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS__SHIFT 0x10 577 #define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET_MASK 0x00000001L 578 #define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS_MASK 0x00010000L 579 580 581 // addressBlock: uvd0_uvd_jpeg_enc_dec 582 //UVD_JPEG_ENC_INT_EN 583 #define UVD_JPEG_ENC_INT_EN__HUFF_JOB_DONE_INT_EN__SHIFT 0x0 584 #define UVD_JPEG_ENC_INT_EN__SCLR_JOB_DONE_INT_EN__SHIFT 0x1 585 #define UVD_JPEG_ENC_INT_EN__HUFF_ERROR_INT_EN__SHIFT 0x2 586 #define UVD_JPEG_ENC_INT_EN__SCLR_ERROR_INT_EN__SHIFT 0x3 587 #define UVD_JPEG_ENC_INT_EN__QTBL_ERROR_INT_EN__SHIFT 0x4 588 #define UVD_JPEG_ENC_INT_EN__PIC_SIZE_ERROR_INT_EN__SHIFT 0x5 589 #define UVD_JPEG_ENC_INT_EN__FENCE_VAL_INT_EN__SHIFT 0x6 590 #define UVD_JPEG_ENC_INT_EN__HUFF_JOB_DONE_INT_EN_MASK 0x00000001L 591 #define UVD_JPEG_ENC_INT_EN__SCLR_JOB_DONE_INT_EN_MASK 0x00000002L 592 #define UVD_JPEG_ENC_INT_EN__HUFF_ERROR_INT_EN_MASK 0x00000004L 593 #define UVD_JPEG_ENC_INT_EN__SCLR_ERROR_INT_EN_MASK 0x00000008L 594 #define UVD_JPEG_ENC_INT_EN__QTBL_ERROR_INT_EN_MASK 0x00000010L 595 #define UVD_JPEG_ENC_INT_EN__PIC_SIZE_ERROR_INT_EN_MASK 0x00000020L 596 #define UVD_JPEG_ENC_INT_EN__FENCE_VAL_INT_EN_MASK 0x00000040L 597 //UVD_JPEG_ENC_INT_STATUS 598 #define UVD_JPEG_ENC_INT_STATUS__HUFF_JOB_DONE_STATUS__SHIFT 0x0 599 #define UVD_JPEG_ENC_INT_STATUS__SCLR_JOB_DONE_STATUS__SHIFT 0x1 600 #define UVD_JPEG_ENC_INT_STATUS__HUFF_ERROR_STATUS__SHIFT 0x2 601 #define UVD_JPEG_ENC_INT_STATUS__SCLR_ERROR_STATUS__SHIFT 0x3 602 #define UVD_JPEG_ENC_INT_STATUS__QTBL_ERROR_STATUS__SHIFT 0x4 603 #define UVD_JPEG_ENC_INT_STATUS__PIC_SIZE_ERROR_STATUS__SHIFT 0x5 604 #define UVD_JPEG_ENC_INT_STATUS__FENCE_VAL_STATUS__SHIFT 0x6 605 #define UVD_JPEG_ENC_INT_STATUS__HUFF_JOB_DONE_STATUS_MASK 0x00000001L 606 #define UVD_JPEG_ENC_INT_STATUS__SCLR_JOB_DONE_STATUS_MASK 0x00000002L 607 #define UVD_JPEG_ENC_INT_STATUS__HUFF_ERROR_STATUS_MASK 0x00000004L 608 #define UVD_JPEG_ENC_INT_STATUS__SCLR_ERROR_STATUS_MASK 0x00000008L 609 #define UVD_JPEG_ENC_INT_STATUS__QTBL_ERROR_STATUS_MASK 0x00000010L 610 #define UVD_JPEG_ENC_INT_STATUS__PIC_SIZE_ERROR_STATUS_MASK 0x00000020L 611 #define UVD_JPEG_ENC_INT_STATUS__FENCE_VAL_STATUS_MASK 0x00000040L 612 //UVD_JPEG_ENC_ENGINE_CNTL 613 #define UVD_JPEG_ENC_ENGINE_CNTL__HUFF_WR_COMB_DIS__SHIFT 0x0 614 #define UVD_JPEG_ENC_ENGINE_CNTL__DISTINCT_CHROMA_QUANT_TABLES__SHIFT 0x1 615 #define UVD_JPEG_ENC_ENGINE_CNTL__SCALAR_EN__SHIFT 0x2 616 #define UVD_JPEG_ENC_ENGINE_CNTL__ENCODE_EN__SHIFT 0x3 617 #define UVD_JPEG_ENC_ENGINE_CNTL__CMP_NEEDED__SHIFT 0x4 618 #define UVD_JPEG_ENC_ENGINE_CNTL__ECS_RESTRICT_32B_EN__SHIFT 0x9 619 #define UVD_JPEG_ENC_ENGINE_CNTL__HUFF_WR_COMB_DIS_MASK 0x00000001L 620 #define UVD_JPEG_ENC_ENGINE_CNTL__DISTINCT_CHROMA_QUANT_TABLES_MASK 0x00000002L 621 #define UVD_JPEG_ENC_ENGINE_CNTL__SCALAR_EN_MASK 0x00000004L 622 #define UVD_JPEG_ENC_ENGINE_CNTL__ENCODE_EN_MASK 0x00000008L 623 #define UVD_JPEG_ENC_ENGINE_CNTL__CMP_NEEDED_MASK 0x00000010L 624 #define UVD_JPEG_ENC_ENGINE_CNTL__ECS_RESTRICT_32B_EN_MASK 0x00000200L 625 //UVD_JPEG_ENC_SCRATCH1 626 #define UVD_JPEG_ENC_SCRATCH1__SCRATCH1__SHIFT 0x0 627 #define UVD_JPEG_ENC_SCRATCH1__SCRATCH1_MASK 0xFFFFFFFFL 628 629 630 // addressBlock: uvd0_uvd_jpeg_enc_sclk_dec 631 //UVD_JPEG_ENC_STATUS 632 #define UVD_JPEG_ENC_STATUS__PEL_FETCH_IDLE__SHIFT 0x0 633 #define UVD_JPEG_ENC_STATUS__HUFF_CORE_IDLE__SHIFT 0x1 634 #define UVD_JPEG_ENC_STATUS__FDCT_IDLE__SHIFT 0x2 635 #define UVD_JPEG_ENC_STATUS__SCALAR_IDLE__SHIFT 0x3 636 #define UVD_JPEG_ENC_STATUS__PEL_FETCH_IDLE_MASK 0x00000001L 637 #define UVD_JPEG_ENC_STATUS__HUFF_CORE_IDLE_MASK 0x00000002L 638 #define UVD_JPEG_ENC_STATUS__FDCT_IDLE_MASK 0x00000004L 639 #define UVD_JPEG_ENC_STATUS__SCALAR_IDLE_MASK 0x00000008L 640 //UVD_JPEG_ENC_PITCH 641 #define UVD_JPEG_ENC_PITCH__PITCH_Y__SHIFT 0x0 642 #define UVD_JPEG_ENC_PITCH__PITCH_UV__SHIFT 0x10 643 #define UVD_JPEG_ENC_PITCH__PITCH_Y_MASK 0x00000FFFL 644 #define UVD_JPEG_ENC_PITCH__PITCH_UV_MASK 0x0FFF0000L 645 //UVD_JPEG_ENC_LUMA_BASE 646 #define UVD_JPEG_ENC_LUMA_BASE__LUMA_BASE__SHIFT 0x0 647 #define UVD_JPEG_ENC_LUMA_BASE__LUMA_BASE_MASK 0xFFFFFFFFL 648 //UVD_JPEG_ENC_CHROMAU_BASE 649 #define UVD_JPEG_ENC_CHROMAU_BASE__CHROMAU_BASE__SHIFT 0x0 650 #define UVD_JPEG_ENC_CHROMAU_BASE__CHROMAU_BASE_MASK 0xFFFFFFFFL 651 //UVD_JPEG_ENC_CHROMAV_BASE 652 #define UVD_JPEG_ENC_CHROMAV_BASE__CHROMAV_BASE__SHIFT 0x0 653 #define UVD_JPEG_ENC_CHROMAV_BASE__CHROMAV_BASE_MASK 0xFFFFFFFFL 654 //JPEG_ENC_Y_GFX10_TILING_SURFACE 655 #define JPEG_ENC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 656 #define JPEG_ENC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 657 //JPEG_ENC_UV_GFX10_TILING_SURFACE 658 #define JPEG_ENC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 659 #define JPEG_ENC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 660 //JPEG_ENC_GFX10_ADDR_CONFIG 661 #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 662 #define JPEG_ENC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 663 #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 664 #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 665 #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 666 #define JPEG_ENC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 667 #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 668 #define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 669 //JPEG_ENC_ADDR_MODE 670 #define JPEG_ENC_ADDR_MODE__ADDR_MODE_Y__SHIFT 0x0 671 #define JPEG_ENC_ADDR_MODE__ADDR_MODE_UV__SHIFT 0x2 672 #define JPEG_ENC_ADDR_MODE__ADDR_LIB_SEL__SHIFT 0xc 673 #define JPEG_ENC_ADDR_MODE__ADDR_MODE_Y_MASK 0x00000003L 674 #define JPEG_ENC_ADDR_MODE__ADDR_MODE_UV_MASK 0x0000000CL 675 #define JPEG_ENC_ADDR_MODE__ADDR_LIB_SEL_MASK 0x00007000L 676 //UVD_JPEG_ENC_GPCOM_CMD 677 #define UVD_JPEG_ENC_GPCOM_CMD__CMD__SHIFT 0x1 678 #define UVD_JPEG_ENC_GPCOM_CMD__CMD_MASK 0x0000000EL 679 //UVD_JPEG_ENC_GPCOM_DATA0 680 #define UVD_JPEG_ENC_GPCOM_DATA0__DATA0__SHIFT 0x0 681 #define UVD_JPEG_ENC_GPCOM_DATA0__DATA0_MASK 0xFFFFFFFFL 682 //UVD_JPEG_ENC_GPCOM_DATA1 683 #define UVD_JPEG_ENC_GPCOM_DATA1__DATA1__SHIFT 0x0 684 #define UVD_JPEG_ENC_GPCOM_DATA1__DATA1_MASK 0xFFFFFFFFL 685 //UVD_JPEG_ENC_CGC_CNTL 686 #define UVD_JPEG_ENC_CGC_CNTL__CGC_EN__SHIFT 0x0 687 #define UVD_JPEG_ENC_CGC_CNTL__CGC_EN_MASK 0x00000001L 688 //UVD_JPEG_ENC_SCRATCH0 689 #define UVD_JPEG_ENC_SCRATCH0__SCRATCH0__SHIFT 0x0 690 #define UVD_JPEG_ENC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 691 //UVD_JPEG_ENC_SOFT_RST 692 #define UVD_JPEG_ENC_SOFT_RST__SOFT_RST__SHIFT 0x0 693 #define UVD_JPEG_ENC_SOFT_RST__RESET_STATUS__SHIFT 0x10 694 #define UVD_JPEG_ENC_SOFT_RST__SOFT_RST_MASK 0x00000001L 695 #define UVD_JPEG_ENC_SOFT_RST__RESET_STATUS_MASK 0x00010000L 696 697 698 // addressBlock: uvd0_uvd_jrbc_dec 699 //UVD_JRBC_RB_WPTR 700 #define UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT 0x4 701 #define UVD_JRBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 702 //UVD_JRBC_RB_CNTL 703 #define UVD_JRBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0 704 #define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1 705 #define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 706 #define UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L 707 #define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L 708 #define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L 709 //UVD_JRBC_IB_SIZE 710 #define UVD_JRBC_IB_SIZE__IB_SIZE__SHIFT 0x4 711 #define UVD_JRBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 712 //UVD_JRBC_URGENT_CNTL 713 #define UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 714 #define UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L 715 //UVD_JRBC_RB_REF_DATA 716 #define UVD_JRBC_RB_REF_DATA__REF_DATA__SHIFT 0x0 717 #define UVD_JRBC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 718 //UVD_JRBC_RB_COND_RD_TIMER 719 #define UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 720 #define UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 721 #define UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 722 #define UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 723 #define UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 724 #define UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 725 #define UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 726 #define UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 727 //UVD_JRBC_SOFT_RESET 728 #define UVD_JRBC_SOFT_RESET__RESET__SHIFT 0x0 729 #define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11 730 #define UVD_JRBC_SOFT_RESET__RESET_MASK 0x00000001L 731 #define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L 732 //UVD_JRBC_STATUS 733 #define UVD_JRBC_STATUS__RB_JOB_DONE__SHIFT 0x0 734 #define UVD_JRBC_STATUS__IB_JOB_DONE__SHIFT 0x1 735 #define UVD_JRBC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2 736 #define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3 737 #define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4 738 #define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5 739 #define UVD_JRBC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6 740 #define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7 741 #define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8 742 #define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9 743 #define UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa 744 #define UVD_JRBC_STATUS__PREEMPT_STATUS__SHIFT 0xb 745 #define UVD_JRBC_STATUS__IB_TRAP_STATUS__SHIFT 0xc 746 #define UVD_JRBC_STATUS__INT_EN__SHIFT 0x10 747 #define UVD_JRBC_STATUS__INT_ACK__SHIFT 0x11 748 #define UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L 749 #define UVD_JRBC_STATUS__IB_JOB_DONE_MASK 0x00000002L 750 #define UVD_JRBC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L 751 #define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L 752 #define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L 753 #define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L 754 #define UVD_JRBC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L 755 #define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L 756 #define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L 757 #define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L 758 #define UVD_JRBC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L 759 #define UVD_JRBC_STATUS__PREEMPT_STATUS_MASK 0x00000800L 760 #define UVD_JRBC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L 761 #define UVD_JRBC_STATUS__INT_EN_MASK 0x00010000L 762 #define UVD_JRBC_STATUS__INT_ACK_MASK 0x00020000L 763 //UVD_JRBC_RB_RPTR 764 #define UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT 0x4 765 #define UVD_JRBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 766 //UVD_JRBC_RB_BUF_STATUS 767 #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 768 #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 769 #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18 770 #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL 771 #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L 772 #define UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L 773 //UVD_JRBC_IB_BUF_STATUS 774 #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0 775 #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10 776 #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18 777 #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL 778 #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L 779 #define UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L 780 //UVD_JRBC_IB_SIZE_UPDATE 781 #define UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 782 #define UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L 783 //UVD_JRBC_IB_COND_RD_TIMER 784 #define UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 785 #define UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 786 #define UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 787 #define UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 788 #define UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 789 #define UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 790 #define UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 791 #define UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 792 //UVD_JRBC_IB_REF_DATA 793 #define UVD_JRBC_IB_REF_DATA__REF_DATA__SHIFT 0x0 794 #define UVD_JRBC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 795 //UVD_JPEG_PREEMPT_CMD 796 #define UVD_JPEG_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0 797 #define UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1 798 #define UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2 799 #define UVD_JPEG_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L 800 #define UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L 801 #define UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L 802 //UVD_JPEG_PREEMPT_FENCE_DATA0 803 #define UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0 804 #define UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL 805 //UVD_JPEG_PREEMPT_FENCE_DATA1 806 #define UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0 807 #define UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL 808 //UVD_JRBC_RB_SIZE 809 #define UVD_JRBC_RB_SIZE__RB_SIZE__SHIFT 0x4 810 #define UVD_JRBC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L 811 //UVD_JRBC_SCRATCH0 812 #define UVD_JRBC_SCRATCH0__SCRATCH0__SHIFT 0x0 813 #define UVD_JRBC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 814 815 816 // addressBlock: uvd0_uvd_jrbc_enc_dec 817 //UVD_JRBC_ENC_RB_WPTR 818 #define UVD_JRBC_ENC_RB_WPTR__RB_WPTR__SHIFT 0x4 819 #define UVD_JRBC_ENC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 820 //UVD_JRBC_ENC_RB_CNTL 821 #define UVD_JRBC_ENC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0 822 #define UVD_JRBC_ENC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1 823 #define UVD_JRBC_ENC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 824 #define UVD_JRBC_ENC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L 825 #define UVD_JRBC_ENC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L 826 #define UVD_JRBC_ENC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L 827 //UVD_JRBC_ENC_IB_SIZE 828 #define UVD_JRBC_ENC_IB_SIZE__IB_SIZE__SHIFT 0x4 829 #define UVD_JRBC_ENC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 830 //UVD_JRBC_ENC_URGENT_CNTL 831 #define UVD_JRBC_ENC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 832 #define UVD_JRBC_ENC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L 833 //UVD_JRBC_ENC_RB_REF_DATA 834 #define UVD_JRBC_ENC_RB_REF_DATA__REF_DATA__SHIFT 0x0 835 #define UVD_JRBC_ENC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 836 //UVD_JRBC_ENC_RB_COND_RD_TIMER 837 #define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 838 #define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 839 #define UVD_JRBC_ENC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 840 #define UVD_JRBC_ENC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 841 #define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 842 #define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 843 #define UVD_JRBC_ENC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 844 #define UVD_JRBC_ENC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 845 //UVD_JRBC_ENC_SOFT_RESET 846 #define UVD_JRBC_ENC_SOFT_RESET__RESET__SHIFT 0x0 847 #define UVD_JRBC_ENC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11 848 #define UVD_JRBC_ENC_SOFT_RESET__RESET_MASK 0x00000001L 849 #define UVD_JRBC_ENC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L 850 //UVD_JRBC_ENC_STATUS 851 #define UVD_JRBC_ENC_STATUS__RB_JOB_DONE__SHIFT 0x0 852 #define UVD_JRBC_ENC_STATUS__IB_JOB_DONE__SHIFT 0x1 853 #define UVD_JRBC_ENC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2 854 #define UVD_JRBC_ENC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3 855 #define UVD_JRBC_ENC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4 856 #define UVD_JRBC_ENC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5 857 #define UVD_JRBC_ENC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6 858 #define UVD_JRBC_ENC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7 859 #define UVD_JRBC_ENC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8 860 #define UVD_JRBC_ENC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9 861 #define UVD_JRBC_ENC_STATUS__RB_TRAP_STATUS__SHIFT 0xa 862 #define UVD_JRBC_ENC_STATUS__PREEMPT_STATUS__SHIFT 0xb 863 #define UVD_JRBC_ENC_STATUS__IB_TRAP_STATUS__SHIFT 0xc 864 #define UVD_JRBC_ENC_STATUS__INT_EN__SHIFT 0x10 865 #define UVD_JRBC_ENC_STATUS__INT_ACK__SHIFT 0x11 866 #define UVD_JRBC_ENC_STATUS__RB_JOB_DONE_MASK 0x00000001L 867 #define UVD_JRBC_ENC_STATUS__IB_JOB_DONE_MASK 0x00000002L 868 #define UVD_JRBC_ENC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L 869 #define UVD_JRBC_ENC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L 870 #define UVD_JRBC_ENC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L 871 #define UVD_JRBC_ENC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L 872 #define UVD_JRBC_ENC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L 873 #define UVD_JRBC_ENC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L 874 #define UVD_JRBC_ENC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L 875 #define UVD_JRBC_ENC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L 876 #define UVD_JRBC_ENC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L 877 #define UVD_JRBC_ENC_STATUS__PREEMPT_STATUS_MASK 0x00000800L 878 #define UVD_JRBC_ENC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L 879 #define UVD_JRBC_ENC_STATUS__INT_EN_MASK 0x00010000L 880 #define UVD_JRBC_ENC_STATUS__INT_ACK_MASK 0x00020000L 881 //UVD_JRBC_ENC_RB_RPTR 882 #define UVD_JRBC_ENC_RB_RPTR__RB_RPTR__SHIFT 0x4 883 #define UVD_JRBC_ENC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 884 //UVD_JRBC_ENC_RB_BUF_STATUS 885 #define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 886 #define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 887 #define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18 888 #define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL 889 #define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L 890 #define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L 891 //UVD_JRBC_ENC_IB_BUF_STATUS 892 #define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0 893 #define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10 894 #define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18 895 #define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL 896 #define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L 897 #define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L 898 //UVD_JRBC_ENC_IB_SIZE_UPDATE 899 #define UVD_JRBC_ENC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 900 #define UVD_JRBC_ENC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L 901 //UVD_JRBC_ENC_IB_COND_RD_TIMER 902 #define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 903 #define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 904 #define UVD_JRBC_ENC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 905 #define UVD_JRBC_ENC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 906 #define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 907 #define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 908 #define UVD_JRBC_ENC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 909 #define UVD_JRBC_ENC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 910 //UVD_JRBC_ENC_IB_REF_DATA 911 #define UVD_JRBC_ENC_IB_REF_DATA__REF_DATA__SHIFT 0x0 912 #define UVD_JRBC_ENC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 913 //UVD_JPEG_ENC_PREEMPT_CMD 914 #define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0 915 #define UVD_JPEG_ENC_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1 916 #define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2 917 #define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L 918 #define UVD_JPEG_ENC_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L 919 #define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L 920 //UVD_JPEG_ENC_PREEMPT_FENCE_DATA0 921 #define UVD_JPEG_ENC_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0 922 #define UVD_JPEG_ENC_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL 923 //UVD_JPEG_ENC_PREEMPT_FENCE_DATA1 924 #define UVD_JPEG_ENC_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0 925 #define UVD_JPEG_ENC_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL 926 //UVD_JRBC_ENC_RB_SIZE 927 #define UVD_JRBC_ENC_RB_SIZE__RB_SIZE__SHIFT 0x4 928 #define UVD_JRBC_ENC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L 929 //UVD_JRBC_ENC_SCRATCH0 930 #define UVD_JRBC_ENC_SCRATCH0__SCRATCH0__SHIFT 0x0 931 #define UVD_JRBC_ENC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 932 933 934 // addressBlock: uvd0_uvd_jmi_dec 935 //UVD_JMI_CTRL 936 #define UVD_JMI_CTRL__STALL_MC_ARB__SHIFT 0x0 937 #define UVD_JMI_CTRL__MASK_MC_URGENT__SHIFT 0x1 938 #define UVD_JMI_CTRL__ASSERT_MC_URGENT__SHIFT 0x2 939 #define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER__SHIFT 0x8 940 #define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER__SHIFT 0x10 941 #define UVD_JMI_CTRL__CRC_RESET__SHIFT 0x18 942 #define UVD_JMI_CTRL__CRC_SEL__SHIFT 0x19 943 #define UVD_JMI_CTRL__STALL_MC_ARB_MASK 0x00000001L 944 #define UVD_JMI_CTRL__MASK_MC_URGENT_MASK 0x00000002L 945 #define UVD_JMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000004L 946 #define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER_MASK 0x0000FF00L 947 #define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER_MASK 0x00FF0000L 948 #define UVD_JMI_CTRL__CRC_RESET_MASK 0x01000000L 949 #define UVD_JMI_CTRL__CRC_SEL_MASK 0x1E000000L 950 //UVD_LMI_JRBC_CTRL 951 #define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 952 #define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 953 #define UVD_LMI_JRBC_CTRL__RD_MAX_BURST__SHIFT 0x4 954 #define UVD_LMI_JRBC_CTRL__WR_MAX_BURST__SHIFT 0x8 955 #define UVD_LMI_JRBC_CTRL__RD_SWAP__SHIFT 0x14 956 #define UVD_LMI_JRBC_CTRL__WR_SWAP__SHIFT 0x16 957 #define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 958 #define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 959 #define UVD_LMI_JRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L 960 #define UVD_LMI_JRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L 961 #define UVD_LMI_JRBC_CTRL__RD_SWAP_MASK 0x00300000L 962 #define UVD_LMI_JRBC_CTRL__WR_SWAP_MASK 0x00C00000L 963 //UVD_LMI_JPEG_CTRL 964 #define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 965 #define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 966 #define UVD_LMI_JPEG_CTRL__RD_MAX_BURST__SHIFT 0x4 967 #define UVD_LMI_JPEG_CTRL__WR_MAX_BURST__SHIFT 0x8 968 #define UVD_LMI_JPEG_CTRL__RD_SWAP__SHIFT 0x14 969 #define UVD_LMI_JPEG_CTRL__WR_SWAP__SHIFT 0x16 970 #define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 971 #define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 972 #define UVD_LMI_JPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L 973 #define UVD_LMI_JPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L 974 #define UVD_LMI_JPEG_CTRL__RD_SWAP_MASK 0x00300000L 975 #define UVD_LMI_JPEG_CTRL__WR_SWAP_MASK 0x00C00000L 976 //UVD_JMI_EJRBC_CTRL 977 #define UVD_JMI_EJRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 978 #define UVD_JMI_EJRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 979 #define UVD_JMI_EJRBC_CTRL__RD_MAX_BURST__SHIFT 0x4 980 #define UVD_JMI_EJRBC_CTRL__WR_MAX_BURST__SHIFT 0x8 981 #define UVD_JMI_EJRBC_CTRL__RD_SWAP__SHIFT 0x14 982 #define UVD_JMI_EJRBC_CTRL__WR_SWAP__SHIFT 0x16 983 #define UVD_JMI_EJRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 984 #define UVD_JMI_EJRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 985 #define UVD_JMI_EJRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L 986 #define UVD_JMI_EJRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L 987 #define UVD_JMI_EJRBC_CTRL__RD_SWAP_MASK 0x00300000L 988 #define UVD_JMI_EJRBC_CTRL__WR_SWAP_MASK 0x00C00000L 989 //UVD_LMI_EJPEG_CTRL 990 #define UVD_LMI_EJPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 991 #define UVD_LMI_EJPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 992 #define UVD_LMI_EJPEG_CTRL__RD_MAX_BURST__SHIFT 0x4 993 #define UVD_LMI_EJPEG_CTRL__WR_MAX_BURST__SHIFT 0x8 994 #define UVD_LMI_EJPEG_CTRL__RD_SWAP__SHIFT 0x14 995 #define UVD_LMI_EJPEG_CTRL__WR_SWAP__SHIFT 0x16 996 #define UVD_LMI_EJPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 997 #define UVD_LMI_EJPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 998 #define UVD_LMI_EJPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L 999 #define UVD_LMI_EJPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L 1000 #define UVD_LMI_EJPEG_CTRL__RD_SWAP_MASK 0x00300000L 1001 #define UVD_LMI_EJPEG_CTRL__WR_SWAP_MASK 0x00C00000L 1002 //UVD_LMI_JRBC_IB_VMID 1003 #define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0 1004 #define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4 1005 #define UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8 1006 #define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL 1007 #define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L 1008 #define UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L 1009 //UVD_LMI_JRBC_RB_VMID 1010 #define UVD_LMI_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0 1011 #define UVD_LMI_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4 1012 #define UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8 1013 #define UVD_LMI_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL 1014 #define UVD_LMI_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L 1015 #define UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L 1016 //UVD_LMI_JPEG_VMID 1017 #define UVD_LMI_JPEG_VMID__JPEG_RD_VMID__SHIFT 0x0 1018 #define UVD_LMI_JPEG_VMID__JPEG_WR_VMID__SHIFT 0x4 1019 #define UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID__SHIFT 0x8 1020 #define UVD_LMI_JPEG_VMID__JPEG_RD_VMID_MASK 0x0000000FL 1021 #define UVD_LMI_JPEG_VMID__JPEG_WR_VMID_MASK 0x000000F0L 1022 #define UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID_MASK 0x00000F00L 1023 //UVD_JMI_ENC_JRBC_IB_VMID 1024 #define UVD_JMI_ENC_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0 1025 #define UVD_JMI_ENC_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4 1026 #define UVD_JMI_ENC_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8 1027 #define UVD_JMI_ENC_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL 1028 #define UVD_JMI_ENC_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L 1029 #define UVD_JMI_ENC_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L 1030 //UVD_JMI_ENC_JRBC_RB_VMID 1031 #define UVD_JMI_ENC_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0 1032 #define UVD_JMI_ENC_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4 1033 #define UVD_JMI_ENC_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8 1034 #define UVD_JMI_ENC_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL 1035 #define UVD_JMI_ENC_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L 1036 #define UVD_JMI_ENC_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L 1037 //UVD_JMI_ENC_JPEG_VMID 1038 #define UVD_JMI_ENC_JPEG_VMID__PEL_RD_VMID__SHIFT 0x0 1039 #define UVD_JMI_ENC_JPEG_VMID__BS_WR_VMID__SHIFT 0x5 1040 #define UVD_JMI_ENC_JPEG_VMID__SCALAR_RD_VMID__SHIFT 0xa 1041 #define UVD_JMI_ENC_JPEG_VMID__SCALAR_WR_VMID__SHIFT 0xf 1042 #define UVD_JMI_ENC_JPEG_VMID__HUFF_FENCE_VMID__SHIFT 0x13 1043 #define UVD_JMI_ENC_JPEG_VMID__ATOMIC_USER1_WR_VMID__SHIFT 0x17 1044 #define UVD_JMI_ENC_JPEG_VMID__PEL_RD_VMID_MASK 0x0000000FL 1045 #define UVD_JMI_ENC_JPEG_VMID__BS_WR_VMID_MASK 0x000001E0L 1046 #define UVD_JMI_ENC_JPEG_VMID__SCALAR_RD_VMID_MASK 0x00003C00L 1047 #define UVD_JMI_ENC_JPEG_VMID__SCALAR_WR_VMID_MASK 0x00078000L 1048 #define UVD_JMI_ENC_JPEG_VMID__HUFF_FENCE_VMID_MASK 0x00780000L 1049 #define UVD_JMI_ENC_JPEG_VMID__ATOMIC_USER1_WR_VMID_MASK 0x07800000L 1050 //UVD_JMI_PERFMON_CTRL 1051 #define UVD_JMI_PERFMON_CTRL__PERFMON_STATE__SHIFT 0x0 1052 #define UVD_JMI_PERFMON_CTRL__PERFMON_SEL__SHIFT 0x8 1053 #define UVD_JMI_PERFMON_CTRL__PERFMON_STATE_MASK 0x00000003L 1054 #define UVD_JMI_PERFMON_CTRL__PERFMON_SEL_MASK 0x00000F00L 1055 //UVD_JMI_PERFMON_COUNT_LO 1056 #define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT 0x0 1057 #define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK 0xFFFFFFFFL 1058 //UVD_JMI_PERFMON_COUNT_HI 1059 #define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT 0x0 1060 #define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK 0x0000FFFFL 1061 //UVD_LMI_JPEG_READ_64BIT_BAR_LOW 1062 #define UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1063 #define UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1064 //UVD_LMI_JPEG_READ_64BIT_BAR_HIGH 1065 #define UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1066 #define UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1067 //UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 1068 #define UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1069 #define UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1070 //UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 1071 #define UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1072 #define UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1073 //UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 1074 #define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1075 #define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1076 //UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 1077 #define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1078 #define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1079 //UVD_LMI_JRBC_RB_64BIT_BAR_LOW 1080 #define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1081 #define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1082 //UVD_LMI_JRBC_RB_64BIT_BAR_HIGH 1083 #define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1084 #define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1085 //UVD_LMI_JRBC_IB_64BIT_BAR_LOW 1086 #define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1087 #define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1088 //UVD_LMI_JRBC_IB_64BIT_BAR_HIGH 1089 #define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1090 #define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1091 //UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 1092 #define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1093 #define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1094 //UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 1095 #define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1096 #define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1097 //UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW 1098 #define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1099 #define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1100 //UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH 1101 #define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1102 #define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1103 //UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 1104 #define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1105 #define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1106 //UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 1107 #define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1108 #define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1109 //UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW 1110 #define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1111 #define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1112 //UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH 1113 #define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1114 #define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1115 //UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW 1116 #define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1117 #define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1118 //UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 1119 #define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1120 #define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1121 //UVD_LMI_EJRBC_RB_64BIT_BAR_LOW 1122 #define UVD_LMI_EJRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1123 #define UVD_LMI_EJRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1124 //UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH 1125 #define UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1126 #define UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1127 //UVD_LMI_EJRBC_IB_64BIT_BAR_LOW 1128 #define UVD_LMI_EJRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1129 #define UVD_LMI_EJRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1130 //UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH 1131 #define UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1132 #define UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1133 //UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW 1134 #define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1135 #define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1136 //UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH 1137 #define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1138 #define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1139 //UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW 1140 #define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1141 #define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1142 //UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH 1143 #define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1144 #define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1145 //UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW 1146 #define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1147 #define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1148 //UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH 1149 #define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1150 #define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1151 //UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW 1152 #define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1153 #define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1154 //UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH 1155 #define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1156 #define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1157 //UVD_LMI_JPEG_PREEMPT_VMID 1158 #define UVD_LMI_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0 1159 #define UVD_LMI_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL 1160 //UVD_LMI_ENC_JPEG_PREEMPT_VMID 1161 #define UVD_LMI_ENC_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0 1162 #define UVD_LMI_ENC_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL 1163 //UVD_LMI_JPEG2_VMID 1164 #define UVD_LMI_JPEG2_VMID__JPEG2_RD_VMID__SHIFT 0x0 1165 #define UVD_LMI_JPEG2_VMID__JPEG2_WR_VMID__SHIFT 0x4 1166 #define UVD_LMI_JPEG2_VMID__JPEG2_RD_VMID_MASK 0x0000000FL 1167 #define UVD_LMI_JPEG2_VMID__JPEG2_WR_VMID_MASK 0x000000F0L 1168 //UVD_LMI_JPEG2_READ_64BIT_BAR_LOW 1169 #define UVD_LMI_JPEG2_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1170 #define UVD_LMI_JPEG2_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1171 //UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH 1172 #define UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1173 #define UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1174 //UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW 1175 #define UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1176 #define UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1177 //UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH 1178 #define UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1179 #define UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1180 //UVD_LMI_JPEG_CTRL2 1181 #define UVD_LMI_JPEG_CTRL2__ARB_RD_WAIT_EN__SHIFT 0x0 1182 #define UVD_LMI_JPEG_CTRL2__ARB_WR_WAIT_EN__SHIFT 0x1 1183 #define UVD_LMI_JPEG_CTRL2__RD_MAX_BURST__SHIFT 0x4 1184 #define UVD_LMI_JPEG_CTRL2__WR_MAX_BURST__SHIFT 0x8 1185 #define UVD_LMI_JPEG_CTRL2__RD_SWAP__SHIFT 0x14 1186 #define UVD_LMI_JPEG_CTRL2__WR_SWAP__SHIFT 0x16 1187 #define UVD_LMI_JPEG_CTRL2__ARB_RD_WAIT_EN_MASK 0x00000001L 1188 #define UVD_LMI_JPEG_CTRL2__ARB_WR_WAIT_EN_MASK 0x00000002L 1189 #define UVD_LMI_JPEG_CTRL2__RD_MAX_BURST_MASK 0x000000F0L 1190 #define UVD_LMI_JPEG_CTRL2__WR_MAX_BURST_MASK 0x00000F00L 1191 #define UVD_LMI_JPEG_CTRL2__RD_SWAP_MASK 0x00300000L 1192 #define UVD_LMI_JPEG_CTRL2__WR_SWAP_MASK 0x00C00000L 1193 //UVD_JMI_DEC_SWAP_CNTL 1194 #define UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 1195 #define UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 1196 #define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4 1197 #define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6 1198 #define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8 1199 #define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa 1200 #define UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc 1201 #define UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP__SHIFT 0xe 1202 #define UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP__SHIFT 0x10 1203 #define UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 1204 #define UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 1205 #define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L 1206 #define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L 1207 #define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L 1208 #define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L 1209 #define UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L 1210 #define UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP_MASK 0x0000C000L 1211 #define UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP_MASK 0x00030000L 1212 //UVD_JMI_ENC_SWAP_CNTL 1213 #define UVD_JMI_ENC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 1214 #define UVD_JMI_ENC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 1215 #define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4 1216 #define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6 1217 #define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8 1218 #define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa 1219 #define UVD_JMI_ENC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc 1220 #define UVD_JMI_ENC_SWAP_CNTL__PEL_RD_MC_SWAP__SHIFT 0xe 1221 #define UVD_JMI_ENC_SWAP_CNTL__BS_WR_MC_SWAP__SHIFT 0x10 1222 #define UVD_JMI_ENC_SWAP_CNTL__SCALAR_RD_MC_SWAP__SHIFT 0x12 1223 #define UVD_JMI_ENC_SWAP_CNTL__SCALAR_WR_MC_SWAP__SHIFT 0x14 1224 #define UVD_JMI_ENC_SWAP_CNTL__HUFF_FENCE_MC_SWAP__SHIFT 0x16 1225 #define UVD_JMI_ENC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 1226 #define UVD_JMI_ENC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 1227 #define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L 1228 #define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L 1229 #define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L 1230 #define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L 1231 #define UVD_JMI_ENC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L 1232 #define UVD_JMI_ENC_SWAP_CNTL__PEL_RD_MC_SWAP_MASK 0x0000C000L 1233 #define UVD_JMI_ENC_SWAP_CNTL__BS_WR_MC_SWAP_MASK 0x00030000L 1234 #define UVD_JMI_ENC_SWAP_CNTL__SCALAR_RD_MC_SWAP_MASK 0x000C0000L 1235 #define UVD_JMI_ENC_SWAP_CNTL__SCALAR_WR_MC_SWAP_MASK 0x00300000L 1236 #define UVD_JMI_ENC_SWAP_CNTL__HUFF_FENCE_MC_SWAP_MASK 0x00C00000L 1237 //UVD_JMI_CNTL 1238 #define UVD_JMI_CNTL__SOFT_RESET__SHIFT 0x0 1239 #define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX__SHIFT 0x8 1240 #define UVD_JMI_CNTL__SOFT_RESET_MASK 0x00000001L 1241 #define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX_MASK 0x0003FF00L 1242 //UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW 1243 #define UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1244 #define UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1245 //UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH 1246 #define UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1247 #define UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1248 //UVD_JMI_DEC_SWAP_CNTL2 1249 #define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_RD_MC_SWAP__SHIFT 0x0 1250 #define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_WR_MC_SWAP__SHIFT 0x2 1251 #define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_RD_MC_SWAP_MASK 0x00000003L 1252 #define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_WR_MC_SWAP_MASK 0x0000000CL 1253 1254 1255 // addressBlock: uvd0_uvd_jpeg_common_dec 1256 //JPEG_SOFT_RESET_STATUS 1257 #define JPEG_SOFT_RESET_STATUS__JPEG_DEC_RESET_STATUS__SHIFT 0x0 1258 #define JPEG_SOFT_RESET_STATUS__JPEG2_DEC_RESET_STATUS__SHIFT 0x1 1259 #define JPEG_SOFT_RESET_STATUS__DJRBC_RESET_STATUS__SHIFT 0x2 1260 #define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS__SHIFT 0x3 1261 #define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS__SHIFT 0x4 1262 #define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS__SHIFT 0x5 1263 #define JPEG_SOFT_RESET_STATUS__JPEG_DEC_RESET_STATUS_MASK 0x00000001L 1264 #define JPEG_SOFT_RESET_STATUS__JPEG2_DEC_RESET_STATUS_MASK 0x00000002L 1265 #define JPEG_SOFT_RESET_STATUS__DJRBC_RESET_STATUS_MASK 0x00000004L 1266 #define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS_MASK 0x00000008L 1267 #define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS_MASK 0x00000010L 1268 #define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS_MASK 0x00000020L 1269 //JPEG_SYS_INT_EN 1270 #define JPEG_SYS_INT_EN__DJPEG_CORE__SHIFT 0x0 1271 #define JPEG_SYS_INT_EN__DJRBC__SHIFT 0x1 1272 #define JPEG_SYS_INT_EN__DJPEG_PF_RPT__SHIFT 0x2 1273 #define JPEG_SYS_INT_EN__EJPEG_PF_RPT__SHIFT 0x3 1274 #define JPEG_SYS_INT_EN__EJPEG_CORE__SHIFT 0x4 1275 #define JPEG_SYS_INT_EN__EJRBC__SHIFT 0x5 1276 #define JPEG_SYS_INT_EN__DJPEG_CORE2__SHIFT 0x6 1277 #define JPEG_SYS_INT_EN__DJPEG_CORE_MASK 0x00000001L 1278 #define JPEG_SYS_INT_EN__DJRBC_MASK 0x00000002L 1279 #define JPEG_SYS_INT_EN__DJPEG_PF_RPT_MASK 0x00000004L 1280 #define JPEG_SYS_INT_EN__EJPEG_PF_RPT_MASK 0x00000008L 1281 #define JPEG_SYS_INT_EN__EJPEG_CORE_MASK 0x00000010L 1282 #define JPEG_SYS_INT_EN__EJRBC_MASK 0x00000020L 1283 #define JPEG_SYS_INT_EN__DJPEG_CORE2_MASK 0x00000040L 1284 //JPEG_SYS_INT_STATUS 1285 #define JPEG_SYS_INT_STATUS__DJPEG_CORE__SHIFT 0x0 1286 #define JPEG_SYS_INT_STATUS__DJRBC__SHIFT 0x1 1287 #define JPEG_SYS_INT_STATUS__DJPEG_PF_RPT__SHIFT 0x2 1288 #define JPEG_SYS_INT_STATUS__EJPEG_PF_RPT__SHIFT 0x3 1289 #define JPEG_SYS_INT_STATUS__EJPEG_CORE__SHIFT 0x4 1290 #define JPEG_SYS_INT_STATUS__EJRBC__SHIFT 0x5 1291 #define JPEG_SYS_INT_STATUS__DJPEG_CORE2__SHIFT 0x6 1292 #define JPEG_SYS_INT_STATUS__DJPEG_CORE_MASK 0x00000001L 1293 #define JPEG_SYS_INT_STATUS__DJRBC_MASK 0x00000002L 1294 #define JPEG_SYS_INT_STATUS__DJPEG_PF_RPT_MASK 0x00000004L 1295 #define JPEG_SYS_INT_STATUS__EJPEG_PF_RPT_MASK 0x00000008L 1296 #define JPEG_SYS_INT_STATUS__EJPEG_CORE_MASK 0x00000010L 1297 #define JPEG_SYS_INT_STATUS__EJRBC_MASK 0x00000020L 1298 #define JPEG_SYS_INT_STATUS__DJPEG_CORE2_MASK 0x00000040L 1299 //JPEG_SYS_INT_ACK 1300 #define JPEG_SYS_INT_ACK__DJPEG_CORE__SHIFT 0x0 1301 #define JPEG_SYS_INT_ACK__DJRBC__SHIFT 0x1 1302 #define JPEG_SYS_INT_ACK__DJPEG_PF_RPT__SHIFT 0x2 1303 #define JPEG_SYS_INT_ACK__EJPEG_PF_RPT__SHIFT 0x3 1304 #define JPEG_SYS_INT_ACK__EJPEG_CORE__SHIFT 0x4 1305 #define JPEG_SYS_INT_ACK__EJRBC__SHIFT 0x5 1306 #define JPEG_SYS_INT_ACK__DJPEG_CORE2__SHIFT 0x6 1307 #define JPEG_SYS_INT_ACK__DJPEG_CORE_MASK 0x00000001L 1308 #define JPEG_SYS_INT_ACK__DJRBC_MASK 0x00000002L 1309 #define JPEG_SYS_INT_ACK__DJPEG_PF_RPT_MASK 0x00000004L 1310 #define JPEG_SYS_INT_ACK__EJPEG_PF_RPT_MASK 0x00000008L 1311 #define JPEG_SYS_INT_ACK__EJPEG_CORE_MASK 0x00000010L 1312 #define JPEG_SYS_INT_ACK__EJRBC_MASK 0x00000020L 1313 #define JPEG_SYS_INT_ACK__DJPEG_CORE2_MASK 0x00000040L 1314 //JPEG_MASTINT_EN 1315 #define JPEG_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 1316 #define JPEG_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 1317 #define JPEG_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L 1318 #define JPEG_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L 1319 //JPEG_IH_CTRL 1320 #define JPEG_IH_CTRL__IH_SOFT_RESET__SHIFT 0x0 1321 #define JPEG_IH_CTRL__IH_STALL_EN__SHIFT 0x1 1322 #define JPEG_IH_CTRL__IH_STATUS_CLEAN__SHIFT 0x2 1323 #define JPEG_IH_CTRL__IH_VMID__SHIFT 0x3 1324 #define JPEG_IH_CTRL__IH_USER_DATA__SHIFT 0x7 1325 #define JPEG_IH_CTRL__IH_RINGID__SHIFT 0x13 1326 #define JPEG_IH_CTRL__IH_SOFT_RESET_MASK 0x00000001L 1327 #define JPEG_IH_CTRL__IH_STALL_EN_MASK 0x00000002L 1328 #define JPEG_IH_CTRL__IH_STATUS_CLEAN_MASK 0x00000004L 1329 #define JPEG_IH_CTRL__IH_VMID_MASK 0x00000078L 1330 #define JPEG_IH_CTRL__IH_USER_DATA_MASK 0x0007FF80L 1331 #define JPEG_IH_CTRL__IH_RINGID_MASK 0x07F80000L 1332 //JRBBM_ARB_CTRL 1333 #define JRBBM_ARB_CTRL__DJRBC_DROP__SHIFT 0x0 1334 #define JRBBM_ARB_CTRL__EJRBC_DROP__SHIFT 0x1 1335 #define JRBBM_ARB_CTRL__SRBM_DROP__SHIFT 0x2 1336 #define JRBBM_ARB_CTRL__DJRBC_DROP_MASK 0x00000001L 1337 #define JRBBM_ARB_CTRL__EJRBC_DROP_MASK 0x00000002L 1338 #define JRBBM_ARB_CTRL__SRBM_DROP_MASK 0x00000004L 1339 1340 1341 // addressBlock: uvd0_uvd_jpeg_common_sclk_dec 1342 //JPEG_CGC_GATE 1343 #define JPEG_CGC_GATE__JPEG_DEC__SHIFT 0x0 1344 #define JPEG_CGC_GATE__JPEG2_DEC__SHIFT 0x1 1345 #define JPEG_CGC_GATE__JPEG_ENC__SHIFT 0x2 1346 #define JPEG_CGC_GATE__JMCIF__SHIFT 0x3 1347 #define JPEG_CGC_GATE__JRBBM__SHIFT 0x4 1348 #define JPEG_CGC_GATE__JPEG_DEC_MASK 0x00000001L 1349 #define JPEG_CGC_GATE__JPEG2_DEC_MASK 0x00000002L 1350 #define JPEG_CGC_GATE__JPEG_ENC_MASK 0x00000004L 1351 #define JPEG_CGC_GATE__JMCIF_MASK 0x00000008L 1352 #define JPEG_CGC_GATE__JRBBM_MASK 0x00000010L 1353 //JPEG_CGC_CTRL 1354 #define JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 1355 #define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x1 1356 #define JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x5 1357 #define JPEG_CGC_CTRL__DYN_OCLK_RAMP_EN__SHIFT 0xa 1358 #define JPEG_CGC_CTRL__DYN_RCLK_RAMP_EN__SHIFT 0xb 1359 #define JPEG_CGC_CTRL__GATER_DIV_ID__SHIFT 0xc 1360 #define JPEG_CGC_CTRL__JPEG_DEC_MODE__SHIFT 0x10 1361 #define JPEG_CGC_CTRL__JPEG2_DEC_MODE__SHIFT 0x11 1362 #define JPEG_CGC_CTRL__JPEG_ENC_MODE__SHIFT 0x12 1363 #define JPEG_CGC_CTRL__JMCIF_MODE__SHIFT 0x13 1364 #define JPEG_CGC_CTRL__JRBBM_MODE__SHIFT 0x14 1365 #define JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L 1366 #define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000001EL 1367 #define JPEG_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000003E0L 1368 #define JPEG_CGC_CTRL__DYN_OCLK_RAMP_EN_MASK 0x00000400L 1369 #define JPEG_CGC_CTRL__DYN_RCLK_RAMP_EN_MASK 0x00000800L 1370 #define JPEG_CGC_CTRL__GATER_DIV_ID_MASK 0x00007000L 1371 #define JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK 0x00010000L 1372 #define JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK 0x00020000L 1373 #define JPEG_CGC_CTRL__JPEG_ENC_MODE_MASK 0x00040000L 1374 #define JPEG_CGC_CTRL__JMCIF_MODE_MASK 0x00080000L 1375 #define JPEG_CGC_CTRL__JRBBM_MODE_MASK 0x00100000L 1376 //JPEG_CGC_STATUS 1377 #define JPEG_CGC_STATUS__JPEG_DEC_VCLK_ACTIVE__SHIFT 0x0 1378 #define JPEG_CGC_STATUS__JPEG_DEC_SCLK_ACTIVE__SHIFT 0x1 1379 #define JPEG_CGC_STATUS__JPEG2_DEC_VCLK_ACTIVE__SHIFT 0x2 1380 #define JPEG_CGC_STATUS__JPEG2_DEC_SCLK_ACTIVE__SHIFT 0x3 1381 #define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE__SHIFT 0x4 1382 #define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE__SHIFT 0x5 1383 #define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE__SHIFT 0x6 1384 #define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE__SHIFT 0x7 1385 #define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE__SHIFT 0x8 1386 #define JPEG_CGC_STATUS__JPEG_DEC_VCLK_ACTIVE_MASK 0x00000001L 1387 #define JPEG_CGC_STATUS__JPEG_DEC_SCLK_ACTIVE_MASK 0x00000002L 1388 #define JPEG_CGC_STATUS__JPEG2_DEC_VCLK_ACTIVE_MASK 0x00000004L 1389 #define JPEG_CGC_STATUS__JPEG2_DEC_SCLK_ACTIVE_MASK 0x00000008L 1390 #define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE_MASK 0x00000010L 1391 #define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE_MASK 0x00000020L 1392 #define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE_MASK 0x00000040L 1393 #define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE_MASK 0x00000080L 1394 #define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE_MASK 0x00000100L 1395 //JPEG_COMN_CGC_MEM_CTRL 1396 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN__SHIFT 0x0 1397 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN__SHIFT 0x1 1398 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN__SHIFT 0x2 1399 #define JPEG_COMN_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10 1400 #define JPEG_COMN_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14 1401 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN_MASK 0x00000001L 1402 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN_MASK 0x00000002L 1403 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN_MASK 0x00000004L 1404 #define JPEG_COMN_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0x000F0000L 1405 #define JPEG_COMN_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0x00F00000L 1406 //JPEG_DEC_CGC_MEM_CTRL 1407 #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_LS_EN__SHIFT 0x0 1408 #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_DS_EN__SHIFT 0x1 1409 #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_SD_EN__SHIFT 0x2 1410 #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_LS_EN_MASK 0x00000001L 1411 #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_DS_EN_MASK 0x00000002L 1412 #define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_SD_EN_MASK 0x00000004L 1413 //JPEG2_DEC_CGC_MEM_CTRL 1414 #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_EN__SHIFT 0x0 1415 #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_DS_EN__SHIFT 0x1 1416 #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_SD_EN__SHIFT 0x2 1417 #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_EN_MASK 0x00000001L 1418 #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_DS_EN_MASK 0x00000002L 1419 #define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_SD_EN_MASK 0x00000004L 1420 //JPEG_ENC_CGC_MEM_CTRL 1421 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN__SHIFT 0x0 1422 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN__SHIFT 0x1 1423 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN__SHIFT 0x2 1424 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN_MASK 0x00000001L 1425 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN_MASK 0x00000002L 1426 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN_MASK 0x00000004L 1427 //JPEG_SOFT_RESET2 1428 #define JPEG_SOFT_RESET2__ATOMIC_SOFT_RESET__SHIFT 0x0 1429 #define JPEG_SOFT_RESET2__ATOMIC_SOFT_RESET_MASK 0x00000001L 1430 //JPEG_PERF_BANK_CONF 1431 #define JPEG_PERF_BANK_CONF__RESET__SHIFT 0x0 1432 #define JPEG_PERF_BANK_CONF__PEEK__SHIFT 0x8 1433 #define JPEG_PERF_BANK_CONF__CONCATENATE__SHIFT 0x10 1434 #define JPEG_PERF_BANK_CONF__RESET_MASK 0x0000000FL 1435 #define JPEG_PERF_BANK_CONF__PEEK_MASK 0x00000F00L 1436 #define JPEG_PERF_BANK_CONF__CONCATENATE_MASK 0x00030000L 1437 //JPEG_PERF_BANK_EVENT_SEL 1438 #define JPEG_PERF_BANK_EVENT_SEL__SEL0__SHIFT 0x0 1439 #define JPEG_PERF_BANK_EVENT_SEL__SEL1__SHIFT 0x8 1440 #define JPEG_PERF_BANK_EVENT_SEL__SEL2__SHIFT 0x10 1441 #define JPEG_PERF_BANK_EVENT_SEL__SEL3__SHIFT 0x18 1442 #define JPEG_PERF_BANK_EVENT_SEL__SEL0_MASK 0x000000FFL 1443 #define JPEG_PERF_BANK_EVENT_SEL__SEL1_MASK 0x0000FF00L 1444 #define JPEG_PERF_BANK_EVENT_SEL__SEL2_MASK 0x00FF0000L 1445 #define JPEG_PERF_BANK_EVENT_SEL__SEL3_MASK 0xFF000000L 1446 //JPEG_PERF_BANK_COUNT0 1447 #define JPEG_PERF_BANK_COUNT0__COUNT__SHIFT 0x0 1448 #define JPEG_PERF_BANK_COUNT0__COUNT_MASK 0xFFFFFFFFL 1449 //JPEG_PERF_BANK_COUNT1 1450 #define JPEG_PERF_BANK_COUNT1__COUNT__SHIFT 0x0 1451 #define JPEG_PERF_BANK_COUNT1__COUNT_MASK 0xFFFFFFFFL 1452 //JPEG_PERF_BANK_COUNT2 1453 #define JPEG_PERF_BANK_COUNT2__COUNT__SHIFT 0x0 1454 #define JPEG_PERF_BANK_COUNT2__COUNT_MASK 0xFFFFFFFFL 1455 //JPEG_PERF_BANK_COUNT3 1456 #define JPEG_PERF_BANK_COUNT3__COUNT__SHIFT 0x0 1457 #define JPEG_PERF_BANK_COUNT3__COUNT_MASK 0xFFFFFFFFL 1458 1459 1460 // addressBlock: uvd0_uvd_pg_dec 1461 //UVD_PGFSM_CONFIG 1462 #define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 0x0 1463 #define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 0x2 1464 #define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 0x4 1465 #define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 0x6 1466 #define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 0x8 1467 #define UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 0xa 1468 #define UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 0xc 1469 #define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 0xe 1470 #define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 0x10 1471 #define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 0x12 1472 #define UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT 0x14 1473 #define UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT 0x16 1474 #define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG_MASK 0x00000003L 1475 #define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG_MASK 0x0000000CL 1476 #define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG_MASK 0x00000030L 1477 #define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG_MASK 0x000000C0L 1478 #define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG_MASK 0x00000300L 1479 #define UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG_MASK 0x00000C00L 1480 #define UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG_MASK 0x00003000L 1481 #define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG_MASK 0x0000C000L 1482 #define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG_MASK 0x00030000L 1483 #define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG_MASK 0x000C0000L 1484 #define UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG_MASK 0x00300000L 1485 #define UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG_MASK 0x00C00000L 1486 //UVD_PGFSM_STATUS 1487 #define UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 0x0 1488 #define UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 0x2 1489 #define UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 0x4 1490 #define UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 0x6 1491 #define UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 0x8 1492 #define UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT 0xa 1493 #define UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT 0xc 1494 #define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 0xe 1495 #define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 0x10 1496 #define UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 0x12 1497 #define UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT 0x14 1498 #define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT 0x16 1499 #define UVD_PGFSM_STATUS__UVDM_PWR_STATUS_MASK 0x00000003L 1500 #define UVD_PGFSM_STATUS__UVDU_PWR_STATUS_MASK 0x0000000CL 1501 #define UVD_PGFSM_STATUS__UVDF_PWR_STATUS_MASK 0x00000030L 1502 #define UVD_PGFSM_STATUS__UVDC_PWR_STATUS_MASK 0x000000C0L 1503 #define UVD_PGFSM_STATUS__UVDB_PWR_STATUS_MASK 0x00000300L 1504 #define UVD_PGFSM_STATUS__UVDIL_PWR_STATUS_MASK 0x00000C00L 1505 #define UVD_PGFSM_STATUS__UVDIR_PWR_STATUS_MASK 0x00003000L 1506 #define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS_MASK 0x0000C000L 1507 #define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS_MASK 0x00030000L 1508 #define UVD_PGFSM_STATUS__UVDE_PWR_STATUS_MASK 0x000C0000L 1509 #define UVD_PGFSM_STATUS__UVDW_PWR_STATUS_MASK 0x00300000L 1510 #define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK 0x00C00000L 1511 //UVD_POWER_STATUS 1512 #define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0 1513 #define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2 1514 #define UVD_POWER_STATUS__UVD_CG_MODE__SHIFT 0x4 1515 #define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8 1516 #define UVD_POWER_STATUS__RBC_SNOOP_DIS__SHIFT 0x9 1517 #define UVD_POWER_STATUS__SW_RB_SNOOP_DIS__SHIFT 0xb 1518 #define UVD_POWER_STATUS__STALL_DPG_POWER_UP__SHIFT 0x1f 1519 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000003L 1520 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L 1521 #define UVD_POWER_STATUS__UVD_CG_MODE_MASK 0x00000030L 1522 #define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L 1523 #define UVD_POWER_STATUS__RBC_SNOOP_DIS_MASK 0x00000200L 1524 #define UVD_POWER_STATUS__SW_RB_SNOOP_DIS_MASK 0x00000800L 1525 #define UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK 0x80000000L 1526 //UVD_PG_IND_INDEX 1527 #define UVD_PG_IND_INDEX__INDEX__SHIFT 0x0 1528 #define UVD_PG_IND_INDEX__INDEX_MASK 0x0000003FL 1529 //UVD_PG_IND_DATA 1530 #define UVD_PG_IND_DATA__DATA__SHIFT 0x0 1531 #define UVD_PG_IND_DATA__DATA_MASK 0xFFFFFFFFL 1532 //CC_UVD_HARVESTING 1533 #define CC_UVD_HARVESTING__MMSCH_DISABLE__SHIFT 0x0 1534 #define CC_UVD_HARVESTING__UVD_DISABLE__SHIFT 0x1 1535 #define CC_UVD_HARVESTING__MMSCH_DISABLE_MASK 0x00000001L 1536 #define CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L 1537 //UVD_JPEG_POWER_STATUS 1538 #define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS__SHIFT 0x0 1539 #define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE__SHIFT 0x4 1540 #define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS__SHIFT 0x8 1541 #define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS__SHIFT 0x9 1542 #define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP__SHIFT 0x1f 1543 #define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK 0x00000001L 1544 #define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK 0x00000010L 1545 #define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS_MASK 0x00000100L 1546 #define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS_MASK 0x00000200L 1547 #define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP_MASK 0x80000000L 1548 //UVD_DPG_LMA_CTL 1549 #define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0 1550 #define UVD_DPG_LMA_CTL__MASK_EN__SHIFT 0x1 1551 #define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT__SHIFT 0x2 1552 #define UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT 0x4 1553 #define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0x10 1554 #define UVD_DPG_LMA_CTL__READ_WRITE_MASK 0x00000001L 1555 #define UVD_DPG_LMA_CTL__MASK_EN_MASK 0x00000002L 1556 #define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT_MASK 0x00000004L 1557 #define UVD_DPG_LMA_CTL__SRAM_SEL_MASK 0x00000010L 1558 #define UVD_DPG_LMA_CTL__READ_WRITE_ADDR_MASK 0xFFFF0000L 1559 //UVD_DPG_LMA_DATA 1560 #define UVD_DPG_LMA_DATA__LMA_DATA__SHIFT 0x0 1561 #define UVD_DPG_LMA_DATA__LMA_DATA_MASK 0xFFFFFFFFL 1562 //UVD_DPG_LMA_MASK 1563 #define UVD_DPG_LMA_MASK__LMA_MASK__SHIFT 0x0 1564 #define UVD_DPG_LMA_MASK__LMA_MASK_MASK 0xFFFFFFFFL 1565 //UVD_DPG_PAUSE 1566 #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ__SHIFT 0x0 1567 #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK__SHIFT 0x1 1568 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ__SHIFT 0x2 1569 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK__SHIFT 0x3 1570 #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK 0x00000001L 1571 #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK 0x00000002L 1572 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK 0x00000004L 1573 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK 0x00000008L 1574 //UVD_SCRATCH1 1575 #define UVD_SCRATCH1__SCRATCH1_DATA__SHIFT 0x0 1576 #define UVD_SCRATCH1__SCRATCH1_DATA_MASK 0xFFFFFFFFL 1577 //UVD_SCRATCH2 1578 #define UVD_SCRATCH2__SCRATCH2_DATA__SHIFT 0x0 1579 #define UVD_SCRATCH2__SCRATCH2_DATA_MASK 0xFFFFFFFFL 1580 //UVD_SCRATCH3 1581 #define UVD_SCRATCH3__SCRATCH3_DATA__SHIFT 0x0 1582 #define UVD_SCRATCH3__SCRATCH3_DATA_MASK 0xFFFFFFFFL 1583 //UVD_SCRATCH4 1584 #define UVD_SCRATCH4__SCRATCH4_DATA__SHIFT 0x0 1585 #define UVD_SCRATCH4__SCRATCH4_DATA_MASK 0xFFFFFFFFL 1586 //UVD_SCRATCH5 1587 #define UVD_SCRATCH5__SCRATCH5_DATA__SHIFT 0x0 1588 #define UVD_SCRATCH5__SCRATCH5_DATA_MASK 0xFFFFFFFFL 1589 //UVD_SCRATCH6 1590 #define UVD_SCRATCH6__SCRATCH6_DATA__SHIFT 0x0 1591 #define UVD_SCRATCH6__SCRATCH6_DATA_MASK 0xFFFFFFFFL 1592 //UVD_SCRATCH7 1593 #define UVD_SCRATCH7__SCRATCH7_DATA__SHIFT 0x0 1594 #define UVD_SCRATCH7__SCRATCH7_DATA_MASK 0xFFFFFFFFL 1595 //UVD_SCRATCH8 1596 #define UVD_SCRATCH8__SCRATCH8_DATA__SHIFT 0x0 1597 #define UVD_SCRATCH8__SCRATCH8_DATA_MASK 0xFFFFFFFFL 1598 //UVD_SCRATCH9 1599 #define UVD_SCRATCH9__SCRATCH9_DATA__SHIFT 0x0 1600 #define UVD_SCRATCH9__SCRATCH9_DATA_MASK 0xFFFFFFFFL 1601 //UVD_SCRATCH10 1602 #define UVD_SCRATCH10__SCRATCH10_DATA__SHIFT 0x0 1603 #define UVD_SCRATCH10__SCRATCH10_DATA_MASK 0xFFFFFFFFL 1604 //UVD_SCRATCH11 1605 #define UVD_SCRATCH11__SCRATCH11_DATA__SHIFT 0x0 1606 #define UVD_SCRATCH11__SCRATCH11_DATA_MASK 0xFFFFFFFFL 1607 //UVD_SCRATCH12 1608 #define UVD_SCRATCH12__SCRATCH12_DATA__SHIFT 0x0 1609 #define UVD_SCRATCH12__SCRATCH12_DATA_MASK 0xFFFFFFFFL 1610 //UVD_SCRATCH13 1611 #define UVD_SCRATCH13__SCRATCH13_DATA__SHIFT 0x0 1612 #define UVD_SCRATCH13__SCRATCH13_DATA_MASK 0xFFFFFFFFL 1613 //UVD_SCRATCH14 1614 #define UVD_SCRATCH14__SCRATCH14_DATA__SHIFT 0x0 1615 #define UVD_SCRATCH14__SCRATCH14_DATA_MASK 0xFFFFFFFFL 1616 //UVD_FREE_COUNTER_REG 1617 #define UVD_FREE_COUNTER_REG__FREE_COUNTER__SHIFT 0x0 1618 #define UVD_FREE_COUNTER_REG__FREE_COUNTER_MASK 0xFFFFFFFFL 1619 //UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 1620 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1621 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1622 //UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 1623 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1624 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1625 //UVD_DPG_VCPU_CACHE_OFFSET0 1626 #define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 1627 #define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x01FFFFFFL 1628 //UVD_DPG_LMI_VCPU_CACHE_VMID 1629 #define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0 1630 #define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL 1631 //UVD_PF_STATUS 1632 #define UVD_PF_STATUS__JPEG_PF_OCCURED__SHIFT 0x0 1633 #define UVD_PF_STATUS__NJ_PF_OCCURED__SHIFT 0x1 1634 #define UVD_PF_STATUS__ENCODER0_PF_OCCURED__SHIFT 0x2 1635 #define UVD_PF_STATUS__ENCODER1_PF_OCCURED__SHIFT 0x3 1636 #define UVD_PF_STATUS__ENCODER2_PF_OCCURED__SHIFT 0x4 1637 #define UVD_PF_STATUS__ENCODER3_PF_OCCURED__SHIFT 0x5 1638 #define UVD_PF_STATUS__ENCODER4_PF_OCCURED__SHIFT 0x6 1639 #define UVD_PF_STATUS__EJPEG_PF_OCCURED__SHIFT 0x7 1640 #define UVD_PF_STATUS__JPEG_PF_CLEAR__SHIFT 0x8 1641 #define UVD_PF_STATUS__NJ_PF_CLEAR__SHIFT 0x9 1642 #define UVD_PF_STATUS__ENCODER0_PF_CLEAR__SHIFT 0xa 1643 #define UVD_PF_STATUS__ENCODER1_PF_CLEAR__SHIFT 0xb 1644 #define UVD_PF_STATUS__ENCODER2_PF_CLEAR__SHIFT 0xc 1645 #define UVD_PF_STATUS__ENCODER3_PF_CLEAR__SHIFT 0xd 1646 #define UVD_PF_STATUS__ENCODER4_PF_CLEAR__SHIFT 0xe 1647 #define UVD_PF_STATUS__EJPEG_PF_CLEAR__SHIFT 0xf 1648 #define UVD_PF_STATUS__NJ_ATM_PF_OCCURED__SHIFT 0x10 1649 #define UVD_PF_STATUS__DJ_ATM_PF_OCCURED__SHIFT 0x11 1650 #define UVD_PF_STATUS__EJ_ATM_PF_OCCURED__SHIFT 0x12 1651 #define UVD_PF_STATUS__JPEG_PF_OCCURED_MASK 0x00000001L 1652 #define UVD_PF_STATUS__NJ_PF_OCCURED_MASK 0x00000002L 1653 #define UVD_PF_STATUS__ENCODER0_PF_OCCURED_MASK 0x00000004L 1654 #define UVD_PF_STATUS__ENCODER1_PF_OCCURED_MASK 0x00000008L 1655 #define UVD_PF_STATUS__ENCODER2_PF_OCCURED_MASK 0x00000010L 1656 #define UVD_PF_STATUS__ENCODER3_PF_OCCURED_MASK 0x00000020L 1657 #define UVD_PF_STATUS__ENCODER4_PF_OCCURED_MASK 0x00000040L 1658 #define UVD_PF_STATUS__EJPEG_PF_OCCURED_MASK 0x00000080L 1659 #define UVD_PF_STATUS__JPEG_PF_CLEAR_MASK 0x00000100L 1660 #define UVD_PF_STATUS__NJ_PF_CLEAR_MASK 0x00000200L 1661 #define UVD_PF_STATUS__ENCODER0_PF_CLEAR_MASK 0x00000400L 1662 #define UVD_PF_STATUS__ENCODER1_PF_CLEAR_MASK 0x00000800L 1663 #define UVD_PF_STATUS__ENCODER2_PF_CLEAR_MASK 0x00001000L 1664 #define UVD_PF_STATUS__ENCODER3_PF_CLEAR_MASK 0x00002000L 1665 #define UVD_PF_STATUS__ENCODER4_PF_CLEAR_MASK 0x00004000L 1666 #define UVD_PF_STATUS__EJPEG_PF_CLEAR_MASK 0x00008000L 1667 #define UVD_PF_STATUS__NJ_ATM_PF_OCCURED_MASK 0x00010000L 1668 #define UVD_PF_STATUS__DJ_ATM_PF_OCCURED_MASK 0x00020000L 1669 #define UVD_PF_STATUS__EJ_ATM_PF_OCCURED_MASK 0x00040000L 1670 //UVD_DPG_CLK_EN_VCPU_REPORT 1671 #define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN__SHIFT 0x0 1672 #define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT__SHIFT 0x1 1673 #define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN_MASK 0x00000001L 1674 #define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT_MASK 0x000000FEL 1675 //UVD_GFX8_ADDR_CONFIG 1676 #define UVD_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 1677 #define UVD_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L 1678 //UVD_GFX10_ADDR_CONFIG 1679 #define UVD_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 1680 #define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 1681 #define UVD_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 1682 #define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 1683 #define UVD_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 1684 #define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 1685 #define UVD_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 1686 #define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 1687 //UVD_GPCNT2_CNTL 1688 #define UVD_GPCNT2_CNTL__CLR__SHIFT 0x0 1689 #define UVD_GPCNT2_CNTL__START__SHIFT 0x1 1690 #define UVD_GPCNT2_CNTL__COUNTUP__SHIFT 0x2 1691 #define UVD_GPCNT2_CNTL__CLR_MASK 0x00000001L 1692 #define UVD_GPCNT2_CNTL__START_MASK 0x00000002L 1693 #define UVD_GPCNT2_CNTL__COUNTUP_MASK 0x00000004L 1694 //UVD_GPCNT2_TARGET_LOWER 1695 #define UVD_GPCNT2_TARGET_LOWER__TARGET__SHIFT 0x0 1696 #define UVD_GPCNT2_TARGET_LOWER__TARGET_MASK 0xFFFFFFFFL 1697 //UVD_GPCNT2_STATUS_LOWER 1698 #define UVD_GPCNT2_STATUS_LOWER__COUNT__SHIFT 0x0 1699 #define UVD_GPCNT2_STATUS_LOWER__COUNT_MASK 0xFFFFFFFFL 1700 //UVD_GPCNT2_TARGET_UPPER 1701 #define UVD_GPCNT2_TARGET_UPPER__TARGET__SHIFT 0x0 1702 #define UVD_GPCNT2_TARGET_UPPER__TARGET_MASK 0x0000FFFFL 1703 //UVD_GPCNT2_STATUS_UPPER 1704 #define UVD_GPCNT2_STATUS_UPPER__COUNT__SHIFT 0x0 1705 #define UVD_GPCNT2_STATUS_UPPER__COUNT_MASK 0x0000FFFFL 1706 //UVD_GPCNT3_CNTL 1707 #define UVD_GPCNT3_CNTL__CLR__SHIFT 0x0 1708 #define UVD_GPCNT3_CNTL__START__SHIFT 0x1 1709 #define UVD_GPCNT3_CNTL__COUNTUP__SHIFT 0x2 1710 #define UVD_GPCNT3_CNTL__FREQ__SHIFT 0x3 1711 #define UVD_GPCNT3_CNTL__DIV__SHIFT 0xa 1712 #define UVD_GPCNT3_CNTL__CLR_MASK 0x00000001L 1713 #define UVD_GPCNT3_CNTL__START_MASK 0x00000002L 1714 #define UVD_GPCNT3_CNTL__COUNTUP_MASK 0x00000004L 1715 #define UVD_GPCNT3_CNTL__FREQ_MASK 0x000003F8L 1716 #define UVD_GPCNT3_CNTL__DIV_MASK 0x0001FC00L 1717 //UVD_GPCNT3_TARGET_LOWER 1718 #define UVD_GPCNT3_TARGET_LOWER__TARGET__SHIFT 0x0 1719 #define UVD_GPCNT3_TARGET_LOWER__TARGET_MASK 0xFFFFFFFFL 1720 //UVD_GPCNT3_STATUS_LOWER 1721 #define UVD_GPCNT3_STATUS_LOWER__COUNT__SHIFT 0x0 1722 #define UVD_GPCNT3_STATUS_LOWER__COUNT_MASK 0xFFFFFFFFL 1723 //UVD_GPCNT3_TARGET_UPPER 1724 #define UVD_GPCNT3_TARGET_UPPER__TARGET__SHIFT 0x0 1725 #define UVD_GPCNT3_TARGET_UPPER__TARGET_MASK 0x0000FFFFL 1726 //UVD_GPCNT3_STATUS_UPPER 1727 #define UVD_GPCNT3_STATUS_UPPER__COUNT__SHIFT 0x0 1728 #define UVD_GPCNT3_STATUS_UPPER__COUNT_MASK 0x0000FFFFL 1729 //UVD_TSC_LOWER 1730 #define UVD_TSC_LOWER__COUNT__SHIFT 0x0 1731 #define UVD_TSC_LOWER__COUNT_MASK 0xFFFFFFFFL 1732 //UVD_TSC_UPPER 1733 #define UVD_TSC_UPPER__COUNT__SHIFT 0x0 1734 #define UVD_TSC_UPPER__COUNT_MASK 0x00FFFFFFL 1735 1736 1737 // addressBlock: uvd0_uvddec 1738 //UVD_SEMA_CNTL 1739 #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0 1740 #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1 1741 #define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x00000001L 1742 #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x00000002L 1743 //UVD_RB_RPTR3 1744 #define UVD_RB_RPTR3__RB_RPTR__SHIFT 0x4 1745 #define UVD_RB_RPTR3__RB_RPTR_MASK 0x007FFFF0L 1746 //UVD_RB_WPTR3 1747 #define UVD_RB_WPTR3__RB_WPTR__SHIFT 0x4 1748 #define UVD_RB_WPTR3__RB_WPTR_MASK 0x007FFFF0L 1749 //UVD_RB_BASE_LO3 1750 #define UVD_RB_BASE_LO3__RB_BASE_LO__SHIFT 0x6 1751 #define UVD_RB_BASE_LO3__RB_BASE_LO_MASK 0xFFFFFFC0L 1752 //UVD_RB_BASE_HI3 1753 #define UVD_RB_BASE_HI3__RB_BASE_HI__SHIFT 0x0 1754 #define UVD_RB_BASE_HI3__RB_BASE_HI_MASK 0xFFFFFFFFL 1755 //UVD_RB_SIZE3 1756 #define UVD_RB_SIZE3__RB_SIZE__SHIFT 0x4 1757 #define UVD_RB_SIZE3__RB_SIZE_MASK 0x007FFFF0L 1758 //UVD_RB_ARB_CTRL 1759 #define UVD_RB_ARB_CTRL__SRBM_DROP__SHIFT 0x0 1760 #define UVD_RB_ARB_CTRL__SRBM_DIS__SHIFT 0x1 1761 #define UVD_RB_ARB_CTRL__VCPU_DROP__SHIFT 0x2 1762 #define UVD_RB_ARB_CTRL__VCPU_DIS__SHIFT 0x3 1763 #define UVD_RB_ARB_CTRL__RBC_DROP__SHIFT 0x4 1764 #define UVD_RB_ARB_CTRL__RBC_DIS__SHIFT 0x5 1765 #define UVD_RB_ARB_CTRL__FWOFLD_DROP__SHIFT 0x6 1766 #define UVD_RB_ARB_CTRL__FWOFLD_DIS__SHIFT 0x7 1767 #define UVD_RB_ARB_CTRL__FAST_PATH_EN__SHIFT 0x8 1768 #define UVD_RB_ARB_CTRL__SRBM_DROP_MASK 0x00000001L 1769 #define UVD_RB_ARB_CTRL__SRBM_DIS_MASK 0x00000002L 1770 #define UVD_RB_ARB_CTRL__VCPU_DROP_MASK 0x00000004L 1771 #define UVD_RB_ARB_CTRL__VCPU_DIS_MASK 0x00000008L 1772 #define UVD_RB_ARB_CTRL__RBC_DROP_MASK 0x00000010L 1773 #define UVD_RB_ARB_CTRL__RBC_DIS_MASK 0x00000020L 1774 #define UVD_RB_ARB_CTRL__FWOFLD_DROP_MASK 0x00000040L 1775 #define UVD_RB_ARB_CTRL__FWOFLD_DIS_MASK 0x00000080L 1776 #define UVD_RB_ARB_CTRL__FAST_PATH_EN_MASK 0x00000100L 1777 //UVD_LMI_LAT_CTRL 1778 #define UVD_LMI_LAT_CTRL__SCALE__SHIFT 0x0 1779 #define UVD_LMI_LAT_CTRL__MAX_START__SHIFT 0x8 1780 #define UVD_LMI_LAT_CTRL__MIN_START__SHIFT 0x9 1781 #define UVD_LMI_LAT_CTRL__AVG_START__SHIFT 0xa 1782 #define UVD_LMI_LAT_CTRL__PERFMON_SYNC__SHIFT 0xb 1783 #define UVD_LMI_LAT_CTRL__SKIP__SHIFT 0x10 1784 #define UVD_LMI_LAT_CTRL__SCALE_MASK 0x000000FFL 1785 #define UVD_LMI_LAT_CTRL__MAX_START_MASK 0x00000100L 1786 #define UVD_LMI_LAT_CTRL__MIN_START_MASK 0x00000200L 1787 #define UVD_LMI_LAT_CTRL__AVG_START_MASK 0x00000400L 1788 #define UVD_LMI_LAT_CTRL__PERFMON_SYNC_MASK 0x00000800L 1789 #define UVD_LMI_LAT_CTRL__SKIP_MASK 0x000F0000L 1790 //UVD_LMI_LAT_CNTR 1791 #define UVD_LMI_LAT_CNTR__MAX_LAT__SHIFT 0x0 1792 #define UVD_LMI_LAT_CNTR__MIN_LAT__SHIFT 0x8 1793 #define UVD_LMI_LAT_CNTR__MAX_LAT_MASK 0x000000FFL 1794 #define UVD_LMI_LAT_CNTR__MIN_LAT_MASK 0x0000FF00L 1795 //UVD_LMI_AVG_LAT_CNTR 1796 #define UVD_LMI_AVG_LAT_CNTR__ENV_LOW__SHIFT 0x0 1797 #define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH__SHIFT 0x8 1798 #define UVD_LMI_AVG_LAT_CNTR__ENV_HIT__SHIFT 0x10 1799 #define UVD_LMI_AVG_LAT_CNTR__ENV_LOW_MASK 0x000000FFL 1800 #define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH_MASK 0x0000FF00L 1801 #define UVD_LMI_AVG_LAT_CNTR__ENV_HIT_MASK 0xFFFF0000L 1802 //UVD_SOFT_RESET2 1803 #define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET__SHIFT 0x0 1804 #define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS__SHIFT 0x10 1805 #define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS__SHIFT 0x11 1806 #define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET_MASK 0x00000001L 1807 #define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS_MASK 0x00010000L 1808 #define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS_MASK 0x00020000L 1809 //UVD_LMI_SPH 1810 #define UVD_LMI_SPH__ADDR__SHIFT 0x0 1811 #define UVD_LMI_SPH__STS__SHIFT 0x1c 1812 #define UVD_LMI_SPH__STS_VALID__SHIFT 0x1e 1813 #define UVD_LMI_SPH__STS_OVERFLOW__SHIFT 0x1f 1814 #define UVD_LMI_SPH__ADDR_MASK 0x0FFFFFFFL 1815 #define UVD_LMI_SPH__STS_MASK 0x30000000L 1816 #define UVD_LMI_SPH__STS_VALID_MASK 0x40000000L 1817 #define UVD_LMI_SPH__STS_OVERFLOW_MASK 0x80000000L 1818 //UVD_CTX_INDEX 1819 #define UVD_CTX_INDEX__INDEX__SHIFT 0x0 1820 #define UVD_CTX_INDEX__INDEX_MASK 0x000001FFL 1821 //UVD_CTX_DATA 1822 #define UVD_CTX_DATA__DATA__SHIFT 0x0 1823 #define UVD_CTX_DATA__DATA_MASK 0xFFFFFFFFL 1824 //UVD_CGC_GATE 1825 #define UVD_CGC_GATE__SYS__SHIFT 0x0 1826 #define UVD_CGC_GATE__UDEC__SHIFT 0x1 1827 #define UVD_CGC_GATE__MPEG2__SHIFT 0x2 1828 #define UVD_CGC_GATE__REGS__SHIFT 0x3 1829 #define UVD_CGC_GATE__RBC__SHIFT 0x4 1830 #define UVD_CGC_GATE__LMI_MC__SHIFT 0x5 1831 #define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6 1832 #define UVD_CGC_GATE__IDCT__SHIFT 0x7 1833 #define UVD_CGC_GATE__MPRD__SHIFT 0x8 1834 #define UVD_CGC_GATE__MPC__SHIFT 0x9 1835 #define UVD_CGC_GATE__LBSI__SHIFT 0xa 1836 #define UVD_CGC_GATE__LRBBM__SHIFT 0xb 1837 #define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc 1838 #define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd 1839 #define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe 1840 #define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf 1841 #define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10 1842 #define UVD_CGC_GATE__WCB__SHIFT 0x11 1843 #define UVD_CGC_GATE__VCPU__SHIFT 0x12 1844 #define UVD_CGC_GATE__SCPU__SHIFT 0x13 1845 #define UVD_CGC_GATE__MMSCH__SHIFT 0x14 1846 #define UVD_CGC_GATE__SYS_MASK 0x00000001L 1847 #define UVD_CGC_GATE__UDEC_MASK 0x00000002L 1848 #define UVD_CGC_GATE__MPEG2_MASK 0x00000004L 1849 #define UVD_CGC_GATE__REGS_MASK 0x00000008L 1850 #define UVD_CGC_GATE__RBC_MASK 0x00000010L 1851 #define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L 1852 #define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L 1853 #define UVD_CGC_GATE__IDCT_MASK 0x00000080L 1854 #define UVD_CGC_GATE__MPRD_MASK 0x00000100L 1855 #define UVD_CGC_GATE__MPC_MASK 0x00000200L 1856 #define UVD_CGC_GATE__LBSI_MASK 0x00000400L 1857 #define UVD_CGC_GATE__LRBBM_MASK 0x00000800L 1858 #define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L 1859 #define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L 1860 #define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L 1861 #define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L 1862 #define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L 1863 #define UVD_CGC_GATE__WCB_MASK 0x00020000L 1864 #define UVD_CGC_GATE__VCPU_MASK 0x00040000L 1865 #define UVD_CGC_GATE__SCPU_MASK 0x00080000L 1866 #define UVD_CGC_GATE__MMSCH_MASK 0x00100000L 1867 //UVD_CGC_STATUS 1868 #define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0 1869 #define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1 1870 #define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2 1871 #define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3 1872 #define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4 1873 #define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5 1874 #define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6 1875 #define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7 1876 #define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8 1877 #define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9 1878 #define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa 1879 #define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb 1880 #define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc 1881 #define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd 1882 #define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe 1883 #define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf 1884 #define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10 1885 #define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11 1886 #define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12 1887 #define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13 1888 #define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14 1889 #define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15 1890 #define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16 1891 #define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17 1892 #define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18 1893 #define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19 1894 #define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a 1895 #define UVD_CGC_STATUS__MMSCH_SCLK__SHIFT 0x1b 1896 #define UVD_CGC_STATUS__MMSCH_VCLK__SHIFT 0x1c 1897 #define UVD_CGC_STATUS__ALL_ENC_ACTIVE__SHIFT 0x1d 1898 #define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT 0x1f 1899 #define UVD_CGC_STATUS__SYS_SCLK_MASK 0x00000001L 1900 #define UVD_CGC_STATUS__SYS_DCLK_MASK 0x00000002L 1901 #define UVD_CGC_STATUS__SYS_VCLK_MASK 0x00000004L 1902 #define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x00000008L 1903 #define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x00000010L 1904 #define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x00000020L 1905 #define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x00000040L 1906 #define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x00000080L 1907 #define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x00000100L 1908 #define UVD_CGC_STATUS__REGS_SCLK_MASK 0x00000200L 1909 #define UVD_CGC_STATUS__REGS_VCLK_MASK 0x00000400L 1910 #define UVD_CGC_STATUS__RBC_SCLK_MASK 0x00000800L 1911 #define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x00001000L 1912 #define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x00002000L 1913 #define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x00004000L 1914 #define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x00008000L 1915 #define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x00010000L 1916 #define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x00020000L 1917 #define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x00040000L 1918 #define UVD_CGC_STATUS__MPC_SCLK_MASK 0x00080000L 1919 #define UVD_CGC_STATUS__MPC_DCLK_MASK 0x00100000L 1920 #define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x00200000L 1921 #define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x00400000L 1922 #define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x00800000L 1923 #define UVD_CGC_STATUS__WCB_SCLK_MASK 0x01000000L 1924 #define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x02000000L 1925 #define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x04000000L 1926 #define UVD_CGC_STATUS__MMSCH_SCLK_MASK 0x08000000L 1927 #define UVD_CGC_STATUS__MMSCH_VCLK_MASK 0x10000000L 1928 #define UVD_CGC_STATUS__ALL_ENC_ACTIVE_MASK 0x20000000L 1929 #define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK 0x80000000L 1930 //UVD_CGC_CTRL 1931 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 1932 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 1933 #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 1934 #define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb 1935 #define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc 1936 #define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd 1937 #define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe 1938 #define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf 1939 #define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10 1940 #define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11 1941 #define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12 1942 #define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13 1943 #define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14 1944 #define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15 1945 #define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16 1946 #define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17 1947 #define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18 1948 #define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19 1949 #define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a 1950 #define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b 1951 #define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c 1952 #define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d 1953 #define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e 1954 #define UVD_CGC_CTRL__MMSCH_MODE__SHIFT 0x1f 1955 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L 1956 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL 1957 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L 1958 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L 1959 #define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L 1960 #define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L 1961 #define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L 1962 #define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L 1963 #define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L 1964 #define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L 1965 #define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L 1966 #define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L 1967 #define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L 1968 #define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L 1969 #define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L 1970 #define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L 1971 #define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L 1972 #define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L 1973 #define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L 1974 #define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L 1975 #define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L 1976 #define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L 1977 #define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000L 1978 #define UVD_CGC_CTRL__MMSCH_MODE_MASK 0x80000000L 1979 //UVD_CGC_UDEC_STATUS 1980 #define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0 1981 #define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1 1982 #define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2 1983 #define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3 1984 #define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4 1985 #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 1986 #define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6 1987 #define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7 1988 #define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8 1989 #define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9 1990 #define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa 1991 #define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb 1992 #define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc 1993 #define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd 1994 #define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe 1995 #define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x00000001L 1996 #define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x00000002L 1997 #define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x00000004L 1998 #define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x00000008L 1999 #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x00000010L 2000 #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x00000020L 2001 #define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x00000040L 2002 #define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x00000080L 2003 #define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x00000100L 2004 #define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x00000200L 2005 #define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x00000400L 2006 #define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x00000800L 2007 #define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x00001000L 2008 #define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x00002000L 2009 #define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x00004000L 2010 //UVD_CXW_WR_INT_ID 2011 #define UVD_CXW_WR_INT_ID__ID__SHIFT 0x0 2012 #define UVD_CXW_WR_INT_ID__ID_MASK 0x000000FFL 2013 //UVD_CXW_WR_INT_CTX_ID 2014 #define UVD_CXW_WR_INT_CTX_ID__ID__SHIFT 0x0 2015 #define UVD_CXW_WR_INT_CTX_ID__ID_MASK 0x0FFFFFFFL 2016 //UVD_VCPU_INT_ROUTE 2017 #define UVD_VCPU_INT_ROUTE__DRV_FW_MSG__SHIFT 0x0 2018 #define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK__SHIFT 0x1 2019 #define UVD_VCPU_INT_ROUTE__VCPU_GPCOM__SHIFT 0x2 2020 #define UVD_VCPU_INT_ROUTE__DRV_FW_MSG_MASK 0x00000001L 2021 #define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK_MASK 0x00000002L 2022 #define UVD_VCPU_INT_ROUTE__VCPU_GPCOM_MASK 0x00000004L 2023 //UVD_GP_SCRATCH0 2024 #define UVD_GP_SCRATCH0__DATA__SHIFT 0x0 2025 #define UVD_GP_SCRATCH0__DATA_MASK 0xFFFFFFFFL 2026 //UVD_GP_SCRATCH1 2027 #define UVD_GP_SCRATCH1__DATA__SHIFT 0x0 2028 #define UVD_GP_SCRATCH1__DATA_MASK 0xFFFFFFFFL 2029 //UVD_GP_SCRATCH2 2030 #define UVD_GP_SCRATCH2__DATA__SHIFT 0x0 2031 #define UVD_GP_SCRATCH2__DATA_MASK 0xFFFFFFFFL 2032 //UVD_GP_SCRATCH3 2033 #define UVD_GP_SCRATCH3__DATA__SHIFT 0x0 2034 #define UVD_GP_SCRATCH3__DATA_MASK 0xFFFFFFFFL 2035 //UVD_GP_SCRATCH4 2036 #define UVD_GP_SCRATCH4__DATA__SHIFT 0x0 2037 #define UVD_GP_SCRATCH4__DATA_MASK 0xFFFFFFFFL 2038 //UVD_GP_SCRATCH5 2039 #define UVD_GP_SCRATCH5__DATA__SHIFT 0x0 2040 #define UVD_GP_SCRATCH5__DATA_MASK 0xFFFFFFFFL 2041 //UVD_GP_SCRATCH6 2042 #define UVD_GP_SCRATCH6__DATA__SHIFT 0x0 2043 #define UVD_GP_SCRATCH6__DATA_MASK 0xFFFFFFFFL 2044 //UVD_GP_SCRATCH7 2045 #define UVD_GP_SCRATCH7__DATA__SHIFT 0x0 2046 #define UVD_GP_SCRATCH7__DATA_MASK 0xFFFFFFFFL 2047 //UVD_LMI_VCPU_CACHE_VMID 2048 #define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0 2049 #define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL 2050 //UVD_LMI_CTRL2 2051 #define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0 2052 #define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1 2053 #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2 2054 #define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3 2055 #define UVD_LMI_CTRL2__CRC1_RESET__SHIFT 0x4 2056 #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7 2057 #define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 2058 #define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 2059 #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb 2060 #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd 2061 #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe 2062 #define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf 2063 #define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10 2064 #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11 2065 #define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP__SHIFT 0x19 2066 #define UVD_LMI_CTRL2__NJ_MIF_GATING__SHIFT 0x1a 2067 #define UVD_LMI_CTRL2__CRC1_SEL__SHIFT 0x1b 2068 #define UVD_LMI_CTRL2__SPH_DIS_MASK 0x00000001L 2069 #define UVD_LMI_CTRL2__STALL_ARB_MASK 0x00000002L 2070 #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L 2071 #define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x00000008L 2072 #define UVD_LMI_CTRL2__CRC1_RESET_MASK 0x00000010L 2073 #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x00000080L 2074 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L 2075 #define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x00000600L 2076 #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x00001800L 2077 #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x00002000L 2078 #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x00004000L 2079 #define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x00008000L 2080 #define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x00010000L 2081 #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x01FE0000L 2082 #define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP_MASK 0x02000000L 2083 #define UVD_LMI_CTRL2__NJ_MIF_GATING_MASK 0x04000000L 2084 #define UVD_LMI_CTRL2__CRC1_SEL_MASK 0xF8000000L 2085 //UVD_MASTINT_EN 2086 #define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 2087 #define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1 2088 #define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2 2089 #define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 2090 #define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L 2091 #define UVD_MASTINT_EN__VCPU_EN_MASK 0x00000002L 2092 #define UVD_MASTINT_EN__SYS_EN_MASK 0x00000004L 2093 #define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L 2094 //UVD_SYS_INT_EN 2095 #define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN__SHIFT 0x0 2096 #define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT 0x1 2097 #define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT 0x2 2098 #define UVD_SYS_INT_EN__CXW_WR_EN__SHIFT 0x3 2099 #define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT 0x6 2100 #define UVD_SYS_INT_EN__UVD_HOST_CXW_EN__SHIFT 0x8 2101 #define UVD_SYS_INT_EN__LBSI_EN__SHIFT 0xb 2102 #define UVD_SYS_INT_EN__UDEC_EN__SHIFT 0xc 2103 #define UVD_SYS_INT_EN__JOB_DONE_EN__SHIFT 0x10 2104 #define UVD_SYS_INT_EN__WPTR_IDLE_EN__SHIFT 0x15 2105 #define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_IDCT_EN__SHIFT 0x16 2106 #define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT 0x17 2107 #define UVD_SYS_INT_EN__IDCT_EN__SHIFT 0x18 2108 #define UVD_SYS_INT_EN__MPRD_EN__SHIFT 0x19 2109 #define UVD_SYS_INT_EN__FCS_EN__SHIFT 0x1a 2110 #define UVD_SYS_INT_EN__CLK_SWT_EN__SHIFT 0x1b 2111 #define UVD_SYS_INT_EN__MIF_HWINT_EN__SHIFT 0x1c 2112 #define UVD_SYS_INT_EN__MPRD_ERR_EN__SHIFT 0x1d 2113 #define UVD_SYS_INT_EN__AVM_INT_EN__SHIFT 0x1f 2114 #define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN_MASK 0x00000001L 2115 #define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK 0x00000002L 2116 #define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK 0x00000004L 2117 #define UVD_SYS_INT_EN__CXW_WR_EN_MASK 0x00000008L 2118 #define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK 0x00000040L 2119 #define UVD_SYS_INT_EN__UVD_HOST_CXW_EN_MASK 0x00000100L 2120 #define UVD_SYS_INT_EN__LBSI_EN_MASK 0x00000800L 2121 #define UVD_SYS_INT_EN__UDEC_EN_MASK 0x00001000L 2122 #define UVD_SYS_INT_EN__JOB_DONE_EN_MASK 0x00010000L 2123 #define UVD_SYS_INT_EN__WPTR_IDLE_EN_MASK 0x00200000L 2124 #define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_IDCT_EN_MASK 0x00400000L 2125 #define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK 0x00800000L 2126 #define UVD_SYS_INT_EN__IDCT_EN_MASK 0x01000000L 2127 #define UVD_SYS_INT_EN__MPRD_EN_MASK 0x02000000L 2128 #define UVD_SYS_INT_EN__FCS_EN_MASK 0x04000000L 2129 #define UVD_SYS_INT_EN__CLK_SWT_EN_MASK 0x08000000L 2130 #define UVD_SYS_INT_EN__MIF_HWINT_EN_MASK 0x10000000L 2131 #define UVD_SYS_INT_EN__MPRD_ERR_EN_MASK 0x20000000L 2132 #define UVD_SYS_INT_EN__AVM_INT_EN_MASK 0x80000000L 2133 //UVD_SYS_INT_STATUS 2134 #define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT__SHIFT 0x0 2135 #define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT__SHIFT 0x1 2136 #define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT__SHIFT 0x2 2137 #define UVD_SYS_INT_STATUS__CXW_WR_INT__SHIFT 0x3 2138 #define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT__SHIFT 0x6 2139 #define UVD_SYS_INT_STATUS__UVD_HOST_CXW_INT__SHIFT 0x8 2140 #define UVD_SYS_INT_STATUS__LBSI_INT__SHIFT 0xb 2141 #define UVD_SYS_INT_STATUS__UDEC_INT__SHIFT 0xc 2142 #define UVD_SYS_INT_STATUS__JOB_DONE_INT__SHIFT 0x10 2143 #define UVD_SYS_INT_STATUS__GPCOM_INT__SHIFT 0x12 2144 #define UVD_SYS_INT_STATUS__WPTR_IDLE_INT__SHIFT 0x15 2145 #define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_IDCT_INT__SHIFT 0x16 2146 #define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT__SHIFT 0x17 2147 #define UVD_SYS_INT_STATUS__IDCT_INT__SHIFT 0x18 2148 #define UVD_SYS_INT_STATUS__MPRD_INT__SHIFT 0x19 2149 #define UVD_SYS_INT_STATUS__FCS_INT__SHIFT 0x1a 2150 #define UVD_SYS_INT_STATUS__CLK_SWT_INT__SHIFT 0x1b 2151 #define UVD_SYS_INT_STATUS__MIF_HWINT__SHIFT 0x1c 2152 #define UVD_SYS_INT_STATUS__MPRD_ERR_INT__SHIFT 0x1d 2153 #define UVD_SYS_INT_STATUS__AVM_INT__SHIFT 0x1f 2154 #define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT_MASK 0x00000001L 2155 #define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT_MASK 0x00000002L 2156 #define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT_MASK 0x00000004L 2157 #define UVD_SYS_INT_STATUS__CXW_WR_INT_MASK 0x00000008L 2158 #define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT_MASK 0x00000040L 2159 #define UVD_SYS_INT_STATUS__UVD_HOST_CXW_INT_MASK 0x00000100L 2160 #define UVD_SYS_INT_STATUS__LBSI_INT_MASK 0x00000800L 2161 #define UVD_SYS_INT_STATUS__UDEC_INT_MASK 0x00001000L 2162 #define UVD_SYS_INT_STATUS__JOB_DONE_INT_MASK 0x00010000L 2163 #define UVD_SYS_INT_STATUS__GPCOM_INT_MASK 0x00040000L 2164 #define UVD_SYS_INT_STATUS__WPTR_IDLE_INT_MASK 0x00200000L 2165 #define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_IDCT_INT_MASK 0x00400000L 2166 #define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT_MASK 0x00800000L 2167 #define UVD_SYS_INT_STATUS__IDCT_INT_MASK 0x01000000L 2168 #define UVD_SYS_INT_STATUS__MPRD_INT_MASK 0x02000000L 2169 #define UVD_SYS_INT_STATUS__FCS_INT_MASK 0x04000000L 2170 #define UVD_SYS_INT_STATUS__CLK_SWT_INT_MASK 0x08000000L 2171 #define UVD_SYS_INT_STATUS__MIF_HWINT_MASK 0x10000000L 2172 #define UVD_SYS_INT_STATUS__MPRD_ERR_INT_MASK 0x20000000L 2173 #define UVD_SYS_INT_STATUS__AVM_INT_MASK 0x80000000L 2174 //UVD_SYS_INT_ACK 2175 #define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT 0x0 2176 #define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT 0x1 2177 #define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT 0x2 2178 #define UVD_SYS_INT_ACK__CXW_WR_ACK__SHIFT 0x3 2179 #define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT 0x6 2180 #define UVD_SYS_INT_ACK__UVD_HOST_CXW_ACK__SHIFT 0x8 2181 #define UVD_SYS_INT_ACK__LBSI_ACK__SHIFT 0xb 2182 #define UVD_SYS_INT_ACK__UDEC_ACK__SHIFT 0xc 2183 #define UVD_SYS_INT_ACK__JOB_DONE_ACK__SHIFT 0x10 2184 #define UVD_SYS_INT_ACK__WPTR_IDLE_ACK__SHIFT 0x15 2185 #define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_IDCT_ACK__SHIFT 0x16 2186 #define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT 0x17 2187 #define UVD_SYS_INT_ACK__IDCT_ACK__SHIFT 0x18 2188 #define UVD_SYS_INT_ACK__MPRD_ACK__SHIFT 0x19 2189 #define UVD_SYS_INT_ACK__FCS_ACK__SHIFT 0x1a 2190 #define UVD_SYS_INT_ACK__CLK_SWT_ACK__SHIFT 0x1b 2191 #define UVD_SYS_INT_ACK__MIF_HWINT_ACK__SHIFT 0x1c 2192 #define UVD_SYS_INT_ACK__MPRD_ERR_ACK__SHIFT 0x1d 2193 #define UVD_SYS_INT_ACK__AVM_INT_ACK__SHIFT 0x1f 2194 #define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK_MASK 0x00000001L 2195 #define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK 0x00000002L 2196 #define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK 0x00000004L 2197 #define UVD_SYS_INT_ACK__CXW_WR_ACK_MASK 0x00000008L 2198 #define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK 0x00000040L 2199 #define UVD_SYS_INT_ACK__UVD_HOST_CXW_ACK_MASK 0x00000100L 2200 #define UVD_SYS_INT_ACK__LBSI_ACK_MASK 0x00000800L 2201 #define UVD_SYS_INT_ACK__UDEC_ACK_MASK 0x00001000L 2202 #define UVD_SYS_INT_ACK__JOB_DONE_ACK_MASK 0x00010000L 2203 #define UVD_SYS_INT_ACK__WPTR_IDLE_ACK_MASK 0x00200000L 2204 #define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_IDCT_ACK_MASK 0x00400000L 2205 #define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK 0x00800000L 2206 #define UVD_SYS_INT_ACK__IDCT_ACK_MASK 0x01000000L 2207 #define UVD_SYS_INT_ACK__MPRD_ACK_MASK 0x02000000L 2208 #define UVD_SYS_INT_ACK__FCS_ACK_MASK 0x04000000L 2209 #define UVD_SYS_INT_ACK__CLK_SWT_ACK_MASK 0x08000000L 2210 #define UVD_SYS_INT_ACK__MIF_HWINT_ACK_MASK 0x10000000L 2211 #define UVD_SYS_INT_ACK__MPRD_ERR_ACK_MASK 0x20000000L 2212 #define UVD_SYS_INT_ACK__AVM_INT_ACK_MASK 0x80000000L 2213 //UVD_VCPU_INT_EN 2214 #define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN__SHIFT 0x0 2215 #define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT 0x1 2216 #define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT 0x2 2217 #define UVD_VCPU_INT_EN__NJ_PF_RPT_EN__SHIFT 0x3 2218 #define UVD_VCPU_INT_EN__SW_RB1_INT_EN__SHIFT 0x4 2219 #define UVD_VCPU_INT_EN__SW_RB2_INT_EN__SHIFT 0x5 2220 #define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT 0x6 2221 #define UVD_VCPU_INT_EN__SW_RB3_INT_EN__SHIFT 0x7 2222 #define UVD_VCPU_INT_EN__UVD_HOST_CXW_EN__SHIFT 0x8 2223 #define UVD_VCPU_INT_EN__SW_RB4_INT_EN__SHIFT 0x9 2224 #define UVD_VCPU_INT_EN__SW_RB5_INT_EN__SHIFT 0xa 2225 #define UVD_VCPU_INT_EN__LBSI_EN__SHIFT 0xb 2226 #define UVD_VCPU_INT_EN__UDEC_EN__SHIFT 0xc 2227 #define UVD_VCPU_INT_EN__RPTR_WR_EN__SHIFT 0x10 2228 #define UVD_VCPU_INT_EN__JOB_START_EN__SHIFT 0x11 2229 #define UVD_VCPU_INT_EN__NJ_PF_EN__SHIFT 0x12 2230 #define UVD_VCPU_INT_EN__WPTR_IDLE_EN__SHIFT 0x15 2231 #define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_IDCT_EN__SHIFT 0x16 2232 #define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT 0x17 2233 #define UVD_VCPU_INT_EN__IDCT_EN__SHIFT 0x18 2234 #define UVD_VCPU_INT_EN__MPRD_EN__SHIFT 0x19 2235 #define UVD_VCPU_INT_EN__AVM_INT_EN__SHIFT 0x1a 2236 #define UVD_VCPU_INT_EN__CLK_SWT_EN__SHIFT 0x1b 2237 #define UVD_VCPU_INT_EN__MIF_HWINT_EN__SHIFT 0x1c 2238 #define UVD_VCPU_INT_EN__MPRD_ERR_EN__SHIFT 0x1d 2239 #define UVD_VCPU_INT_EN__DRV_FW_REQ_EN__SHIFT 0x1e 2240 #define UVD_VCPU_INT_EN__DRV_FW_ACK_EN__SHIFT 0x1f 2241 #define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN_MASK 0x00000001L 2242 #define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK 0x00000002L 2243 #define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK 0x00000004L 2244 #define UVD_VCPU_INT_EN__NJ_PF_RPT_EN_MASK 0x00000008L 2245 #define UVD_VCPU_INT_EN__SW_RB1_INT_EN_MASK 0x00000010L 2246 #define UVD_VCPU_INT_EN__SW_RB2_INT_EN_MASK 0x00000020L 2247 #define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK 0x00000040L 2248 #define UVD_VCPU_INT_EN__SW_RB3_INT_EN_MASK 0x00000080L 2249 #define UVD_VCPU_INT_EN__UVD_HOST_CXW_EN_MASK 0x00000100L 2250 #define UVD_VCPU_INT_EN__SW_RB4_INT_EN_MASK 0x00000200L 2251 #define UVD_VCPU_INT_EN__SW_RB5_INT_EN_MASK 0x00000400L 2252 #define UVD_VCPU_INT_EN__LBSI_EN_MASK 0x00000800L 2253 #define UVD_VCPU_INT_EN__UDEC_EN_MASK 0x00001000L 2254 #define UVD_VCPU_INT_EN__RPTR_WR_EN_MASK 0x00010000L 2255 #define UVD_VCPU_INT_EN__JOB_START_EN_MASK 0x00020000L 2256 #define UVD_VCPU_INT_EN__NJ_PF_EN_MASK 0x00040000L 2257 #define UVD_VCPU_INT_EN__WPTR_IDLE_EN_MASK 0x00200000L 2258 #define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_IDCT_EN_MASK 0x00400000L 2259 #define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK 0x00800000L 2260 #define UVD_VCPU_INT_EN__IDCT_EN_MASK 0x01000000L 2261 #define UVD_VCPU_INT_EN__MPRD_EN_MASK 0x02000000L 2262 #define UVD_VCPU_INT_EN__AVM_INT_EN_MASK 0x04000000L 2263 #define UVD_VCPU_INT_EN__CLK_SWT_EN_MASK 0x08000000L 2264 #define UVD_VCPU_INT_EN__MIF_HWINT_EN_MASK 0x10000000L 2265 #define UVD_VCPU_INT_EN__MPRD_ERR_EN_MASK 0x20000000L 2266 #define UVD_VCPU_INT_EN__DRV_FW_REQ_EN_MASK 0x40000000L 2267 #define UVD_VCPU_INT_EN__DRV_FW_ACK_EN_MASK 0x80000000L 2268 //UVD_VCPU_INT_ACK 2269 #define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT 0x0 2270 #define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT 0x1 2271 #define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT 0x2 2272 #define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK__SHIFT 0x3 2273 #define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK__SHIFT 0x4 2274 #define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK__SHIFT 0x5 2275 #define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT 0x6 2276 #define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK__SHIFT 0x7 2277 #define UVD_VCPU_INT_ACK__UVD_HOST_CXW_ACK__SHIFT 0x8 2278 #define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK__SHIFT 0x9 2279 #define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK__SHIFT 0xa 2280 #define UVD_VCPU_INT_ACK__LBSI_ACK__SHIFT 0xb 2281 #define UVD_VCPU_INT_ACK__UDEC_ACK__SHIFT 0xc 2282 #define UVD_VCPU_INT_ACK__RPTR_WR_ACK__SHIFT 0x10 2283 #define UVD_VCPU_INT_ACK__JOB_START_ACK__SHIFT 0x11 2284 #define UVD_VCPU_INT_ACK__NJ_PF_ACK__SHIFT 0x12 2285 #define UVD_VCPU_INT_ACK__WPTR_IDLE_ACK__SHIFT 0x15 2286 #define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_IDCT_ACK__SHIFT 0x16 2287 #define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT 0x17 2288 #define UVD_VCPU_INT_ACK__IDCT_ACK__SHIFT 0x18 2289 #define UVD_VCPU_INT_ACK__MPRD_ACK__SHIFT 0x19 2290 #define UVD_VCPU_INT_ACK__AVM_INT_ACK__SHIFT 0x1a 2291 #define UVD_VCPU_INT_ACK__CLK_SWT_ACK__SHIFT 0x1b 2292 #define UVD_VCPU_INT_ACK__MIF_HWINT_ACK__SHIFT 0x1c 2293 #define UVD_VCPU_INT_ACK__MPRD_ERR_ACK__SHIFT 0x1d 2294 #define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK__SHIFT 0x1e 2295 #define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK__SHIFT 0x1f 2296 #define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK_MASK 0x00000001L 2297 #define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK 0x00000002L 2298 #define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK 0x00000004L 2299 #define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK_MASK 0x00000008L 2300 #define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK_MASK 0x00000010L 2301 #define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK_MASK 0x00000020L 2302 #define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK 0x00000040L 2303 #define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK_MASK 0x00000080L 2304 #define UVD_VCPU_INT_ACK__UVD_HOST_CXW_ACK_MASK 0x00000100L 2305 #define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK_MASK 0x00000200L 2306 #define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK_MASK 0x00000400L 2307 #define UVD_VCPU_INT_ACK__LBSI_ACK_MASK 0x00000800L 2308 #define UVD_VCPU_INT_ACK__UDEC_ACK_MASK 0x00001000L 2309 #define UVD_VCPU_INT_ACK__RPTR_WR_ACK_MASK 0x00010000L 2310 #define UVD_VCPU_INT_ACK__JOB_START_ACK_MASK 0x00020000L 2311 #define UVD_VCPU_INT_ACK__NJ_PF_ACK_MASK 0x00040000L 2312 #define UVD_VCPU_INT_ACK__WPTR_IDLE_ACK_MASK 0x00200000L 2313 #define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_IDCT_ACK_MASK 0x00400000L 2314 #define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK 0x00800000L 2315 #define UVD_VCPU_INT_ACK__IDCT_ACK_MASK 0x01000000L 2316 #define UVD_VCPU_INT_ACK__MPRD_ACK_MASK 0x02000000L 2317 #define UVD_VCPU_INT_ACK__AVM_INT_ACK_MASK 0x04000000L 2318 #define UVD_VCPU_INT_ACK__CLK_SWT_ACK_MASK 0x08000000L 2319 #define UVD_VCPU_INT_ACK__MIF_HWINT_ACK_MASK 0x10000000L 2320 #define UVD_VCPU_INT_ACK__MPRD_ERR_ACK_MASK 0x20000000L 2321 #define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK_MASK 0x40000000L 2322 #define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK_MASK 0x80000000L 2323 //UVD_TOP_CTRL 2324 #define UVD_TOP_CTRL__STANDARD__SHIFT 0x0 2325 #define UVD_TOP_CTRL__STD_VERSION__SHIFT 0x4 2326 #define UVD_TOP_CTRL__STANDARD_MASK 0x0000000FL 2327 #define UVD_TOP_CTRL__STD_VERSION_MASK 0x000000F0L 2328 //UVD_ENC_VCPU_INT_EN 2329 #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN__SHIFT 0x0 2330 #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN__SHIFT 0x1 2331 #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN__SHIFT 0x2 2332 #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN_MASK 0x00000001L 2333 #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN_MASK 0x00000002L 2334 #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN_MASK 0x00000004L 2335 //UVD_ENC_VCPU_INT_ACK 2336 #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK__SHIFT 0x0 2337 #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK__SHIFT 0x1 2338 #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK__SHIFT 0x2 2339 #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK_MASK 0x00000001L 2340 #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK_MASK 0x00000002L 2341 #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK_MASK 0x00000004L 2342 //UVD_LMI_VCPU_CACHE_VMIDS_MULTI 2343 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID__SHIFT 0x0 2344 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID__SHIFT 0x4 2345 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID__SHIFT 0x8 2346 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID__SHIFT 0xc 2347 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID__SHIFT 0x10 2348 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID__SHIFT 0x14 2349 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID__SHIFT 0x18 2350 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID__SHIFT 0x1c 2351 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID_MASK 0x0000000FL 2352 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID_MASK 0x000000F0L 2353 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID_MASK 0x00000F00L 2354 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID_MASK 0x0000F000L 2355 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID_MASK 0x000F0000L 2356 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID_MASK 0x00F00000L 2357 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID_MASK 0x0F000000L 2358 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID_MASK 0xF0000000L 2359 //UVD_LMI_VCPU_NC_VMIDS_MULTI 2360 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID__SHIFT 0x4 2361 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID__SHIFT 0x8 2362 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID__SHIFT 0xc 2363 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID__SHIFT 0x10 2364 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID__SHIFT 0x14 2365 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID__SHIFT 0x18 2366 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID_MASK 0x000000F0L 2367 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID_MASK 0x00000F00L 2368 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID_MASK 0x0000F000L 2369 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID_MASK 0x000F0000L 2370 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID_MASK 0x00F00000L 2371 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID_MASK 0x0F000000L 2372 //UVD_LMI_URGENT_CTRL 2373 #define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL__SHIFT 0x0 2374 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL__SHIFT 0x1 2375 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT__SHIFT 0x2 2376 #define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL__SHIFT 0x8 2377 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL__SHIFT 0x9 2378 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT__SHIFT 0xa 2379 #define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL__SHIFT 0x10 2380 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL__SHIFT 0x11 2381 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT__SHIFT 0x12 2382 #define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL__SHIFT 0x18 2383 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL__SHIFT 0x19 2384 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT__SHIFT 0x1a 2385 #define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL_MASK 0x00000001L 2386 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL_MASK 0x00000002L 2387 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT_MASK 0x0000003CL 2388 #define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL_MASK 0x00000100L 2389 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL_MASK 0x00000200L 2390 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT_MASK 0x00003C00L 2391 #define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL_MASK 0x00010000L 2392 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL_MASK 0x00020000L 2393 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT_MASK 0x003C0000L 2394 #define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL_MASK 0x01000000L 2395 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL_MASK 0x02000000L 2396 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT_MASK 0x3C000000L 2397 //UVD_LMI_CTRL 2398 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 2399 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8 2400 #define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9 2401 #define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb 2402 #define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc 2403 #define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd 2404 #define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe 2405 #define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf 2406 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 2407 #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16 2408 #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17 2409 #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18 2410 #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19 2411 #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a 2412 #define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ__SHIFT 0x1b 2413 #define UVD_LMI_CTRL__RFU__SHIFT 0x1c 2414 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0x000000FFL 2415 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L 2416 #define UVD_LMI_CTRL__REQ_MODE_MASK 0x00000200L 2417 #define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000800L 2418 #define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x00001000L 2419 #define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x00002000L 2420 #define UVD_LMI_CTRL__CRC_RESET_MASK 0x00004000L 2421 #define UVD_LMI_CTRL__CRC_SEL_MASK 0x000F8000L 2422 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L 2423 #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x00400000L 2424 #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x00800000L 2425 #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x01000000L 2426 #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x02000000L 2427 #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x04000000L 2428 #define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ_MASK 0x08000000L 2429 #define UVD_LMI_CTRL__RFU_MASK 0xF0000000L 2430 //UVD_LMI_STATUS 2431 #define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0 2432 #define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1 2433 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2 2434 #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3 2435 #define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4 2436 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5 2437 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6 2438 #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7 2439 #define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8 2440 #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9 2441 #define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa 2442 #define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb 2443 #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc 2444 #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd 2445 #define UVD_LMI_STATUS__BSP0_WRITE_CLEAN__SHIFT 0x12 2446 #define UVD_LMI_STATUS__BSP1_WRITE_CLEAN__SHIFT 0x13 2447 #define UVD_LMI_STATUS__BSP2_WRITE_CLEAN__SHIFT 0x14 2448 #define UVD_LMI_STATUS__BSP3_WRITE_CLEAN__SHIFT 0x15 2449 #define UVD_LMI_STATUS__CENC_READ_CLEAN__SHIFT 0x16 2450 #define UVD_LMI_STATUS__READ_CLEAN_MASK 0x00000001L 2451 #define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x00000002L 2452 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x00000004L 2453 #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x00000008L 2454 #define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x00000010L 2455 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x00000020L 2456 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x00000040L 2457 #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x00000080L 2458 #define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x00000100L 2459 #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x00000200L 2460 #define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x00000400L 2461 #define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x00000800L 2462 #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x00001000L 2463 #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x00002000L 2464 #define UVD_LMI_STATUS__BSP0_WRITE_CLEAN_MASK 0x00040000L 2465 #define UVD_LMI_STATUS__BSP1_WRITE_CLEAN_MASK 0x00080000L 2466 #define UVD_LMI_STATUS__BSP2_WRITE_CLEAN_MASK 0x00100000L 2467 #define UVD_LMI_STATUS__BSP3_WRITE_CLEAN_MASK 0x00200000L 2468 #define UVD_LMI_STATUS__CENC_READ_CLEAN_MASK 0x00400000L 2469 //UVD_LMI_VM_CTRL 2470 #define UVD_LMI_VM_CTRL__VCPU_VM__SHIFT 0x0 2471 #define UVD_LMI_VM_CTRL__CM_VM__SHIFT 0x1 2472 #define UVD_LMI_VM_CTRL__IT_VM__SHIFT 0x2 2473 #define UVD_LMI_VM_CTRL__MP_VM__SHIFT 0x3 2474 #define UVD_LMI_VM_CTRL__DB_VM__SHIFT 0x4 2475 #define UVD_LMI_VM_CTRL__RB_VM__SHIFT 0x5 2476 #define UVD_LMI_VM_CTRL__IB_VM__SHIFT 0x6 2477 #define UVD_LMI_VM_CTRL__CSM_VM__SHIFT 0x7 2478 #define UVD_LMI_VM_CTRL__RB_WR_VM__SHIFT 0x8 2479 #define UVD_LMI_VM_CTRL__DBW_VM__SHIFT 0xa 2480 #define UVD_LMI_VM_CTRL__RB_RPTR_VM__SHIFT 0xb 2481 #define UVD_LMI_VM_CTRL__RE_VM__SHIFT 0xc 2482 #define UVD_LMI_VM_CTRL__SCPU_VM__SHIFT 0xd 2483 #define UVD_LMI_VM_CTRL__ACAP_VM__SHIFT 0xe 2484 #define UVD_LMI_VM_CTRL__VCPU_VM_MASK 0x00000001L 2485 #define UVD_LMI_VM_CTRL__CM_VM_MASK 0x00000002L 2486 #define UVD_LMI_VM_CTRL__IT_VM_MASK 0x00000004L 2487 #define UVD_LMI_VM_CTRL__MP_VM_MASK 0x00000008L 2488 #define UVD_LMI_VM_CTRL__DB_VM_MASK 0x00000010L 2489 #define UVD_LMI_VM_CTRL__RB_VM_MASK 0x00000020L 2490 #define UVD_LMI_VM_CTRL__IB_VM_MASK 0x00000040L 2491 #define UVD_LMI_VM_CTRL__CSM_VM_MASK 0x00000080L 2492 #define UVD_LMI_VM_CTRL__RB_WR_VM_MASK 0x00000100L 2493 #define UVD_LMI_VM_CTRL__DBW_VM_MASK 0x00000400L 2494 #define UVD_LMI_VM_CTRL__RB_RPTR_VM_MASK 0x00000800L 2495 #define UVD_LMI_VM_CTRL__RE_VM_MASK 0x00001000L 2496 #define UVD_LMI_VM_CTRL__SCPU_VM_MASK 0x00002000L 2497 #define UVD_LMI_VM_CTRL__ACAP_VM_MASK 0x00004000L 2498 //UVD_LMI_PERFMON_CTRL 2499 #define UVD_LMI_PERFMON_CTRL__PERFMON_STATE__SHIFT 0x0 2500 #define UVD_LMI_PERFMON_CTRL__PERFMON_SEL__SHIFT 0x8 2501 #define UVD_LMI_PERFMON_CTRL__PERFMON_STATE_MASK 0x00000003L 2502 #define UVD_LMI_PERFMON_CTRL__PERFMON_SEL_MASK 0x00001F00L 2503 //UVD_LMI_PERFMON_COUNT_LO 2504 #define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT 0x0 2505 #define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK 0xFFFFFFFFL 2506 //UVD_LMI_PERFMON_COUNT_HI 2507 #define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT 0x0 2508 #define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK 0x0000FFFFL 2509 //UVD_LMI_SWAP_CNTL 2510 #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 2511 #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 2512 #define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4 2513 #define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6 2514 #define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8 2515 #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa 2516 #define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc 2517 #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe 2518 #define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10 2519 #define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12 2520 #define UVD_LMI_SWAP_CNTL__ACAP_MC_SWAP__SHIFT 0x14 2521 #define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT 0x16 2522 #define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18 2523 #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a 2524 #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c 2525 #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e 2526 #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 2527 #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 2528 #define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x00000030L 2529 #define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0x000000C0L 2530 #define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x00000300L 2531 #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK 0x00000C00L 2532 #define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK 0x00003000L 2533 #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK 0x0000C000L 2534 #define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x00030000L 2535 #define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK 0x000C0000L 2536 #define UVD_LMI_SWAP_CNTL__ACAP_MC_SWAP_MASK 0x00300000L 2537 #define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK 0x00C00000L 2538 #define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK 0x03000000L 2539 #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0x0C000000L 2540 #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000L 2541 #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xC0000000L 2542 //UVD_UDEC_ADR 2543 #define UVD_UDEC_ADR__SYNC_RE__SHIFT 0x7 2544 #define UVD_UDEC_ADR__SYNC_RE_MASK 0x00000080L 2545 //UVD_MP_SWAP_CNTL 2546 #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0 2547 #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2 2548 #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4 2549 #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6 2550 #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8 2551 #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa 2552 #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc 2553 #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe 2554 #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10 2555 #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12 2556 #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14 2557 #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16 2558 #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18 2559 #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a 2560 #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c 2561 #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e 2562 #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x00000003L 2563 #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0x0000000CL 2564 #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x00000030L 2565 #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0x000000C0L 2566 #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x00000300L 2567 #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0x00000C00L 2568 #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x00003000L 2569 #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0x0000C000L 2570 #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x00030000L 2571 #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0x000C0000L 2572 #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x00300000L 2573 #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0x00C00000L 2574 #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x03000000L 2575 #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0x0C000000L 2576 #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000L 2577 #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xC0000000L 2578 //UVD_MPC_LUMA_SRCH 2579 #define UVD_MPC_LUMA_SRCH__CNTR__SHIFT 0x0 2580 #define UVD_MPC_LUMA_SRCH__CNTR_MASK 0xFFFFFFFFL 2581 //UVD_MPC_LUMA_HIT 2582 #define UVD_MPC_LUMA_HIT__CNTR__SHIFT 0x0 2583 #define UVD_MPC_LUMA_HIT__CNTR_MASK 0xFFFFFFFFL 2584 //UVD_MPC_LUMA_HITPEND 2585 #define UVD_MPC_LUMA_HITPEND__CNTR__SHIFT 0x0 2586 #define UVD_MPC_LUMA_HITPEND__CNTR_MASK 0xFFFFFFFFL 2587 //UVD_MPC_CHROMA_SRCH 2588 #define UVD_MPC_CHROMA_SRCH__CNTR__SHIFT 0x0 2589 #define UVD_MPC_CHROMA_SRCH__CNTR_MASK 0xFFFFFFFFL 2590 //UVD_MPC_CHROMA_HIT 2591 #define UVD_MPC_CHROMA_HIT__CNTR__SHIFT 0x0 2592 #define UVD_MPC_CHROMA_HIT__CNTR_MASK 0xFFFFFFFFL 2593 //UVD_MPC_CHROMA_HITPEND 2594 #define UVD_MPC_CHROMA_HITPEND__CNTR__SHIFT 0x0 2595 #define UVD_MPC_CHROMA_HITPEND__CNTR_MASK 0xFFFFFFFFL 2596 //UVD_MPC_CNTL 2597 #define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3 2598 #define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6 2599 #define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10 2600 #define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12 2601 #define UVD_MPC_CNTL__SMPAT_REQ_SPEED_UP__SHIFT 0x13 2602 #define UVD_MPC_CNTL__TEST_MODE_EN__SHIFT 0x14 2603 #define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L 2604 #define UVD_MPC_CNTL__PERF_RST_MASK 0x00000040L 2605 #define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x00030000L 2606 #define UVD_MPC_CNTL__URGENT_EN_MASK 0x00040000L 2607 #define UVD_MPC_CNTL__SMPAT_REQ_SPEED_UP_MASK 0x00080000L 2608 #define UVD_MPC_CNTL__TEST_MODE_EN_MASK 0x00100000L 2609 //UVD_MPC_PITCH 2610 #define UVD_MPC_PITCH__LUMA_PITCH__SHIFT 0x0 2611 #define UVD_MPC_PITCH__LUMA_PITCH_MASK 0x000007FFL 2612 //UVD_MPC_SET_MUXA0 2613 #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 2614 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 2615 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc 2616 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 2617 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 2618 #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x0000003FL 2619 #define UVD_MPC_SET_MUXA0__VARA_1_MASK 0x00000FC0L 2620 #define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x0003F000L 2621 #define UVD_MPC_SET_MUXA0__VARA_3_MASK 0x00FC0000L 2622 #define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3F000000L 2623 //UVD_MPC_SET_MUXA1 2624 #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0 2625 #define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6 2626 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc 2627 #define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x0000003FL 2628 #define UVD_MPC_SET_MUXA1__VARA_6_MASK 0x00000FC0L 2629 #define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x0003F000L 2630 //UVD_MPC_SET_MUXB0 2631 #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 2632 #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6 2633 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc 2634 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 2635 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 2636 #define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x0000003FL 2637 #define UVD_MPC_SET_MUXB0__VARB_1_MASK 0x00000FC0L 2638 #define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x0003F000L 2639 #define UVD_MPC_SET_MUXB0__VARB_3_MASK 0x00FC0000L 2640 #define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3F000000L 2641 //UVD_MPC_SET_MUXB1 2642 #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0 2643 #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 2644 #define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc 2645 #define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x0000003FL 2646 #define UVD_MPC_SET_MUXB1__VARB_6_MASK 0x00000FC0L 2647 #define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x0003F000L 2648 //UVD_MPC_SET_MUX 2649 #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 2650 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 2651 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 2652 #define UVD_MPC_SET_MUX__SET_0_MASK 0x00000007L 2653 #define UVD_MPC_SET_MUX__SET_1_MASK 0x00000038L 2654 #define UVD_MPC_SET_MUX__SET_2_MASK 0x000001C0L 2655 //UVD_MPC_SET_ALU 2656 #define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0 2657 #define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4 2658 #define UVD_MPC_SET_ALU__FUNCT_MASK 0x00000007L 2659 #define UVD_MPC_SET_ALU__OPERAND_MASK 0x00000FF0L 2660 //UVD_GPCOM_SYS_CMD 2661 #define UVD_GPCOM_SYS_CMD__CMD_SEND__SHIFT 0x0 2662 #define UVD_GPCOM_SYS_CMD__CMD__SHIFT 0x1 2663 #define UVD_GPCOM_SYS_CMD__CMD_SOURCE__SHIFT 0x1f 2664 #define UVD_GPCOM_SYS_CMD__CMD_SEND_MASK 0x00000001L 2665 #define UVD_GPCOM_SYS_CMD__CMD_MASK 0x7FFFFFFEL 2666 #define UVD_GPCOM_SYS_CMD__CMD_SOURCE_MASK 0x80000000L 2667 //UVD_GPCOM_SYS_DATA0 2668 #define UVD_GPCOM_SYS_DATA0__DATA0__SHIFT 0x0 2669 #define UVD_GPCOM_SYS_DATA0__DATA0_MASK 0xFFFFFFFFL 2670 //UVD_GPCOM_SYS_DATA1 2671 #define UVD_GPCOM_SYS_DATA1__DATA1__SHIFT 0x0 2672 #define UVD_GPCOM_SYS_DATA1__DATA1_MASK 0xFFFFFFFFL 2673 //UVD_VCPU_CACHE_OFFSET0 2674 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 2675 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x001FFFFFL 2676 //UVD_VCPU_CACHE_SIZE0 2677 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0 2678 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x001FFFFFL 2679 //UVD_VCPU_CACHE_OFFSET1 2680 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 2681 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x001FFFFFL 2682 //UVD_VCPU_CACHE_SIZE1 2683 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0 2684 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x001FFFFFL 2685 //UVD_VCPU_CACHE_OFFSET2 2686 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 2687 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x001FFFFFL 2688 //UVD_VCPU_CACHE_SIZE2 2689 #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0 2690 #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x001FFFFFL 2691 //UVD_VCPU_CACHE_OFFSET3 2692 #define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3__SHIFT 0x0 2693 #define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3_MASK 0x001FFFFFL 2694 //UVD_VCPU_CACHE_SIZE3 2695 #define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3__SHIFT 0x0 2696 #define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3_MASK 0x001FFFFFL 2697 //UVD_VCPU_CACHE_OFFSET4 2698 #define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4__SHIFT 0x0 2699 #define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4_MASK 0x001FFFFFL 2700 //UVD_VCPU_CACHE_SIZE4 2701 #define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4__SHIFT 0x0 2702 #define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4_MASK 0x001FFFFFL 2703 //UVD_VCPU_CACHE_OFFSET5 2704 #define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5__SHIFT 0x0 2705 #define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5_MASK 0x001FFFFFL 2706 //UVD_VCPU_CACHE_SIZE5 2707 #define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5__SHIFT 0x0 2708 #define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5_MASK 0x001FFFFFL 2709 //UVD_VCPU_CACHE_OFFSET6 2710 #define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6__SHIFT 0x0 2711 #define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6_MASK 0x001FFFFFL 2712 //UVD_VCPU_CACHE_SIZE6 2713 #define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6__SHIFT 0x0 2714 #define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6_MASK 0x001FFFFFL 2715 //UVD_VCPU_CACHE_OFFSET7 2716 #define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7__SHIFT 0x0 2717 #define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7_MASK 0x001FFFFFL 2718 //UVD_VCPU_CACHE_SIZE7 2719 #define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7__SHIFT 0x0 2720 #define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7_MASK 0x001FFFFFL 2721 //UVD_VCPU_CACHE_OFFSET8 2722 #define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8__SHIFT 0x0 2723 #define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8_MASK 0x001FFFFFL 2724 //UVD_VCPU_CACHE_SIZE8 2725 #define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8__SHIFT 0x0 2726 #define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8_MASK 0x001FFFFFL 2727 //UVD_VCPU_NONCACHE_OFFSET0 2728 #define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0__SHIFT 0x0 2729 #define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0_MASK 0x01FFFFFFL 2730 //UVD_VCPU_NONCACHE_SIZE0 2731 #define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0__SHIFT 0x0 2732 #define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0_MASK 0x001FFFFFL 2733 //UVD_VCPU_NONCACHE_OFFSET1 2734 #define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1__SHIFT 0x0 2735 #define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1_MASK 0x01FFFFFFL 2736 //UVD_VCPU_NONCACHE_SIZE1 2737 #define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1__SHIFT 0x0 2738 #define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1_MASK 0x001FFFFFL 2739 //UVD_VCPU_CNTL 2740 #define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0 2741 #define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5 2742 #define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6 2743 #define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7 2744 #define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8 2745 #define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9 2746 #define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa 2747 #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb 2748 #define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10 2749 #define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP__SHIFT 0x11 2750 #define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12 2751 #define UVD_VCPU_CNTL__SUVD_EN__SHIFT 0x13 2752 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 2753 #define UVD_VCPU_CNTL__CABAC_MB_ACC__SHIFT 0x1c 2754 #define UVD_VCPU_CNTL__WMV9_EN__SHIFT 0x1e 2755 #define UVD_VCPU_CNTL__RE_OFFLOAD_EN__SHIFT 0x1f 2756 #define UVD_VCPU_CNTL__IRQ_ERR_MASK 0x0000000FL 2757 #define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x00000020L 2758 #define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x00000040L 2759 #define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x00000080L 2760 #define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x00000100L 2761 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L 2762 #define UVD_VCPU_CNTL__TRCE_EN_MASK 0x00000400L 2763 #define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x00001800L 2764 #define UVD_VCPU_CNTL__JTAG_EN_MASK 0x00010000L 2765 #define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK 0x00020000L 2766 #define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x00040000L 2767 #define UVD_VCPU_CNTL__SUVD_EN_MASK 0x00080000L 2768 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0x0FF00000L 2769 #define UVD_VCPU_CNTL__CABAC_MB_ACC_MASK 0x10000000L 2770 #define UVD_VCPU_CNTL__WMV9_EN_MASK 0x40000000L 2771 #define UVD_VCPU_CNTL__RE_OFFLOAD_EN_MASK 0x80000000L 2772 //UVD_VCPU_PRID 2773 #define UVD_VCPU_PRID__PRID__SHIFT 0x0 2774 #define UVD_VCPU_PRID__PRID_MASK 0x0000FFFFL 2775 //UVD_VCPU_TRCE 2776 #define UVD_VCPU_TRCE__PC__SHIFT 0x0 2777 #define UVD_VCPU_TRCE__PC_MASK 0x0FFFFFFFL 2778 //UVD_VCPU_TRCE_RD 2779 #define UVD_VCPU_TRCE_RD__DATA__SHIFT 0x0 2780 #define UVD_VCPU_TRCE_RD__DATA_MASK 0xFFFFFFFFL 2781 //UVD_MPC_PERF0 2782 #define UVD_MPC_PERF0__MAX_LAT__SHIFT 0x0 2783 #define UVD_MPC_PERF0__MAX_LAT_MASK 0x000003FFL 2784 //UVD_MPC_PERF1 2785 #define UVD_MPC_PERF1__AVE_LAT__SHIFT 0x0 2786 #define UVD_MPC_PERF1__AVE_LAT_MASK 0x000003FFL 2787 //UVD_CXW_WR 2788 #define UVD_CXW_WR__DAT__SHIFT 0x0 2789 #define UVD_CXW_WR__STAT__SHIFT 0x1f 2790 #define UVD_CXW_WR__DAT_MASK 0x0FFFFFFFL 2791 #define UVD_CXW_WR__STAT_MASK 0x80000000L 2792 //UVD_SOFT_RESET 2793 #define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0 2794 #define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1 2795 #define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2 2796 #define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3 2797 #define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4 2798 #define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT 0x5 2799 #define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6 2800 #define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7 2801 #define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8 2802 #define UVD_SOFT_RESET__EFC_SOFT_RESET__SHIFT 0x9 2803 #define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa 2804 #define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb 2805 #define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc 2806 #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd 2807 #define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe 2808 #define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf 2809 #define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10 2810 #define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11 2811 #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12 2812 #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13 2813 #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14 2814 #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15 2815 #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16 2816 #define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS__SHIFT 0x17 2817 #define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS__SHIFT 0x18 2818 #define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS__SHIFT 0x19 2819 #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a 2820 #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b 2821 #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c 2822 #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d 2823 #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e 2824 #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f 2825 #define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x00000001L 2826 #define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x00000002L 2827 #define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x00000004L 2828 #define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x00000008L 2829 #define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x00000010L 2830 #define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK 0x00000020L 2831 #define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x00000040L 2832 #define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000080L 2833 #define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x00000100L 2834 #define UVD_SOFT_RESET__EFC_SOFT_RESET_MASK 0x00000200L 2835 #define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x00000400L 2836 #define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x00000800L 2837 #define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x00001000L 2838 #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x00002000L 2839 #define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x00004000L 2840 #define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x00008000L 2841 #define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x00010000L 2842 #define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x00020000L 2843 #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x00040000L 2844 #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x00080000L 2845 #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x00100000L 2846 #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x00200000L 2847 #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x00400000L 2848 #define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS_MASK 0x00800000L 2849 #define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS_MASK 0x01000000L 2850 #define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS_MASK 0x02000000L 2851 #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x04000000L 2852 #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x08000000L 2853 #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000L 2854 #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000L 2855 #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000L 2856 #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000L 2857 //UVD_LMI_RBC_IB_VMID 2858 #define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0 2859 #define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0x0000000FL 2860 //UVD_RBC_IB_SIZE 2861 #define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4 2862 #define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 2863 //UVD_LMI_RBC_RB_VMID 2864 #define UVD_LMI_RBC_RB_VMID__RB_VMID__SHIFT 0x0 2865 #define UVD_LMI_RBC_RB_VMID__RB_VMID_MASK 0x0000000FL 2866 //UVD_RBC_RB_RPTR 2867 #define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4 2868 #define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 2869 //UVD_RBC_RB_WPTR 2870 #define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4 2871 #define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 2872 //UVD_RBC_RB_WPTR_CNTL 2873 #define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x0 2874 #define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK 0x00007FFFL 2875 //UVD_RBC_READ_REQ_URGENT_CNTL 2876 #define UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 2877 #define UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L 2878 //UVD_RBC_WPTR_STATUS 2879 #define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE__SHIFT 0x4 2880 #define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE_MASK 0x007FFFF0L 2881 //UVD_RBC_RB_CNTL 2882 #define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0 2883 #define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8 2884 #define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10 2885 #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14 2886 #define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18 2887 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c 2888 #define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x0000001FL 2889 #define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x00001F00L 2890 #define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x00010000L 2891 #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x00100000L 2892 #define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x01000000L 2893 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000L 2894 //UVD_RBC_RB_RPTR_ADDR 2895 #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0 2896 #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFFL 2897 //UVD_JOB_START 2898 #define UVD_JOB_START__JOB_START__SHIFT 0x0 2899 #define UVD_JOB_START__JOB_START_MASK 0x00000001L 2900 //UVD_JOB_DONE 2901 #define UVD_JOB_DONE__JOB_DONE__SHIFT 0x0 2902 #define UVD_JOB_DONE__JOB_DONE_MASK 0x00000003L 2903 //UVD_STATUS 2904 #define UVD_STATUS__RBC_BUSY__SHIFT 0x0 2905 #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 2906 #define UVD_STATUS__AVP_BUSY__SHIFT 0x8 2907 #define UVD_STATUS__IDCT_BUSY__SHIFT 0x9 2908 #define UVD_STATUS__IDCT_CTL_ACK__SHIFT 0xb 2909 #define UVD_STATUS__UVD_CTL_ACK__SHIFT 0xc 2910 #define UVD_STATUS__AVP_BLOCK_ACK__SHIFT 0xd 2911 #define UVD_STATUS__IDCT_BLOCK_ACK__SHIFT 0xe 2912 #define UVD_STATUS__UVD_BLOCK_ACK__SHIFT 0xf 2913 #define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT 0x10 2914 #define UVD_STATUS__SYS_GPCOM_REQ__SHIFT 0x1f 2915 #define UVD_STATUS__RBC_BUSY_MASK 0x00000001L 2916 #define UVD_STATUS__VCPU_REPORT_MASK 0x000000FEL 2917 #define UVD_STATUS__AVP_BUSY_MASK 0x00000100L 2918 #define UVD_STATUS__IDCT_BUSY_MASK 0x00000200L 2919 #define UVD_STATUS__IDCT_CTL_ACK_MASK 0x00000800L 2920 #define UVD_STATUS__UVD_CTL_ACK_MASK 0x00001000L 2921 #define UVD_STATUS__AVP_BLOCK_ACK_MASK 0x00002000L 2922 #define UVD_STATUS__IDCT_BLOCK_ACK_MASK 0x00004000L 2923 #define UVD_STATUS__UVD_BLOCK_ACK_MASK 0x00008000L 2924 #define UVD_STATUS__RBC_ACCESS_GPCOM_MASK 0x00010000L 2925 #define UVD_STATUS__SYS_GPCOM_REQ_MASK 0x80000000L 2926 //UVD_SEMA_TIMEOUT_STATUS 2927 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0 2928 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1 2929 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2 2930 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3 2931 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000001L 2932 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x00000002L 2933 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000004L 2934 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x00000008L 2935 //UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 2936 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0 2937 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1 2938 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 2939 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x00000001L 2940 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x001FFFFEL 2941 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L 2942 //UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 2943 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0 2944 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1 2945 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 2946 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x00000001L 2947 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x001FFFFEL 2948 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L 2949 //UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 2950 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0 2951 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1 2952 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 2953 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x00000001L 2954 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x001FFFFEL 2955 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L 2956 //UVD_CXW_EN 2957 #define UVD_CXW_EN__CXW_ENABLE__SHIFT 0x0 2958 #define UVD_CXW_EN__CXW_ENABLE_MASK 0x00000001L 2959 //UVD_CXW_SE 2960 #define UVD_CXW_SE__CXW_SCAN_ENABLE__SHIFT 0x0 2961 #define UVD_CXW_SE__CXW_SCAN_ENABLE_MASK 0x00000001L 2962 //UVD_CXW_FINISHED 2963 #define UVD_CXW_FINISHED__CXW_FINISHED__SHIFT 0x0 2964 #define UVD_CXW_FINISHED__CXW_FINISHED_MASK 0x00000001L 2965 //UVD_CXW_SHIFT_FINISHED 2966 #define UVD_CXW_SHIFT_FINISHED__SHIFT_FINISHED__SHIFT 0x0 2967 #define UVD_CXW_SHIFT_FINISHED__SHIFT_FINISHED_MASK 0x00000001L 2968 //UVD_CXW_START 2969 #define UVD_CXW_START__START_CXW__SHIFT 0x0 2970 #define UVD_CXW_START__START_CXW_MASK 0x00000001L 2971 //UVD_CXW_BLOCK_STATUS 2972 #define UVD_CXW_BLOCK_STATUS__VCPU_IDLE__SHIFT 0x0 2973 #define UVD_CXW_BLOCK_STATUS__LBSI_IDLE__SHIFT 0x1 2974 #define UVD_CXW_BLOCK_STATUS__LMI_IDLE__SHIFT 0x2 2975 #define UVD_CXW_BLOCK_STATUS__VCPU_IDLE_MASK 0x00000001L 2976 #define UVD_CXW_BLOCK_STATUS__LBSI_IDLE_MASK 0x00000002L 2977 #define UVD_CXW_BLOCK_STATUS__LMI_IDLE_MASK 0x00000004L 2978 //UVD_STOP_CONTEXT 2979 #define UVD_STOP_CONTEXT__STOP_CONTEXT__SHIFT 0x0 2980 #define UVD_STOP_CONTEXT__CONTEXT_MODE__SHIFT 0x1 2981 #define UVD_STOP_CONTEXT__STOP_CONTEXT_MASK 0x00000001L 2982 #define UVD_STOP_CONTEXT__CONTEXT_MODE_MASK 0x00000002L 2983 //UVD_CXW_SAVE_AREA_ADDR 2984 #define UVD_CXW_SAVE_AREA_ADDR__CXW_SAVE_AREA_ADDR__SHIFT 0x6 2985 #define UVD_CXW_SAVE_AREA_ADDR__CXW_SAVE_AREA_ADDR_MASK 0xFFFFFFC0L 2986 //UVD_CBUF_ID 2987 #define UVD_CBUF_ID__CBUF_ID__SHIFT 0x0 2988 #define UVD_CBUF_ID__CBUF_ID_MASK 0xFFFFFFFFL 2989 //UVD_CONTEXT_ID 2990 #define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0 2991 #define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xFFFFFFFFL 2992 //UVD_CXW_SAVE_AREA_SIZE 2993 #define UVD_CXW_SAVE_AREA_SIZE__CXW_SAVE_AREA_SIZE__SHIFT 0x0 2994 #define UVD_CXW_SAVE_AREA_SIZE__CXW_SAVE_AREA_SIZE_MASK 0xFFFFFFFFL 2995 //UVD_CONTEXT_ID2 2996 #define UVD_CONTEXT_ID2__CONTEXT_ID2__SHIFT 0x0 2997 #define UVD_CONTEXT_ID2__CONTEXT_ID2_MASK 0xFFFFFFFFL 2998 //UVD_CXW_CNTL 2999 #define UVD_CXW_CNTL__HOST_CXW_EN__SHIFT 0x0 3000 #define UVD_CXW_CNTL__EXTERNAL_CXW_EN__SHIFT 0x1 3001 #define UVD_CXW_CNTL__SEMAPHORE_TIMEOUT_CXW_EN__SHIFT 0x3 3002 #define UVD_CXW_CNTL__HOST_CXW_INT_EN__SHIFT 0x4 3003 #define UVD_CXW_CNTL__EXTERNAL_CXW_INT_EN__SHIFT 0x5 3004 #define UVD_CXW_CNTL__SEMAPHORE_TIMEOUT_CXW_INT_EN__SHIFT 0x7 3005 #define UVD_CXW_CNTL__HOST_CXW_EN_MASK 0x00000001L 3006 #define UVD_CXW_CNTL__EXTERNAL_CXW_EN_MASK 0x00000002L 3007 #define UVD_CXW_CNTL__SEMAPHORE_TIMEOUT_CXW_EN_MASK 0x00000008L 3008 #define UVD_CXW_CNTL__HOST_CXW_INT_EN_MASK 0x00000010L 3009 #define UVD_CXW_CNTL__EXTERNAL_CXW_INT_EN_MASK 0x00000020L 3010 #define UVD_CXW_CNTL__SEMAPHORE_TIMEOUT_CXW_INT_EN_MASK 0x00000080L 3011 //UVD_CXW_EVENT 3012 #define UVD_CXW_EVENT__HOST_CXW_EVENT_OCCURRED__SHIFT 0x0 3013 #define UVD_CXW_EVENT__EXTERNAL_CXW_EVENT_OCCURRED__SHIFT 0x1 3014 #define UVD_CXW_EVENT__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_EVENT_OCCURRED__SHIFT 0x3 3015 #define UVD_CXW_EVENT__SEMAPHORE_WAIT_FAULT_TIMEOUT_EVENT_OCCURRED__SHIFT 0x4 3016 #define UVD_CXW_EVENT__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_EVENT_OCCURRED__SHIFT 0x5 3017 #define UVD_CXW_EVENT__HOST_CXW_EVENT_OCCURRED_MASK 0x00000001L 3018 #define UVD_CXW_EVENT__EXTERNAL_CXW_EVENT_OCCURRED_MASK 0x00000002L 3019 #define UVD_CXW_EVENT__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_EVENT_OCCURRED_MASK 0x00000008L 3020 #define UVD_CXW_EVENT__SEMAPHORE_WAIT_FAULT_TIMEOUT_EVENT_OCCURRED_MASK 0x00000010L 3021 #define UVD_CXW_EVENT__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_EVENT_OCCURRED_MASK 0x00000020L 3022 //UVD_CXW_SCAN_AREA_OFFSET 3023 #define UVD_CXW_SCAN_AREA_OFFSET__CXW_SCAN_AREA_OFFSET__SHIFT 0x0 3024 #define UVD_CXW_SCAN_AREA_OFFSET__CXW_CONTEXT_RESTORE__SHIFT 0x1a 3025 #define UVD_CXW_SCAN_AREA_OFFSET__CXW_CONTEXT_SAVE__SHIFT 0x1b 3026 #define UVD_CXW_SCAN_AREA_OFFSET__CXW_SCAN_AREA_OFFSET_MASK 0x03FFFFFFL 3027 #define UVD_CXW_SCAN_AREA_OFFSET__CXW_CONTEXT_RESTORE_MASK 0x04000000L 3028 #define UVD_CXW_SCAN_AREA_OFFSET__CXW_CONTEXT_SAVE_MASK 0x08000000L 3029 //UVD_CXW_SHIFT_CNTL 3030 #define UVD_CXW_SHIFT_CNTL__SHIFT_CNTL__SHIFT 0x0 3031 #define UVD_CXW_SHIFT_CNTL__SHIFT_COUNT__SHIFT 0x1 3032 #define UVD_CXW_SHIFT_CNTL__SHIFT_CNTL_MASK 0x00000001L 3033 #define UVD_CXW_SHIFT_CNTL__SHIFT_COUNT_MASK 0x00000FFEL 3034 //UVD_RBC_CAM_EN 3035 #define UVD_RBC_CAM_EN__RBC_CAM_EN__SHIFT 0x0 3036 #define UVD_RBC_CAM_EN__RBC_CAM_EN_MASK 0x00000001L 3037 //UVD_RBC_CAM_INDEX 3038 #define UVD_RBC_CAM_INDEX__RBC_CAM_INDEX__SHIFT 0x0 3039 #define UVD_RBC_CAM_INDEX__RBC_CAM_INDEX_MASK 0xFFFFFFFFL 3040 //UVD_RBC_CAM_DATA 3041 #define UVD_RBC_CAM_DATA__RBC_CAM_DATA_ORG__SHIFT 0x0 3042 #define UVD_RBC_CAM_DATA__RBC_CAM_DATA_MAP__SHIFT 0x10 3043 #define UVD_RBC_CAM_DATA__RBC_CAM_DATA_ORG_MASK 0x0000FFFFL 3044 #define UVD_RBC_CAM_DATA__RBC_CAM_DATA_MAP_MASK 0xFFFF0000L 3045 //UVD_RBC_VCPU_ACCESS 3046 #define UVD_RBC_VCPU_ACCESS__ENABLE_RBC__SHIFT 0x0 3047 #define UVD_RBC_VCPU_ACCESS__ENABLE_RBC_MASK 0x00000001L 3048 //UVD_CXW_INT_ID 3049 #define UVD_CXW_INT_ID__ID__SHIFT 0x0 3050 #define UVD_CXW_INT_ID__ID_MASK 0x000000FFL 3051 //UVD_LMI_CRC0 3052 #define UVD_LMI_CRC0__CRC32__SHIFT 0x0 3053 #define UVD_LMI_CRC0__CRC32_MASK 0xFFFFFFFFL 3054 //UVD_LMI_CRC1 3055 #define UVD_LMI_CRC1__CRC32__SHIFT 0x0 3056 #define UVD_LMI_CRC1__CRC32_MASK 0xFFFFFFFFL 3057 //UVD_LMI_CRC2 3058 #define UVD_LMI_CRC2__CRC32__SHIFT 0x0 3059 #define UVD_LMI_CRC2__CRC32_MASK 0xFFFFFFFFL 3060 //UVD_LMI_CRC3 3061 #define UVD_LMI_CRC3__CRC32__SHIFT 0x0 3062 #define UVD_LMI_CRC3__CRC32_MASK 0xFFFFFFFFL 3063 //UVD_RBC_WPTR_POLL_CNTL 3064 #define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ__SHIFT 0x0 3065 #define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 3066 #define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ_MASK 0x0000FFFFL 3067 #define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 3068 //UVD_RBC_WPTR_POLL_ADDR 3069 #define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR__SHIFT 0x2 3070 #define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR_MASK 0xFFFFFFFCL 3071 //UVD_RB_BASE_LO4 3072 #define UVD_RB_BASE_LO4__RB_BASE_LO__SHIFT 0x6 3073 #define UVD_RB_BASE_LO4__RB_BASE_LO_MASK 0xFFFFFFC0L 3074 //UVD_RB_BASE_HI4 3075 #define UVD_RB_BASE_HI4__RB_BASE_HI__SHIFT 0x0 3076 #define UVD_RB_BASE_HI4__RB_BASE_HI_MASK 0xFFFFFFFFL 3077 //UVD_RB_SIZE4 3078 #define UVD_RB_SIZE4__RB_SIZE__SHIFT 0x4 3079 #define UVD_RB_SIZE4__RB_SIZE_MASK 0x007FFFF0L 3080 //UVD_RB_RPTR4 3081 #define UVD_RB_RPTR4__RB_RPTR__SHIFT 0x4 3082 #define UVD_RB_RPTR4__RB_RPTR_MASK 0x007FFFF0L 3083 //UVD_LMI_MC_CREDITS 3084 #define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS__SHIFT 0x0 3085 #define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS__SHIFT 0x8 3086 #define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS__SHIFT 0x10 3087 #define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS__SHIFT 0x18 3088 #define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS_MASK 0x0000003FL 3089 #define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS_MASK 0x00003F00L 3090 #define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS_MASK 0x003F0000L 3091 #define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS_MASK 0x3F000000L 3092 //UVD_RBC_BUF_STATUS 3093 #define UVD_RBC_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 3094 #define UVD_RBC_BUF_STATUS__IB_BUF_VALID__SHIFT 0x8 3095 #define UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 3096 #define UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x13 3097 #define UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x16 3098 #define UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x19 3099 #define UVD_RBC_BUF_STATUS__RB_BUF_VALID_MASK 0x000000FFL 3100 #define UVD_RBC_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FF00L 3101 #define UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x00070000L 3102 #define UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x00380000L 3103 #define UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x01C00000L 3104 #define UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x0E000000L 3105 //UVD_RBC_IB_SIZE_UPDATE 3106 #define UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 3107 #define UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L 3108 //UVD_RBC_BDM_PRE 3109 #define UVD_RBC_BDM_PRE__BDM_ENABLE__SHIFT 0x0 3110 #define UVD_RBC_BDM_PRE__BDM_ENABLE_MASK 0x00000001L 3111 //CG_TIMESTAMP_LOW 3112 #define CG_TIMESTAMP_LOW__CG_LOW__SHIFT 0x0 3113 #define CG_TIMESTAMP_LOW__CG_LOW_MASK 0xFFFFFFFFL 3114 //CG_TIMESTAMP_HIGH 3115 #define CG_TIMESTAMP_HIGH__CG_HIGH__SHIFT 0x0 3116 #define CG_TIMESTAMP_HIGH__CG_HIGH_MASK 0xFFFFFFFFL 3117 //UVD_UMC_UVD_CTL_CMD 3118 #define UVD_UMC_UVD_CTL_CMD__CMC_REQ__SHIFT 0x0 3119 #define UVD_UMC_UVD_CTL_CMD__CMC_REQ_MASK 0x00000001L 3120 //UVD_UMC_UVD_BLOCK_REQ 3121 #define UVD_UMC_UVD_BLOCK_REQ__CMC_BLOCK_REQ__SHIFT 0x0 3122 #define UVD_UMC_UVD_BLOCK_REQ__CMC_BLOCK_REQ_MASK 0x00000001L 3123 //UVD_RBC_CXW_RELEASE 3124 #define UVD_RBC_CXW_RELEASE__SOFT_RELEASE_RBC__SHIFT 0x0 3125 #define UVD_RBC_CXW_RELEASE__SOFT_RELEASE_RBC_MASK 0x00000001L 3126 //UVD_YBASE 3127 #define UVD_YBASE__DUM__SHIFT 0x0 3128 #define UVD_YBASE__DUM_MASK 0xFFFFFFFFL 3129 //UVD_UVBASE 3130 #define UVD_UVBASE__DUM__SHIFT 0x0 3131 #define UVD_UVBASE__DUM_MASK 0xFFFFFFFFL 3132 //UVD_PITCH 3133 #define UVD_PITCH__DUM__SHIFT 0x0 3134 #define UVD_PITCH__DUM_MASK 0xFFFFFFFFL 3135 //UVD_WIDTH 3136 #define UVD_WIDTH__DUM__SHIFT 0x0 3137 #define UVD_WIDTH__DUM_MASK 0xFFFFFFFFL 3138 //UVD_HEIGHT 3139 #define UVD_HEIGHT__DUM__SHIFT 0x0 3140 #define UVD_HEIGHT__DUM_MASK 0xFFFFFFFFL 3141 //UVD_PICCOUNT 3142 #define UVD_PICCOUNT__DUM__SHIFT 0x0 3143 #define UVD_PICCOUNT__DUM_MASK 0xFFFFFFFFL 3144 3145 3146 // addressBlock: uvd0_uvdnpdec 3147 //UVD_SEMA_ADDR_LOW 3148 #define UVD_SEMA_ADDR_LOW__ADDR_26_3__SHIFT 0x0 3149 #define UVD_SEMA_ADDR_LOW__ADDR_26_3_MASK 0x00FFFFFFL 3150 //UVD_SEMA_ADDR_HIGH 3151 #define UVD_SEMA_ADDR_HIGH__ADDR_47_27__SHIFT 0x0 3152 #define UVD_SEMA_ADDR_HIGH__ADDR_47_27_MASK 0x001FFFFFL 3153 //UVD_SEMA_CMD 3154 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0 3155 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 3156 #define UVD_SEMA_CMD__MODE__SHIFT 0x6 3157 #define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7 3158 #define UVD_SEMA_CMD__VMID__SHIFT 0x8 3159 #define UVD_SEMA_CMD__REQ_CMD_MASK 0x0000000FL 3160 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x00000030L 3161 #define UVD_SEMA_CMD__MODE_MASK 0x00000040L 3162 #define UVD_SEMA_CMD__VMID_EN_MASK 0x00000080L 3163 #define UVD_SEMA_CMD__VMID_MASK 0x00000F00L 3164 //UVD_GPCOM_VCPU_CMD 3165 #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0 3166 #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 3167 #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f 3168 #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x00000001L 3169 #define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7FFFFFFEL 3170 #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000L 3171 //UVD_GPCOM_VCPU_DATA0 3172 #define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 3173 #define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xFFFFFFFFL 3174 //UVD_GPCOM_VCPU_DATA1 3175 #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 3176 #define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xFFFFFFFFL 3177 //UVD_ENGINE_CNTL 3178 #define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0 3179 #define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1 3180 #define UVD_ENGINE_CNTL__NJ_PF_HANDLE_DISABLE__SHIFT 0x2 3181 #define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x00000001L 3182 #define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x00000002L 3183 #define UVD_ENGINE_CNTL__NJ_PF_HANDLE_DISABLE_MASK 0x00000004L 3184 //UVD_SUVD_CGC_GATE 3185 #define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0 3186 #define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1 3187 #define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2 3188 #define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3 3189 #define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4 3190 #define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 3191 #define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 3192 #define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 3193 #define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 3194 #define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 3195 #define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 3196 #define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 3197 #define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 3198 #define UVD_SUVD_CGC_GATE__SCLR__SHIFT 0xd 3199 #define UVD_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 3200 #define UVD_SUVD_CGC_GATE__ENT__SHIFT 0xf 3201 #define UVD_SUVD_CGC_GATE__IME__SHIFT 0x10 3202 #define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 3203 #define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 3204 #define UVD_SUVD_CGC_GATE__SITE__SHIFT 0x13 3205 #define UVD_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 3206 #define UVD_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 3207 #define UVD_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 3208 #define UVD_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 3209 #define UVD_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 3210 #define UVD_SUVD_CGC_GATE__EFC__SHIFT 0x19 3211 #define UVD_SUVD_CGC_GATE__SRE_MASK 0x00000001L 3212 #define UVD_SUVD_CGC_GATE__SIT_MASK 0x00000002L 3213 #define UVD_SUVD_CGC_GATE__SMP_MASK 0x00000004L 3214 #define UVD_SUVD_CGC_GATE__SCM_MASK 0x00000008L 3215 #define UVD_SUVD_CGC_GATE__SDB_MASK 0x00000010L 3216 #define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 3217 #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 3218 #define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 3219 #define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 3220 #define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 3221 #define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 3222 #define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 3223 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 3224 #define UVD_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 3225 #define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 3226 #define UVD_SUVD_CGC_GATE__ENT_MASK 0x00008000L 3227 #define UVD_SUVD_CGC_GATE__IME_MASK 0x00010000L 3228 #define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 3229 #define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 3230 #define UVD_SUVD_CGC_GATE__SITE_MASK 0x00080000L 3231 #define UVD_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 3232 #define UVD_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 3233 #define UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 3234 #define UVD_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 3235 #define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 3236 #define UVD_SUVD_CGC_GATE__EFC_MASK 0x02000000L 3237 //UVD_SUVD_CGC_STATUS 3238 #define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT 0x0 3239 #define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT 0x1 3240 #define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT 0x2 3241 #define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3 3242 #define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT 0x4 3243 #define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5 3244 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6 3245 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT 0x7 3246 #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT 0x8 3247 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 0x9 3248 #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa 3249 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb 3250 #define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT 0xc 3251 #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 0xd 3252 #define UVD_SUVD_CGC_STATUS__SCLR_DCLK__SHIFT 0xe 3253 #define UVD_SUVD_CGC_STATUS__UVD_SC__SHIFT 0xf 3254 #define UVD_SUVD_CGC_STATUS__ENT_DCLK__SHIFT 0x10 3255 #define UVD_SUVD_CGC_STATUS__IME_DCLK__SHIFT 0x11 3256 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK__SHIFT 0x12 3257 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK__SHIFT 0x13 3258 #define UVD_SUVD_CGC_STATUS__SITE_DCLK__SHIFT 0x14 3259 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK__SHIFT 0x15 3260 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK__SHIFT 0x16 3261 #define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK__SHIFT 0x17 3262 #define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK__SHIFT 0x18 3263 #define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK__SHIFT 0x19 3264 #define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK__SHIFT 0x1a 3265 #define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK__SHIFT 0x1b 3266 #define UVD_SUVD_CGC_STATUS__EFC_DCLK__SHIFT 0x1c 3267 #define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 0x00000001L 3268 #define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x00000002L 3269 #define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 0x00000004L 3270 #define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x00000008L 3271 #define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x00000010L 3272 #define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x00000020L 3273 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x00000040L 3274 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x00000080L 3275 #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x00000100L 3276 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x00000200L 3277 #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK 0x00000400L 3278 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x00000800L 3279 #define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK 0x00001000L 3280 #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 0x00002000L 3281 #define UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK 0x00004000L 3282 #define UVD_SUVD_CGC_STATUS__UVD_SC_MASK 0x00008000L 3283 #define UVD_SUVD_CGC_STATUS__ENT_DCLK_MASK 0x00010000L 3284 #define UVD_SUVD_CGC_STATUS__IME_DCLK_MASK 0x00020000L 3285 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK_MASK 0x00040000L 3286 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK_MASK 0x00080000L 3287 #define UVD_SUVD_CGC_STATUS__SITE_DCLK_MASK 0x00100000L 3288 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK_MASK 0x00200000L 3289 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK_MASK 0x00400000L 3290 #define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK_MASK 0x00800000L 3291 #define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK_MASK 0x01000000L 3292 #define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK_MASK 0x02000000L 3293 #define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK_MASK 0x04000000L 3294 #define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK_MASK 0x08000000L 3295 #define UVD_SUVD_CGC_STATUS__EFC_DCLK_MASK 0x10000000L 3296 //UVD_SUVD_CGC_CTRL 3297 #define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 3298 #define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 3299 #define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 3300 #define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 3301 #define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 3302 #define UVD_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 3303 #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 3304 #define UVD_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 3305 #define UVD_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 3306 #define UVD_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 3307 #define UVD_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 3308 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 3309 #define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 3310 #define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 3311 #define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 3312 #define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 3313 #define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 3314 #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 3315 #define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 3316 #define UVD_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 3317 #define UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 3318 #define UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 3319 //UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 3320 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3321 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3322 //UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 3323 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3324 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3325 //UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW 3326 #define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3327 #define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3328 //UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH 3329 #define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3330 #define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3331 //UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 3332 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3333 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3334 //UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 3335 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3336 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3337 //UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW 3338 #define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3339 #define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3340 //UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH 3341 #define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3342 #define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3343 //UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW 3344 #define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3345 #define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3346 //UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH 3347 #define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3348 #define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3349 //UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW 3350 #define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3351 #define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3352 //UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH 3353 #define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3354 #define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3355 //UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW 3356 #define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3357 #define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3358 //UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH 3359 #define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3360 #define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3361 //UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW 3362 #define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3363 #define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3364 //UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH 3365 #define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3366 #define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3367 //UVD_SCRATCH_NP 3368 #define UVD_SCRATCH_NP__DATA__SHIFT 0x0 3369 #define UVD_SCRATCH_NP__DATA_MASK 0xFFFFFFFFL 3370 //UVD_NO_OP 3371 #define UVD_NO_OP__NO_OP__SHIFT 0x0 3372 #define UVD_NO_OP__NO_OP_MASK 0xFFFFFFFFL 3373 //MDM_DMA_CMD 3374 #define MDM_DMA_CMD__MDM_DMA_CMD__SHIFT 0x0 3375 #define MDM_DMA_CMD__MDM_DMA_CMD_MASK 0xFFFFFFFFL 3376 //MDM_DMA_STATUS 3377 #define MDM_DMA_STATUS__SDB_DMA_WR_BUSY__SHIFT 0x0 3378 #define MDM_DMA_STATUS__SCM_DMA_WR_BUSY__SHIFT 0x1 3379 #define MDM_DMA_STATUS__SCM_DMA_RD_BUSY__SHIFT 0x2 3380 #define MDM_DMA_STATUS__RB_DMA_WR_BUSY__SHIFT 0x3 3381 #define MDM_DMA_STATUS__RB_DMA_RD_BUSY__SHIFT 0x4 3382 #define MDM_DMA_STATUS__SDB_DMA_RD_BUSY__SHIFT 0x5 3383 #define MDM_DMA_STATUS__SCLR_DMA_WR_BUSY__SHIFT 0x6 3384 #define MDM_DMA_STATUS__SDB_DMA_WR_BUSY_MASK 0x00000001L 3385 #define MDM_DMA_STATUS__SCM_DMA_WR_BUSY_MASK 0x00000002L 3386 #define MDM_DMA_STATUS__SCM_DMA_RD_BUSY_MASK 0x00000004L 3387 #define MDM_DMA_STATUS__RB_DMA_WR_BUSY_MASK 0x00000008L 3388 #define MDM_DMA_STATUS__RB_DMA_RD_BUSY_MASK 0x00000010L 3389 #define MDM_DMA_STATUS__SDB_DMA_RD_BUSY_MASK 0x00000020L 3390 #define MDM_DMA_STATUS__SCLR_DMA_WR_BUSY_MASK 0x00000040L 3391 //MDM_DMA_CTL 3392 #define MDM_DMA_CTL__MDM_BYPASS__SHIFT 0x0 3393 #define MDM_DMA_CTL__FOUR_CMD__SHIFT 0x1 3394 #define MDM_DMA_CTL__ENCODE_MODE__SHIFT 0x2 3395 #define MDM_DMA_CTL__VP9_DEC_MODE__SHIFT 0x3 3396 #define MDM_DMA_CTL__SW_DRST__SHIFT 0x1f 3397 #define MDM_DMA_CTL__MDM_BYPASS_MASK 0x00000001L 3398 #define MDM_DMA_CTL__FOUR_CMD_MASK 0x00000002L 3399 #define MDM_DMA_CTL__ENCODE_MODE_MASK 0x00000004L 3400 #define MDM_DMA_CTL__VP9_DEC_MODE_MASK 0x00000008L 3401 #define MDM_DMA_CTL__SW_DRST_MASK 0x80000000L 3402 //MDM_ENC_PIPE_BUSY 3403 #define MDM_ENC_PIPE_BUSY__IME_BUSY__SHIFT 0x0 3404 #define MDM_ENC_PIPE_BUSY__SMP_BUSY__SHIFT 0x1 3405 #define MDM_ENC_PIPE_BUSY__SIT_BUSY__SHIFT 0x2 3406 #define MDM_ENC_PIPE_BUSY__SDB_BUSY__SHIFT 0x3 3407 #define MDM_ENC_PIPE_BUSY__ENT_BUSY__SHIFT 0x4 3408 #define MDM_ENC_PIPE_BUSY__ENT_HEADER_BUSY__SHIFT 0x5 3409 #define MDM_ENC_PIPE_BUSY__LCM_BUSY__SHIFT 0x6 3410 #define MDM_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY__SHIFT 0x7 3411 #define MDM_ENC_PIPE_BUSY__MDM_RD_REF_BUSY__SHIFT 0x8 3412 #define MDM_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY__SHIFT 0x9 3413 #define MDM_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY__SHIFT 0xa 3414 #define MDM_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY__SHIFT 0xb 3415 #define MDM_ENC_PIPE_BUSY__MDM_EFC_BUSY__SHIFT 0xc 3416 #define MDM_ENC_PIPE_BUSY__MDM_EFC_PROGRAM_BUSY__SHIFT 0xd 3417 #define MDM_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY__SHIFT 0x10 3418 #define MDM_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY__SHIFT 0x11 3419 #define MDM_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY__SHIFT 0x12 3420 #define MDM_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY__SHIFT 0x13 3421 #define MDM_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY__SHIFT 0x14 3422 #define MDM_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY__SHIFT 0x15 3423 #define MDM_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY__SHIFT 0x16 3424 #define MDM_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY__SHIFT 0x17 3425 #define MDM_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY__SHIFT 0x18 3426 #define MDM_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY__SHIFT 0x19 3427 #define MDM_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY__SHIFT 0x1a 3428 #define MDM_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY__SHIFT 0x1b 3429 #define MDM_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY__SHIFT 0x1c 3430 #define MDM_ENC_PIPE_BUSY__IME_BUSY_MASK 0x00000001L 3431 #define MDM_ENC_PIPE_BUSY__SMP_BUSY_MASK 0x00000002L 3432 #define MDM_ENC_PIPE_BUSY__SIT_BUSY_MASK 0x00000004L 3433 #define MDM_ENC_PIPE_BUSY__SDB_BUSY_MASK 0x00000008L 3434 #define MDM_ENC_PIPE_BUSY__ENT_BUSY_MASK 0x00000010L 3435 #define MDM_ENC_PIPE_BUSY__ENT_HEADER_BUSY_MASK 0x00000020L 3436 #define MDM_ENC_PIPE_BUSY__LCM_BUSY_MASK 0x00000040L 3437 #define MDM_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY_MASK 0x00000080L 3438 #define MDM_ENC_PIPE_BUSY__MDM_RD_REF_BUSY_MASK 0x00000100L 3439 #define MDM_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY_MASK 0x00000200L 3440 #define MDM_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY_MASK 0x00000400L 3441 #define MDM_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY_MASK 0x00000800L 3442 #define MDM_ENC_PIPE_BUSY__MDM_EFC_BUSY_MASK 0x00001000L 3443 #define MDM_ENC_PIPE_BUSY__MDM_EFC_PROGRAM_BUSY_MASK 0x00002000L 3444 #define MDM_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY_MASK 0x00010000L 3445 #define MDM_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY_MASK 0x00020000L 3446 #define MDM_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY_MASK 0x00040000L 3447 #define MDM_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY_MASK 0x00080000L 3448 #define MDM_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY_MASK 0x00100000L 3449 #define MDM_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY_MASK 0x00200000L 3450 #define MDM_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY_MASK 0x00400000L 3451 #define MDM_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY_MASK 0x00800000L 3452 #define MDM_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY_MASK 0x01000000L 3453 #define MDM_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY_MASK 0x02000000L 3454 #define MDM_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY_MASK 0x04000000L 3455 #define MDM_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY_MASK 0x08000000L 3456 #define MDM_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY_MASK 0x10000000L 3457 //MDM_WIG_PIPE_BUSY 3458 #define MDM_WIG_PIPE_BUSY__WIG_TBE_BUSY__SHIFT 0x0 3459 #define MDM_WIG_PIPE_BUSY__WIG_ENT_BUSY__SHIFT 0x1 3460 #define MDM_WIG_PIPE_BUSY__WIG_ENT_HEADER_BUSY__SHIFT 0x2 3461 #define MDM_WIG_PIPE_BUSY__WIG_ENT_HEADER_FIFO_FULL__SHIFT 0x3 3462 #define MDM_WIG_PIPE_BUSY__LCM_BUSY__SHIFT 0x4 3463 #define MDM_WIG_PIPE_BUSY__MDM_RD_CUR_BUSY__SHIFT 0x5 3464 #define MDM_WIG_PIPE_BUSY__MDM_RD_REF_BUSY__SHIFT 0x6 3465 #define MDM_WIG_PIPE_BUSY__MDM_RD_GEN_BUSY__SHIFT 0x7 3466 #define MDM_WIG_PIPE_BUSY__MDM_WR_RECON_BUSY__SHIFT 0x8 3467 #define MDM_WIG_PIPE_BUSY__MDM_WR_GEN_BUSY__SHIFT 0x9 3468 #define MDM_WIG_PIPE_BUSY__MIF_RD_CUR_BUSY__SHIFT 0xa 3469 #define MDM_WIG_PIPE_BUSY__MIF_RD_REF0_BUSY__SHIFT 0xb 3470 #define MDM_WIG_PIPE_BUSY__MIF_WR_GEN0_BUSY__SHIFT 0xc 3471 #define MDM_WIG_PIPE_BUSY__MIF_RD_GEN0_BUSY__SHIFT 0xd 3472 #define MDM_WIG_PIPE_BUSY__MIF_WR_GEN1_BUSY__SHIFT 0xe 3473 #define MDM_WIG_PIPE_BUSY__MIF_RD_GEN1_BUSY__SHIFT 0xf 3474 #define MDM_WIG_PIPE_BUSY__MIF_WR_BSP0_BUSY__SHIFT 0x10 3475 #define MDM_WIG_PIPE_BUSY__MIF_WR_BSP1_BUSY__SHIFT 0x11 3476 #define MDM_WIG_PIPE_BUSY__MIF_RD_BSD0_BUSY__SHIFT 0x12 3477 #define MDM_WIG_PIPE_BUSY__MIF_RD_BSD1_BUSY__SHIFT 0x13 3478 #define MDM_WIG_PIPE_BUSY__MIF_RD_BSD2_BUSY__SHIFT 0x14 3479 #define MDM_WIG_PIPE_BUSY__MIF_RD_BSD3_BUSY__SHIFT 0x15 3480 #define MDM_WIG_PIPE_BUSY__MIF_RD_BSD4_BUSY__SHIFT 0x16 3481 #define MDM_WIG_PIPE_BUSY__MIF_RD_BSD5_BUSY__SHIFT 0x17 3482 #define MDM_WIG_PIPE_BUSY__MIF_WR_BSP2_BUSY__SHIFT 0x18 3483 #define MDM_WIG_PIPE_BUSY__MIF_WR_BSP3_BUSY__SHIFT 0x19 3484 #define MDM_WIG_PIPE_BUSY__LCM_BSP0_NOT_EMPTY__SHIFT 0x1a 3485 #define MDM_WIG_PIPE_BUSY__LCM_BSP1_NOT_EMPTY__SHIFT 0x1b 3486 #define MDM_WIG_PIPE_BUSY__LCM_BSP2_NOT_EMPTY__SHIFT 0x1c 3487 #define MDM_WIG_PIPE_BUSY__LCM_BSP3_NOT_EMPTY__SHIFT 0x1d 3488 #define MDM_WIG_PIPE_BUSY__WIG_TBE_BUSY_MASK 0x00000001L 3489 #define MDM_WIG_PIPE_BUSY__WIG_ENT_BUSY_MASK 0x00000002L 3490 #define MDM_WIG_PIPE_BUSY__WIG_ENT_HEADER_BUSY_MASK 0x00000004L 3491 #define MDM_WIG_PIPE_BUSY__WIG_ENT_HEADER_FIFO_FULL_MASK 0x00000008L 3492 #define MDM_WIG_PIPE_BUSY__LCM_BUSY_MASK 0x00000010L 3493 #define MDM_WIG_PIPE_BUSY__MDM_RD_CUR_BUSY_MASK 0x00000020L 3494 #define MDM_WIG_PIPE_BUSY__MDM_RD_REF_BUSY_MASK 0x00000040L 3495 #define MDM_WIG_PIPE_BUSY__MDM_RD_GEN_BUSY_MASK 0x00000080L 3496 #define MDM_WIG_PIPE_BUSY__MDM_WR_RECON_BUSY_MASK 0x00000100L 3497 #define MDM_WIG_PIPE_BUSY__MDM_WR_GEN_BUSY_MASK 0x00000200L 3498 #define MDM_WIG_PIPE_BUSY__MIF_RD_CUR_BUSY_MASK 0x00000400L 3499 #define MDM_WIG_PIPE_BUSY__MIF_RD_REF0_BUSY_MASK 0x00000800L 3500 #define MDM_WIG_PIPE_BUSY__MIF_WR_GEN0_BUSY_MASK 0x00001000L 3501 #define MDM_WIG_PIPE_BUSY__MIF_RD_GEN0_BUSY_MASK 0x00002000L 3502 #define MDM_WIG_PIPE_BUSY__MIF_WR_GEN1_BUSY_MASK 0x00004000L 3503 #define MDM_WIG_PIPE_BUSY__MIF_RD_GEN1_BUSY_MASK 0x00008000L 3504 #define MDM_WIG_PIPE_BUSY__MIF_WR_BSP0_BUSY_MASK 0x00010000L 3505 #define MDM_WIG_PIPE_BUSY__MIF_WR_BSP1_BUSY_MASK 0x00020000L 3506 #define MDM_WIG_PIPE_BUSY__MIF_RD_BSD0_BUSY_MASK 0x00040000L 3507 #define MDM_WIG_PIPE_BUSY__MIF_RD_BSD1_BUSY_MASK 0x00080000L 3508 #define MDM_WIG_PIPE_BUSY__MIF_RD_BSD2_BUSY_MASK 0x00100000L 3509 #define MDM_WIG_PIPE_BUSY__MIF_RD_BSD3_BUSY_MASK 0x00200000L 3510 #define MDM_WIG_PIPE_BUSY__MIF_RD_BSD4_BUSY_MASK 0x00400000L 3511 #define MDM_WIG_PIPE_BUSY__MIF_RD_BSD5_BUSY_MASK 0x00800000L 3512 #define MDM_WIG_PIPE_BUSY__MIF_WR_BSP2_BUSY_MASK 0x01000000L 3513 #define MDM_WIG_PIPE_BUSY__MIF_WR_BSP3_BUSY_MASK 0x02000000L 3514 #define MDM_WIG_PIPE_BUSY__LCM_BSP0_NOT_EMPTY_MASK 0x04000000L 3515 #define MDM_WIG_PIPE_BUSY__LCM_BSP1_NOT_EMPTY_MASK 0x08000000L 3516 #define MDM_WIG_PIPE_BUSY__LCM_BSP2_NOT_EMPTY_MASK 0x10000000L 3517 #define MDM_WIG_PIPE_BUSY__LCM_BSP3_NOT_EMPTY_MASK 0x20000000L 3518 //UVD_VERSION 3519 #define UVD_VERSION__MINOR_VERSION__SHIFT 0x0 3520 #define UVD_VERSION__MAJOR_VERSION__SHIFT 0x10 3521 #define UVD_VERSION__MINOR_VERSION_MASK 0x0000FFFFL 3522 #define UVD_VERSION__MAJOR_VERSION_MASK 0xFFFF0000L 3523 //UVD_GP_SCRATCH8 3524 #define UVD_GP_SCRATCH8__DATA__SHIFT 0x0 3525 #define UVD_GP_SCRATCH8__DATA_MASK 0xFFFFFFFFL 3526 //UVD_GP_SCRATCH9 3527 #define UVD_GP_SCRATCH9__DATA__SHIFT 0x0 3528 #define UVD_GP_SCRATCH9__DATA_MASK 0xFFFFFFFFL 3529 //UVD_GP_SCRATCH10 3530 #define UVD_GP_SCRATCH10__DATA__SHIFT 0x0 3531 #define UVD_GP_SCRATCH10__DATA_MASK 0xFFFFFFFFL 3532 //UVD_GP_SCRATCH11 3533 #define UVD_GP_SCRATCH11__DATA__SHIFT 0x0 3534 #define UVD_GP_SCRATCH11__DATA_MASK 0xFFFFFFFFL 3535 //UVD_GP_SCRATCH12 3536 #define UVD_GP_SCRATCH12__DATA__SHIFT 0x0 3537 #define UVD_GP_SCRATCH12__DATA_MASK 0xFFFFFFFFL 3538 //UVD_GP_SCRATCH13 3539 #define UVD_GP_SCRATCH13__DATA__SHIFT 0x0 3540 #define UVD_GP_SCRATCH13__DATA_MASK 0xFFFFFFFFL 3541 //UVD_GP_SCRATCH14 3542 #define UVD_GP_SCRATCH14__DATA__SHIFT 0x0 3543 #define UVD_GP_SCRATCH14__DATA_MASK 0xFFFFFFFFL 3544 //UVD_GP_SCRATCH15 3545 #define UVD_GP_SCRATCH15__DATA__SHIFT 0x0 3546 #define UVD_GP_SCRATCH15__DATA_MASK 0xFFFFFFFFL 3547 //UVD_GP_SCRATCH16 3548 #define UVD_GP_SCRATCH16__DATA__SHIFT 0x0 3549 #define UVD_GP_SCRATCH16__DATA_MASK 0xFFFFFFFFL 3550 //UVD_GP_SCRATCH17 3551 #define UVD_GP_SCRATCH17__DATA__SHIFT 0x0 3552 #define UVD_GP_SCRATCH17__DATA_MASK 0xFFFFFFFFL 3553 //UVD_GP_SCRATCH18 3554 #define UVD_GP_SCRATCH18__DATA__SHIFT 0x0 3555 #define UVD_GP_SCRATCH18__DATA_MASK 0xFFFFFFFFL 3556 //UVD_GP_SCRATCH19 3557 #define UVD_GP_SCRATCH19__DATA__SHIFT 0x0 3558 #define UVD_GP_SCRATCH19__DATA_MASK 0xFFFFFFFFL 3559 //UVD_GP_SCRATCH20 3560 #define UVD_GP_SCRATCH20__DATA__SHIFT 0x0 3561 #define UVD_GP_SCRATCH20__DATA_MASK 0xFFFFFFFFL 3562 //UVD_GP_SCRATCH21 3563 #define UVD_GP_SCRATCH21__DATA__SHIFT 0x0 3564 #define UVD_GP_SCRATCH21__DATA_MASK 0xFFFFFFFFL 3565 //UVD_GP_SCRATCH22 3566 #define UVD_GP_SCRATCH22__DATA__SHIFT 0x0 3567 #define UVD_GP_SCRATCH22__DATA_MASK 0xFFFFFFFFL 3568 //UVD_GP_SCRATCH23 3569 #define UVD_GP_SCRATCH23__DATA__SHIFT 0x0 3570 #define UVD_GP_SCRATCH23__DATA_MASK 0xFFFFFFFFL 3571 //UVD_ENC_REG_INDEX 3572 #define UVD_ENC_REG_INDEX__INDEX__SHIFT 0x0 3573 #define UVD_ENC_REG_INDEX__INDEX_MASK 0x00001FFFL 3574 //UVD_ENC_REG_DATA 3575 #define UVD_ENC_REG_DATA__DATA__SHIFT 0x0 3576 #define UVD_ENC_REG_DATA__DATA_MASK 0xFFFFFFFFL 3577 //UVD_OUT_RB_BASE_LO 3578 #define UVD_OUT_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 3579 #define UVD_OUT_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L 3580 //UVD_OUT_RB_BASE_HI 3581 #define UVD_OUT_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 3582 #define UVD_OUT_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL 3583 //UVD_OUT_RB_SIZE 3584 #define UVD_OUT_RB_SIZE__RB_SIZE__SHIFT 0x4 3585 #define UVD_OUT_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L 3586 //UVD_OUT_RB_RPTR 3587 #define UVD_OUT_RB_RPTR__RB_RPTR__SHIFT 0x4 3588 #define UVD_OUT_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 3589 //UVD_OUT_RB_WPTR 3590 #define UVD_OUT_RB_WPTR__RB_WPTR__SHIFT 0x4 3591 #define UVD_OUT_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 3592 //UVD_RB_BASE_LO2 3593 #define UVD_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6 3594 #define UVD_RB_BASE_LO2__RB_BASE_LO_MASK 0xFFFFFFC0L 3595 //UVD_RB_BASE_HI2 3596 #define UVD_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0 3597 #define UVD_RB_BASE_HI2__RB_BASE_HI_MASK 0xFFFFFFFFL 3598 //UVD_RB_SIZE2 3599 #define UVD_RB_SIZE2__RB_SIZE__SHIFT 0x4 3600 #define UVD_RB_SIZE2__RB_SIZE_MASK 0x007FFFF0L 3601 //UVD_RB_RPTR2 3602 #define UVD_RB_RPTR2__RB_RPTR__SHIFT 0x4 3603 #define UVD_RB_RPTR2__RB_RPTR_MASK 0x007FFFF0L 3604 //UVD_RB_WPTR2 3605 #define UVD_RB_WPTR2__RB_WPTR__SHIFT 0x4 3606 #define UVD_RB_WPTR2__RB_WPTR_MASK 0x007FFFF0L 3607 //UVD_RB_BASE_LO 3608 #define UVD_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 3609 #define UVD_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L 3610 //UVD_RB_BASE_HI 3611 #define UVD_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 3612 #define UVD_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL 3613 //UVD_RB_SIZE 3614 #define UVD_RB_SIZE__RB_SIZE__SHIFT 0x4 3615 #define UVD_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L 3616 //UVD_RB_RPTR 3617 #define UVD_RB_RPTR__RB_RPTR__SHIFT 0x4 3618 #define UVD_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 3619 //UVD_RB_WPTR 3620 #define UVD_RB_WPTR__RB_WPTR__SHIFT 0x4 3621 #define UVD_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 3622 //UVD_ENC_PIPE_BUSY 3623 #define UVD_ENC_PIPE_BUSY__IME_BUSY__SHIFT 0x0 3624 #define UVD_ENC_PIPE_BUSY__SMP_BUSY__SHIFT 0x1 3625 #define UVD_ENC_PIPE_BUSY__SIT_BUSY__SHIFT 0x2 3626 #define UVD_ENC_PIPE_BUSY__SDB_BUSY__SHIFT 0x3 3627 #define UVD_ENC_PIPE_BUSY__ENT_BUSY__SHIFT 0x4 3628 #define UVD_ENC_PIPE_BUSY__ENT_HEADER_BUSY__SHIFT 0x5 3629 #define UVD_ENC_PIPE_BUSY__LCM_BUSY__SHIFT 0x6 3630 #define UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY__SHIFT 0x7 3631 #define UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY__SHIFT 0x8 3632 #define UVD_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY__SHIFT 0x9 3633 #define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY__SHIFT 0xa 3634 #define UVD_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY__SHIFT 0xb 3635 #define UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY__SHIFT 0x10 3636 #define UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY__SHIFT 0x11 3637 #define UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY__SHIFT 0x12 3638 #define UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY__SHIFT 0x13 3639 #define UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY__SHIFT 0x14 3640 #define UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY__SHIFT 0x15 3641 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY__SHIFT 0x16 3642 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY__SHIFT 0x17 3643 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY__SHIFT 0x18 3644 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY__SHIFT 0x19 3645 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY__SHIFT 0x1a 3646 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY__SHIFT 0x1b 3647 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY__SHIFT 0x1c 3648 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY__SHIFT 0x1d 3649 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY__SHIFT 0x1e 3650 #define UVD_ENC_PIPE_BUSY__IME_BUSY_MASK 0x00000001L 3651 #define UVD_ENC_PIPE_BUSY__SMP_BUSY_MASK 0x00000002L 3652 #define UVD_ENC_PIPE_BUSY__SIT_BUSY_MASK 0x00000004L 3653 #define UVD_ENC_PIPE_BUSY__SDB_BUSY_MASK 0x00000008L 3654 #define UVD_ENC_PIPE_BUSY__ENT_BUSY_MASK 0x00000010L 3655 #define UVD_ENC_PIPE_BUSY__ENT_HEADER_BUSY_MASK 0x00000020L 3656 #define UVD_ENC_PIPE_BUSY__LCM_BUSY_MASK 0x00000040L 3657 #define UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY_MASK 0x00000080L 3658 #define UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY_MASK 0x00000100L 3659 #define UVD_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY_MASK 0x00000200L 3660 #define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY_MASK 0x00000400L 3661 #define UVD_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY_MASK 0x00000800L 3662 #define UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY_MASK 0x00010000L 3663 #define UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY_MASK 0x00020000L 3664 #define UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY_MASK 0x00040000L 3665 #define UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY_MASK 0x00080000L 3666 #define UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY_MASK 0x00100000L 3667 #define UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY_MASK 0x00200000L 3668 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY_MASK 0x00400000L 3669 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY_MASK 0x00800000L 3670 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY_MASK 0x01000000L 3671 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY_MASK 0x02000000L 3672 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY_MASK 0x04000000L 3673 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY_MASK 0x08000000L 3674 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY_MASK 0x10000000L 3675 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY_MASK 0x20000000L 3676 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY_MASK 0x40000000L 3677 //UVD_RB_WPTR4 3678 #define UVD_RB_WPTR4__RB_WPTR__SHIFT 0x4 3679 #define UVD_RB_WPTR4__RB_WPTR_MASK 0x007FFFF0L 3680 //UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 3681 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3682 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3683 //UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 3684 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3685 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3686 //UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH 3687 #define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3688 #define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3689 //UVD_LMI_VCPU_NC1_64BIT_BAR_LOW 3690 #define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3691 #define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3692 //UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH 3693 #define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3694 #define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3695 //UVD_LMI_VCPU_NC0_64BIT_BAR_LOW 3696 #define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3697 #define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3698 //UVD_LMI_RBC_IB_64BIT_BAR_HIGH 3699 #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3700 #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3701 //UVD_LMI_RBC_IB_64BIT_BAR_LOW 3702 #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3703 #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3704 //UVD_LMI_RBC_RB_64BIT_BAR_HIGH 3705 #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3706 #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3707 //UVD_LMI_RBC_RB_64BIT_BAR_LOW 3708 #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3709 #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3710 3711 3712 // addressBlock: uvd0_uvdnp2dec 3713 //UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW 3714 #define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3715 #define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3716 //UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH 3717 #define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3718 #define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3719 //UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW 3720 #define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3721 #define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3722 //UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH 3723 #define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3724 #define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3725 //UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW 3726 #define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3727 #define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3728 //UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH 3729 #define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3730 #define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3731 //UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW 3732 #define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3733 #define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3734 //UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH 3735 #define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3736 #define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3737 //UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW 3738 #define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3739 #define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3740 //UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH 3741 #define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3742 #define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3743 //UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW 3744 #define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3745 #define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3746 //UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH 3747 #define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3748 #define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3749 //UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW 3750 #define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3751 #define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3752 //UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH 3753 #define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3754 #define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3755 //UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW 3756 #define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3757 #define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3758 //UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH 3759 #define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3760 #define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3761 //UVD_LMI_MMSCH_NC_VMID 3762 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID__SHIFT 0x0 3763 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID__SHIFT 0x4 3764 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID__SHIFT 0x8 3765 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID__SHIFT 0xc 3766 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID__SHIFT 0x10 3767 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID__SHIFT 0x14 3768 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID__SHIFT 0x18 3769 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID__SHIFT 0x1c 3770 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID_MASK 0x0000000FL 3771 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID_MASK 0x000000F0L 3772 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID_MASK 0x00000F00L 3773 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID_MASK 0x0000F000L 3774 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID_MASK 0x000F0000L 3775 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID_MASK 0x00F00000L 3776 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID_MASK 0x0F000000L 3777 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID_MASK 0xF0000000L 3778 //UVD_LMI_MMSCH_CTRL 3779 #define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN__SHIFT 0x0 3780 #define UVD_LMI_MMSCH_CTRL__MMSCH_VM__SHIFT 0x1 3781 #define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP__SHIFT 0x3 3782 #define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP__SHIFT 0x5 3783 #define UVD_LMI_MMSCH_CTRL__MMSCH_RD__SHIFT 0x7 3784 #define UVD_LMI_MMSCH_CTRL__MMSCH_WR__SHIFT 0x9 3785 #define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP__SHIFT 0xb 3786 #define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP__SHIFT 0xc 3787 #define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN_MASK 0x00000001L 3788 #define UVD_LMI_MMSCH_CTRL__MMSCH_VM_MASK 0x00000002L 3789 #define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP_MASK 0x00000018L 3790 #define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP_MASK 0x00000060L 3791 #define UVD_LMI_MMSCH_CTRL__MMSCH_RD_MASK 0x00000180L 3792 #define UVD_LMI_MMSCH_CTRL__MMSCH_WR_MASK 0x00000600L 3793 #define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP_MASK 0x00000800L 3794 #define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP_MASK 0x00001000L 3795 //UVD_MMSCH_SOFT_RESET 3796 #define UVD_MMSCH_SOFT_RESET__MMSCH_RESET__SHIFT 0x0 3797 #define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x1 3798 #define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK__SHIFT 0x1f 3799 #define UVD_MMSCH_SOFT_RESET__MMSCH_RESET_MASK 0x00000001L 3800 #define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000002L 3801 #define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK_MASK 0x80000000L 3802 //UVD_LMI_ARB_CTRL2 3803 #define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN__SHIFT 0x0 3804 #define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN__SHIFT 0x1 3805 #define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST__SHIFT 0x2 3806 #define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST__SHIFT 0x6 3807 #define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX__SHIFT 0xa 3808 #define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX__SHIFT 0x14 3809 #define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN_MASK 0x00000001L 3810 #define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN_MASK 0x00000002L 3811 #define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST_MASK 0x0000003CL 3812 #define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST_MASK 0x000003C0L 3813 #define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX_MASK 0x000FFC00L 3814 #define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX_MASK 0xFFF00000L 3815 3816 3817 #endif 3818