1 /* $NetBSD: uvd_7_0_sh_mask.h,v 1.2 2021/12/18 23:45:24 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2017 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef _uvd_7_0_SH_MASK_HEADER 24 #define _uvd_7_0_SH_MASK_HEADER 25 26 27 // addressBlock: uvd0_uvd_pg_dec 28 //UVD_POWER_STATUS 29 #define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0 30 #define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2 31 #define UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT__SHIFT 0x3 32 #define UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT__SHIFT 0x4 33 #define UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT__SHIFT 0x5 34 #define UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE__SHIFT 0x6 35 #define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8 36 #define UVD_POWER_STATUS__PAUSE_DPG_REQ__SHIFT 0x9 37 #define UVD_POWER_STATUS__PAUSE_DPG_ACK__SHIFT 0xa 38 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000003L 39 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L 40 #define UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT_MASK 0x00000008L 41 #define UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT_MASK 0x00000010L 42 #define UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT_MASK 0x00000020L 43 #define UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE_MASK 0x000000C0L 44 #define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L 45 #define UVD_POWER_STATUS__PAUSE_DPG_REQ_MASK 0x00000200L 46 #define UVD_POWER_STATUS__PAUSE_DPG_ACK_MASK 0x00000400L 47 //UVD_DPG_RBC_RB_CNTL 48 #define UVD_DPG_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0 49 #define UVD_DPG_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8 50 #define UVD_DPG_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10 51 #define UVD_DPG_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14 52 #define UVD_DPG_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18 53 #define UVD_DPG_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c 54 #define UVD_DPG_RBC_RB_CNTL__RB_BUFSZ_MASK 0x0000001FL 55 #define UVD_DPG_RBC_RB_CNTL__RB_BLKSZ_MASK 0x00001F00L 56 #define UVD_DPG_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x00010000L 57 #define UVD_DPG_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x00100000L 58 #define UVD_DPG_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x01000000L 59 #define UVD_DPG_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000L 60 //UVD_DPG_RBC_RB_BASE_LOW 61 #define UVD_DPG_RBC_RB_BASE_LOW__RB_BASE_LOW__SHIFT 0x0 62 #define UVD_DPG_RBC_RB_BASE_LOW__RB_BASE_LOW_MASK 0xFFFFFFFFL 63 //UVD_DPG_RBC_RB_BASE_HIGH 64 #define UVD_DPG_RBC_RB_BASE_HIGH__RB_BASE_HIGH__SHIFT 0x0 65 #define UVD_DPG_RBC_RB_BASE_HIGH__RB_BASE_HIGH_MASK 0xFFFFFFFFL 66 //UVD_DPG_RBC_RB_WPTR_CNTL 67 #define UVD_DPG_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x0 68 #define UVD_DPG_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK 0x00007FFFL 69 //UVD_DPG_RBC_RB_RPTR 70 #define UVD_DPG_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4 71 #define UVD_DPG_RBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 72 //UVD_DPG_RBC_RB_WPTR 73 #define UVD_DPG_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4 74 #define UVD_DPG_RBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 75 //UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 76 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 77 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 78 //UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 79 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 80 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 81 //UVD_DPG_VCPU_CACHE_OFFSET0 82 #define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 83 #define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x01FFFFFFL 84 85 86 // addressBlock: uvd0_uvdnpdec 87 //UVD_JPEG_ADDR_CONFIG 88 #define UVD_JPEG_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 89 #define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 90 #define UVD_JPEG_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 91 #define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 92 #define UVD_JPEG_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 93 #define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 94 #define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 95 #define UVD_JPEG_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15 96 #define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 97 #define UVD_JPEG_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a 98 #define UVD_JPEG_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 99 #define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 100 #define UVD_JPEG_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f 101 #define UVD_JPEG_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 102 #define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 103 #define UVD_JPEG_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L 104 #define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 105 #define UVD_JPEG_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 106 #define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L 107 #define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 108 #define UVD_JPEG_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L 109 #define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L 110 #define UVD_JPEG_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L 111 #define UVD_JPEG_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L 112 #define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L 113 #define UVD_JPEG_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L 114 //UVD_GPCOM_VCPU_CMD 115 #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0 116 #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 117 #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f 118 #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x00000001L 119 #define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7FFFFFFEL 120 #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000L 121 //UVD_GPCOM_VCPU_DATA0 122 #define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 123 #define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xFFFFFFFFL 124 //UVD_GPCOM_VCPU_DATA1 125 #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 126 #define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xFFFFFFFFL 127 //UVD_UDEC_ADDR_CONFIG 128 #define UVD_UDEC_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 129 #define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 130 #define UVD_UDEC_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 131 #define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 132 #define UVD_UDEC_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 133 #define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 134 #define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 135 #define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15 136 #define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 137 #define UVD_UDEC_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a 138 #define UVD_UDEC_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 139 #define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 140 #define UVD_UDEC_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f 141 #define UVD_UDEC_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 142 #define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 143 #define UVD_UDEC_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L 144 #define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 145 #define UVD_UDEC_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 146 #define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L 147 #define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 148 #define UVD_UDEC_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L 149 #define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L 150 #define UVD_UDEC_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L 151 #define UVD_UDEC_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L 152 #define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L 153 #define UVD_UDEC_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L 154 //UVD_UDEC_DB_ADDR_CONFIG 155 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 156 #define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 157 #define UVD_UDEC_DB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 158 #define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 159 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 160 #define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 161 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 162 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15 163 #define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 164 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a 165 #define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 166 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 167 #define UVD_UDEC_DB_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f 168 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 169 #define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 170 #define UVD_UDEC_DB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L 171 #define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 172 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 173 #define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L 174 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 175 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L 176 #define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L 177 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L 178 #define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L 179 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L 180 #define UVD_UDEC_DB_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L 181 //UVD_UDEC_DBW_ADDR_CONFIG 182 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 183 #define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 184 #define UVD_UDEC_DBW_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 185 #define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 186 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 187 #define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 188 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 189 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15 190 #define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 191 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a 192 #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 193 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 194 #define UVD_UDEC_DBW_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f 195 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 196 #define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 197 #define UVD_UDEC_DBW_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L 198 #define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 199 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 200 #define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L 201 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 202 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L 203 #define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L 204 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L 205 #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L 206 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L 207 #define UVD_UDEC_DBW_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L 208 //UVD_SUVD_CGC_GATE 209 #define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0 210 #define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1 211 #define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2 212 #define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3 213 #define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4 214 #define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 215 #define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 216 #define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 217 #define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 218 #define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 219 #define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 220 #define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 221 #define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 222 #define UVD_SUVD_CGC_GATE__SCLR__SHIFT 0xd 223 #define UVD_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 224 #define UVD_SUVD_CGC_GATE__ENT__SHIFT 0xf 225 #define UVD_SUVD_CGC_GATE__IME__SHIFT 0x10 226 #define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 227 #define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 228 #define UVD_SUVD_CGC_GATE__SRE_MASK 0x00000001L 229 #define UVD_SUVD_CGC_GATE__SIT_MASK 0x00000002L 230 #define UVD_SUVD_CGC_GATE__SMP_MASK 0x00000004L 231 #define UVD_SUVD_CGC_GATE__SCM_MASK 0x00000008L 232 #define UVD_SUVD_CGC_GATE__SDB_MASK 0x00000010L 233 #define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 234 #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 235 #define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 236 #define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 237 #define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 238 #define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 239 #define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 240 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 241 #define UVD_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 242 #define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 243 #define UVD_SUVD_CGC_GATE__ENT_MASK 0x00008000L 244 #define UVD_SUVD_CGC_GATE__IME_MASK 0x00010000L 245 #define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 246 #define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 247 //UVD_SUVD_CGC_CTRL 248 #define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 249 #define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 250 #define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 251 #define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 252 #define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 253 #define UVD_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 254 #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 255 #define UVD_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 256 #define UVD_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 257 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 258 #define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 259 #define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 260 #define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 261 #define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 262 #define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 263 #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 264 #define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 265 #define UVD_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 266 //UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 267 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 268 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 269 //UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 270 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 271 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 272 //UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 273 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 274 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 275 //UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 276 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 277 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 278 //UVD_POWER_STATUS_U 279 #define UVD_POWER_STATUS_U__UVD_POWER_STATUS__SHIFT 0x0 280 #define UVD_POWER_STATUS_U__UVD_POWER_STATUS_MASK 0x00000003L 281 //UVD_NO_OP 282 #define UVD_NO_OP__NO_OP__SHIFT 0x0 283 #define UVD_NO_OP__NO_OP_MASK 0xFFFFFFFFL 284 //UVD_GP_SCRATCH8 285 #define UVD_GP_SCRATCH8__DATA__SHIFT 0x0 286 #define UVD_GP_SCRATCH8__DATA_MASK 0xFFFFFFFFL 287 //UVD_RB_BASE_LO2 288 #define UVD_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6 289 #define UVD_RB_BASE_LO2__RB_BASE_LO_MASK 0xFFFFFFC0L 290 //UVD_RB_BASE_HI2 291 #define UVD_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0 292 #define UVD_RB_BASE_HI2__RB_BASE_HI_MASK 0xFFFFFFFFL 293 //UVD_RB_SIZE2 294 #define UVD_RB_SIZE2__RB_SIZE__SHIFT 0x4 295 #define UVD_RB_SIZE2__RB_SIZE_MASK 0x007FFFF0L 296 //UVD_RB_RPTR2 297 #define UVD_RB_RPTR2__RB_RPTR__SHIFT 0x4 298 #define UVD_RB_RPTR2__RB_RPTR_MASK 0x007FFFF0L 299 //UVD_RB_WPTR2 300 #define UVD_RB_WPTR2__RB_WPTR__SHIFT 0x4 301 #define UVD_RB_WPTR2__RB_WPTR_MASK 0x007FFFF0L 302 //UVD_RB_BASE_LO 303 #define UVD_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 304 #define UVD_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L 305 //UVD_RB_BASE_HI 306 #define UVD_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 307 #define UVD_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL 308 //UVD_RB_SIZE 309 #define UVD_RB_SIZE__RB_SIZE__SHIFT 0x4 310 #define UVD_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L 311 //UVD_RB_RPTR 312 #define UVD_RB_RPTR__RB_RPTR__SHIFT 0x4 313 #define UVD_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 314 //UVD_RB_WPTR 315 #define UVD_RB_WPTR__RB_WPTR__SHIFT 0x4 316 #define UVD_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 317 //UVD_JRBC_RB_RPTR 318 #define UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT 0x4 319 #define UVD_JRBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 320 //UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 321 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 322 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 323 //UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 324 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 325 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 326 //UVD_LMI_RBC_IB_64BIT_BAR_HIGH 327 #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 328 #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 329 //UVD_LMI_RBC_IB_64BIT_BAR_LOW 330 #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 331 #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 332 //UVD_LMI_RBC_RB_64BIT_BAR_HIGH 333 #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 334 #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 335 //UVD_LMI_RBC_RB_64BIT_BAR_LOW 336 #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 337 #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 338 339 340 // addressBlock: uvd0_uvddec 341 //UVD_SEMA_CNTL 342 #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0 343 #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1 344 #define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x00000001L 345 #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x00000002L 346 //UVD_LMI_JRBC_RB_64BIT_BAR_LOW 347 #define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 348 #define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 349 //UVD_JRBC_RB_WPTR 350 #define UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT 0x4 351 #define UVD_JRBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 352 //UVD_RB_RPTR3 353 #define UVD_RB_RPTR3__RB_RPTR__SHIFT 0x4 354 #define UVD_RB_RPTR3__RB_RPTR_MASK 0x007FFFF0L 355 //UVD_RB_WPTR3 356 #define UVD_RB_WPTR3__RB_WPTR__SHIFT 0x4 357 #define UVD_RB_WPTR3__RB_WPTR_MASK 0x007FFFF0L 358 //UVD_RB_BASE_LO3 359 #define UVD_RB_BASE_LO3__RB_BASE_LO__SHIFT 0x6 360 #define UVD_RB_BASE_LO3__RB_BASE_LO_MASK 0xFFFFFFC0L 361 //UVD_RB_BASE_HI3 362 #define UVD_RB_BASE_HI3__RB_BASE_HI__SHIFT 0x0 363 #define UVD_RB_BASE_HI3__RB_BASE_HI_MASK 0xFFFFFFFFL 364 //UVD_RB_SIZE3 365 #define UVD_RB_SIZE3__RB_SIZE__SHIFT 0x4 366 #define UVD_RB_SIZE3__RB_SIZE_MASK 0x007FFFF0L 367 //JPEG_CGC_GATE 368 #define JPEG_CGC_GATE__JPEG__SHIFT 0x14 369 #define JPEG_CGC_GATE__JPEG2__SHIFT 0x15 370 #define JPEG_CGC_GATE__JPEG_MASK 0x00100000L 371 #define JPEG_CGC_GATE__JPEG2_MASK 0x00200000L 372 //UVD_CTX_INDEX 373 #define UVD_CTX_INDEX__INDEX__SHIFT 0x0 374 #define UVD_CTX_INDEX__INDEX_MASK 0x000001FFL 375 //UVD_CTX_DATA 376 #define UVD_CTX_DATA__DATA__SHIFT 0x0 377 #define UVD_CTX_DATA__DATA_MASK 0xFFFFFFFFL 378 //UVD_CGC_GATE 379 #define UVD_CGC_GATE__SYS__SHIFT 0x0 380 #define UVD_CGC_GATE__UDEC__SHIFT 0x1 381 #define UVD_CGC_GATE__MPEG2__SHIFT 0x2 382 #define UVD_CGC_GATE__REGS__SHIFT 0x3 383 #define UVD_CGC_GATE__RBC__SHIFT 0x4 384 #define UVD_CGC_GATE__LMI_MC__SHIFT 0x5 385 #define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6 386 #define UVD_CGC_GATE__IDCT__SHIFT 0x7 387 #define UVD_CGC_GATE__MPRD__SHIFT 0x8 388 #define UVD_CGC_GATE__MPC__SHIFT 0x9 389 #define UVD_CGC_GATE__LBSI__SHIFT 0xa 390 #define UVD_CGC_GATE__LRBBM__SHIFT 0xb 391 #define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc 392 #define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd 393 #define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe 394 #define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf 395 #define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10 396 #define UVD_CGC_GATE__WCB__SHIFT 0x11 397 #define UVD_CGC_GATE__VCPU__SHIFT 0x12 398 #define UVD_CGC_GATE__SCPU__SHIFT 0x13 399 #define UVD_CGC_GATE__SYS_MASK 0x00000001L 400 #define UVD_CGC_GATE__UDEC_MASK 0x00000002L 401 #define UVD_CGC_GATE__MPEG2_MASK 0x00000004L 402 #define UVD_CGC_GATE__REGS_MASK 0x00000008L 403 #define UVD_CGC_GATE__RBC_MASK 0x00000010L 404 #define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L 405 #define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L 406 #define UVD_CGC_GATE__IDCT_MASK 0x00000080L 407 #define UVD_CGC_GATE__MPRD_MASK 0x00000100L 408 #define UVD_CGC_GATE__MPC_MASK 0x00000200L 409 #define UVD_CGC_GATE__LBSI_MASK 0x00000400L 410 #define UVD_CGC_GATE__LRBBM_MASK 0x00000800L 411 #define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L 412 #define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L 413 #define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L 414 #define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L 415 #define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L 416 #define UVD_CGC_GATE__WCB_MASK 0x00020000L 417 #define UVD_CGC_GATE__VCPU_MASK 0x00040000L 418 #define UVD_CGC_GATE__SCPU_MASK 0x00080000L 419 //UVD_CGC_CTRL 420 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 421 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 422 #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 423 #define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb 424 #define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc 425 #define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd 426 #define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe 427 #define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf 428 #define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10 429 #define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11 430 #define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12 431 #define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13 432 #define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14 433 #define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15 434 #define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16 435 #define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17 436 #define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18 437 #define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19 438 #define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a 439 #define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b 440 #define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c 441 #define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d 442 #define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e 443 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L 444 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL 445 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L 446 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L 447 #define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L 448 #define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L 449 #define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L 450 #define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L 451 #define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L 452 #define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L 453 #define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L 454 #define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L 455 #define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L 456 #define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L 457 #define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L 458 #define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L 459 #define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L 460 #define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L 461 #define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L 462 #define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L 463 #define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L 464 #define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L 465 #define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000L 466 //UVD_GP_SCRATCH4 467 #define UVD_GP_SCRATCH4__DATA__SHIFT 0x0 468 #define UVD_GP_SCRATCH4__DATA_MASK 0xFFFFFFFFL 469 //UVD_LMI_CTRL2 470 #define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0 471 #define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1 472 #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2 473 #define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3 474 #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7 475 #define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 476 #define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 477 #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb 478 #define UVD_LMI_CTRL2__SPH_DIS_MASK 0x00000001L 479 #define UVD_LMI_CTRL2__STALL_ARB_MASK 0x00000002L 480 #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L 481 #define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x00000008L 482 #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x00000080L 483 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L 484 #define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x00000600L 485 #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x00001800L 486 //UVD_MASTINT_EN 487 #define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 488 #define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1 489 #define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2 490 #define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 491 #define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L 492 #define UVD_MASTINT_EN__VCPU_EN_MASK 0x00000002L 493 #define UVD_MASTINT_EN__SYS_EN_MASK 0x00000004L 494 #define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L 495 //JPEG_CGC_CTRL 496 #define JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 497 #define JPEG_CGC_CTRL__JPEG2_MODE__SHIFT 0x1 498 #define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 499 #define JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 500 #define JPEG_CGC_CTRL__JPEG_MODE__SHIFT 0x1f 501 #define JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L 502 #define JPEG_CGC_CTRL__JPEG2_MODE_MASK 0x00000002L 503 #define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL 504 #define JPEG_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L 505 #define JPEG_CGC_CTRL__JPEG_MODE_MASK 0x80000000L 506 //UVD_LMI_CTRL 507 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 508 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8 509 #define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9 510 #define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb 511 #define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc 512 #define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd 513 #define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe 514 #define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf 515 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 516 #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16 517 #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17 518 #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18 519 #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19 520 #define UVD_LMI_CTRL__RFU__SHIFT 0x1b 521 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0x000000FFL 522 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L 523 #define UVD_LMI_CTRL__REQ_MODE_MASK 0x00000200L 524 #define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000800L 525 #define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x00001000L 526 #define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x00002000L 527 #define UVD_LMI_CTRL__CRC_RESET_MASK 0x00004000L 528 #define UVD_LMI_CTRL__CRC_SEL_MASK 0x000F8000L 529 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L 530 #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x00400000L 531 #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x00800000L 532 #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x01000000L 533 #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x02000000L 534 #define UVD_LMI_CTRL__RFU_MASK 0xF8000000L 535 //UVD_LMI_SWAP_CNTL 536 #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 537 #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 538 #define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4 539 #define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6 540 #define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8 541 #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa 542 #define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc 543 #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe 544 #define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10 545 #define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12 546 #define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT 0x16 547 #define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18 548 #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a 549 #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c 550 #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e 551 #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 552 #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 553 #define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x00000030L 554 #define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0x000000C0L 555 #define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x00000300L 556 #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK 0x00000C00L 557 #define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK 0x00003000L 558 #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK 0x0000C000L 559 #define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x00030000L 560 #define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK 0x000C0000L 561 #define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK 0x00C00000L 562 #define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK 0x03000000L 563 #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0x0C000000L 564 #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000L 565 #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xC0000000L 566 //UVD_MP_SWAP_CNTL 567 #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0 568 #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2 569 #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4 570 #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6 571 #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8 572 #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa 573 #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc 574 #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe 575 #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10 576 #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12 577 #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14 578 #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16 579 #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18 580 #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a 581 #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c 582 #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e 583 #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x00000003L 584 #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0x0000000CL 585 #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x00000030L 586 #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0x000000C0L 587 #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x00000300L 588 #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0x00000C00L 589 #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x00003000L 590 #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0x0000C000L 591 #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x00030000L 592 #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0x000C0000L 593 #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x00300000L 594 #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0x00C00000L 595 #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x03000000L 596 #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0x0C000000L 597 #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000L 598 #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xC0000000L 599 //UVD_MPC_SET_MUXA0 600 #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 601 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 602 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc 603 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 604 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 605 #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x0000003FL 606 #define UVD_MPC_SET_MUXA0__VARA_1_MASK 0x00000FC0L 607 #define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x0003F000L 608 #define UVD_MPC_SET_MUXA0__VARA_3_MASK 0x00FC0000L 609 #define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3F000000L 610 //UVD_MPC_SET_MUXA1 611 #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0 612 #define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6 613 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc 614 #define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x0000003FL 615 #define UVD_MPC_SET_MUXA1__VARA_6_MASK 0x00000FC0L 616 #define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x0003F000L 617 //UVD_MPC_SET_MUXB0 618 #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 619 #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6 620 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc 621 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 622 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 623 #define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x0000003FL 624 #define UVD_MPC_SET_MUXB0__VARB_1_MASK 0x00000FC0L 625 #define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x0003F000L 626 #define UVD_MPC_SET_MUXB0__VARB_3_MASK 0x00FC0000L 627 #define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3F000000L 628 //UVD_MPC_SET_MUXB1 629 #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0 630 #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 631 #define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc 632 #define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x0000003FL 633 #define UVD_MPC_SET_MUXB1__VARB_6_MASK 0x00000FC0L 634 #define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x0003F000L 635 //UVD_MPC_SET_MUX 636 #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 637 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 638 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 639 #define UVD_MPC_SET_MUX__SET_0_MASK 0x00000007L 640 #define UVD_MPC_SET_MUX__SET_1_MASK 0x00000038L 641 #define UVD_MPC_SET_MUX__SET_2_MASK 0x000001C0L 642 //UVD_MPC_SET_ALU 643 #define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0 644 #define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4 645 #define UVD_MPC_SET_ALU__FUNCT_MASK 0x00000007L 646 #define UVD_MPC_SET_ALU__OPERAND_MASK 0x00000FF0L 647 //UVD_VCPU_CACHE_OFFSET0 648 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 649 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x01FFFFFFL 650 //UVD_VCPU_CACHE_SIZE0 651 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0 652 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x001FFFFFL 653 //UVD_VCPU_CACHE_OFFSET1 654 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 655 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x01FFFFFFL 656 //UVD_VCPU_CACHE_SIZE1 657 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0 658 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x001FFFFFL 659 //UVD_VCPU_CACHE_OFFSET2 660 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 661 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x01FFFFFFL 662 //UVD_VCPU_CACHE_SIZE2 663 #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0 664 #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x001FFFFFL 665 //UVD_VCPU_CNTL 666 #define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9 667 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L 668 //UVD_SOFT_RESET 669 #define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0 670 #define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1 671 #define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2 672 #define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3 673 #define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4 674 #define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT 0x5 675 #define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6 676 #define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7 677 #define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8 678 #define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa 679 #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd 680 #define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe 681 #define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf 682 #define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10 683 #define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11 684 #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12 685 #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13 686 #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14 687 #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15 688 #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16 689 #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a 690 #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b 691 #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c 692 #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d 693 #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e 694 #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f 695 #define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x00000001L 696 #define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x00000002L 697 #define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x00000004L 698 #define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x00000008L 699 #define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x00000010L 700 #define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK 0x00000020L 701 #define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x00000040L 702 #define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000080L 703 #define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x00000100L 704 #define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x00000400L 705 #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x00002000L 706 #define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x00004000L 707 #define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x00008000L 708 #define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x00010000L 709 #define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x00020000L 710 #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x00040000L 711 #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x00080000L 712 #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x00100000L 713 #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x00200000L 714 #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x00400000L 715 #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x04000000L 716 #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x08000000L 717 #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000L 718 #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000L 719 #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000L 720 #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000L 721 //UVD_LMI_RBC_IB_VMID 722 #define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0 723 #define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0x0000000FL 724 //UVD_RBC_IB_SIZE 725 #define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4 726 #define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 727 //UVD_RBC_RB_RPTR 728 #define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4 729 #define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 730 //UVD_RBC_RB_WPTR 731 #define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4 732 #define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 733 //UVD_RBC_RB_WPTR_CNTL 734 #define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x0 735 #define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK 0x00007FFFL 736 //UVD_RBC_RB_CNTL 737 #define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0 738 #define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8 739 #define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10 740 #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14 741 #define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18 742 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c 743 #define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x0000001FL 744 #define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x00001F00L 745 #define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x00010000L 746 #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x00100000L 747 #define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x01000000L 748 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000L 749 //UVD_RBC_RB_RPTR_ADDR 750 #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0 751 #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFFL 752 //UVD_STATUS 753 #define UVD_STATUS__RBC_BUSY__SHIFT 0x0 754 #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 755 #define UVD_STATUS__AVP_BUSY__SHIFT 0x8 756 #define UVD_STATUS__IDCT_BUSY__SHIFT 0x9 757 #define UVD_STATUS__IDCT_CTL_ACK__SHIFT 0xb 758 #define UVD_STATUS__UVD_CTL_ACK__SHIFT 0xc 759 #define UVD_STATUS__AVP_BLOCK_ACK__SHIFT 0xd 760 #define UVD_STATUS__IDCT_BLOCK_ACK__SHIFT 0xe 761 #define UVD_STATUS__UVD_BLOCK_ACK__SHIFT 0xf 762 #define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT 0x10 763 #define UVD_STATUS__SYS_GPCOM_REQ__SHIFT 0x1f 764 #define UVD_STATUS__RBC_BUSY_MASK 0x00000001L 765 #define UVD_STATUS__VCPU_REPORT_MASK 0x000000FEL 766 #define UVD_STATUS__AVP_BUSY_MASK 0x00000100L 767 #define UVD_STATUS__IDCT_BUSY_MASK 0x00000200L 768 #define UVD_STATUS__IDCT_CTL_ACK_MASK 0x00000800L 769 #define UVD_STATUS__UVD_CTL_ACK_MASK 0x00001000L 770 #define UVD_STATUS__AVP_BLOCK_ACK_MASK 0x00002000L 771 #define UVD_STATUS__IDCT_BLOCK_ACK_MASK 0x00004000L 772 #define UVD_STATUS__UVD_BLOCK_ACK_MASK 0x00008000L 773 #define UVD_STATUS__RBC_ACCESS_GPCOM_MASK 0x00010000L 774 #define UVD_STATUS__SYS_GPCOM_REQ_MASK 0x80000000L 775 //UVD_SEMA_TIMEOUT_STATUS 776 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0 777 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1 778 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2 779 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3 780 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000001L 781 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x00000002L 782 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000004L 783 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x00000008L 784 //UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 785 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0 786 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1 787 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 788 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x00000001L 789 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x001FFFFEL 790 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L 791 //UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 792 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0 793 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1 794 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 795 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x00000001L 796 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x001FFFFEL 797 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L 798 //UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 799 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0 800 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1 801 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 802 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x00000001L 803 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x001FFFFEL 804 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L 805 //UVD_CONTEXT_ID 806 #define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0 807 #define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xFFFFFFFFL 808 //UVD_CONTEXT_ID2 809 #define UVD_CONTEXT_ID2__CONTEXT_ID2__SHIFT 0x0 810 #define UVD_CONTEXT_ID2__CONTEXT_ID2_MASK 0xFFFFFFFFL 811 812 813 #endif 814