1 /* $NetBSD: uvd_6_0_sh_mask.h,v 1.3 2021/12/18 23:45:24 riastradh Exp $ */ 2 3 /* 4 * UVD_6_0 Register documentation 5 * 6 * Copyright (C) 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included 16 * in all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 22 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26 #ifndef UVD_6_0_SH_MASK_H 27 #define UVD_6_0_SH_MASK_H 28 29 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff 30 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0 31 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff 32 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0 33 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf 34 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0 35 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30 36 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 37 #define UVD_SEMA_CMD__MODE_MASK 0x40 38 #define UVD_SEMA_CMD__MODE__SHIFT 0x6 39 #define UVD_SEMA_CMD__VMID_EN_MASK 0x80 40 #define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7 41 #define UVD_SEMA_CMD__VMID_MASK 0xf00 42 #define UVD_SEMA_CMD__VMID__SHIFT 0x8 43 #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x1 44 #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0 45 #define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7ffffffe 46 #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 47 #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000 48 #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f 49 #define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xffffffff 50 #define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 51 #define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xffffffff 52 #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 53 #define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x1 54 #define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0 55 #define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x2 56 #define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1 57 #define UVD_UDEC_ADDR_CONFIG__NUM_PIPES_MASK 0x7 58 #define UVD_UDEC_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 59 #define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 60 #define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 61 #define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 62 #define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 63 #define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 64 #define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 65 #define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 66 #define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 67 #define UVD_UDEC_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 68 #define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 69 #define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 70 #define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 71 #define UVD_UDEC_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 72 #define UVD_UDEC_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 73 #define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 74 #define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 75 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES_MASK 0x7 76 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 77 #define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 78 #define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 79 #define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 80 #define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 81 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 82 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 83 #define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 84 #define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 85 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 86 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 87 #define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 88 #define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 89 #define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 90 #define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 91 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 92 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 93 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x7 94 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 95 #define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 96 #define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 97 #define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 98 #define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 99 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 100 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 101 #define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 102 #define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 103 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 104 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 105 #define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 106 #define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 107 #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 108 #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 109 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 110 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 111 #define UVD_POWER_STATUS_U__UVD_POWER_STATUS_MASK 0x3 112 #define UVD_POWER_STATUS_U__UVD_POWER_STATUS__SHIFT 0x0 113 #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff 114 #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 115 #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff 116 #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 117 #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff 118 #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 119 #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff 120 #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 121 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff 122 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 123 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff 124 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 125 #define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x1 126 #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0 127 #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x2 128 #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1 129 #define UVD_LMI_EXT40_ADDR__ADDR_MASK 0xff 130 #define UVD_LMI_EXT40_ADDR__ADDR__SHIFT 0x0 131 #define UVD_LMI_EXT40_ADDR__INDEX_MASK 0x1f0000 132 #define UVD_LMI_EXT40_ADDR__INDEX__SHIFT 0x10 133 #define UVD_LMI_EXT40_ADDR__WRITE_ADDR_MASK 0x80000000 134 #define UVD_LMI_EXT40_ADDR__WRITE_ADDR__SHIFT 0x1f 135 #define UVD_CTX_INDEX__INDEX_MASK 0x1ff 136 #define UVD_CTX_INDEX__INDEX__SHIFT 0x0 137 #define UVD_CTX_DATA__DATA_MASK 0xffffffff 138 #define UVD_CTX_DATA__DATA__SHIFT 0x0 139 #define UVD_CGC_GATE__SYS_MASK 0x1 140 #define UVD_CGC_GATE__SYS__SHIFT 0x0 141 #define UVD_CGC_GATE__UDEC_MASK 0x2 142 #define UVD_CGC_GATE__UDEC__SHIFT 0x1 143 #define UVD_CGC_GATE__MPEG2_MASK 0x4 144 #define UVD_CGC_GATE__MPEG2__SHIFT 0x2 145 #define UVD_CGC_GATE__REGS_MASK 0x8 146 #define UVD_CGC_GATE__REGS__SHIFT 0x3 147 #define UVD_CGC_GATE__RBC_MASK 0x10 148 #define UVD_CGC_GATE__RBC__SHIFT 0x4 149 #define UVD_CGC_GATE__LMI_MC_MASK 0x20 150 #define UVD_CGC_GATE__LMI_MC__SHIFT 0x5 151 #define UVD_CGC_GATE__LMI_UMC_MASK 0x40 152 #define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6 153 #define UVD_CGC_GATE__IDCT_MASK 0x80 154 #define UVD_CGC_GATE__IDCT__SHIFT 0x7 155 #define UVD_CGC_GATE__MPRD_MASK 0x100 156 #define UVD_CGC_GATE__MPRD__SHIFT 0x8 157 #define UVD_CGC_GATE__MPC_MASK 0x200 158 #define UVD_CGC_GATE__MPC__SHIFT 0x9 159 #define UVD_CGC_GATE__LBSI_MASK 0x400 160 #define UVD_CGC_GATE__LBSI__SHIFT 0xa 161 #define UVD_CGC_GATE__LRBBM_MASK 0x800 162 #define UVD_CGC_GATE__LRBBM__SHIFT 0xb 163 #define UVD_CGC_GATE__UDEC_RE_MASK 0x1000 164 #define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc 165 #define UVD_CGC_GATE__UDEC_CM_MASK 0x2000 166 #define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd 167 #define UVD_CGC_GATE__UDEC_IT_MASK 0x4000 168 #define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe 169 #define UVD_CGC_GATE__UDEC_DB_MASK 0x8000 170 #define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf 171 #define UVD_CGC_GATE__UDEC_MP_MASK 0x10000 172 #define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10 173 #define UVD_CGC_GATE__WCB_MASK 0x20000 174 #define UVD_CGC_GATE__WCB__SHIFT 0x11 175 #define UVD_CGC_GATE__VCPU_MASK 0x40000 176 #define UVD_CGC_GATE__VCPU__SHIFT 0x12 177 #define UVD_CGC_GATE__SCPU_MASK 0x80000 178 #define UVD_CGC_GATE__SCPU__SHIFT 0x13 179 #define UVD_CGC_GATE__JPEG_MASK 0x100000 180 #define UVD_CGC_GATE__JPEG__SHIFT 0x14 181 #define UVD_CGC_GATE__JPEG2_MASK 0x200000 182 #define UVD_CGC_GATE__JPEG2__SHIFT 0x15 183 #define UVD_CGC_STATUS__SYS_SCLK_MASK 0x1 184 #define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0 185 #define UVD_CGC_STATUS__SYS_DCLK_MASK 0x2 186 #define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1 187 #define UVD_CGC_STATUS__SYS_VCLK_MASK 0x4 188 #define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2 189 #define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x8 190 #define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3 191 #define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x10 192 #define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4 193 #define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x20 194 #define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5 195 #define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x40 196 #define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6 197 #define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x80 198 #define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7 199 #define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x100 200 #define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8 201 #define UVD_CGC_STATUS__REGS_SCLK_MASK 0x200 202 #define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9 203 #define UVD_CGC_STATUS__REGS_VCLK_MASK 0x400 204 #define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa 205 #define UVD_CGC_STATUS__RBC_SCLK_MASK 0x800 206 #define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb 207 #define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x1000 208 #define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc 209 #define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x2000 210 #define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd 211 #define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x4000 212 #define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe 213 #define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x8000 214 #define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf 215 #define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x10000 216 #define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10 217 #define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x20000 218 #define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11 219 #define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x40000 220 #define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12 221 #define UVD_CGC_STATUS__MPC_SCLK_MASK 0x80000 222 #define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13 223 #define UVD_CGC_STATUS__MPC_DCLK_MASK 0x100000 224 #define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14 225 #define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x200000 226 #define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15 227 #define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x400000 228 #define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16 229 #define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x800000 230 #define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17 231 #define UVD_CGC_STATUS__WCB_SCLK_MASK 0x1000000 232 #define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18 233 #define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x2000000 234 #define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19 235 #define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x4000000 236 #define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a 237 #define UVD_CGC_STATUS__SCPU_SCLK_MASK 0x8000000 238 #define UVD_CGC_STATUS__SCPU_SCLK__SHIFT 0x1b 239 #define UVD_CGC_STATUS__SCPU_VCLK_MASK 0x10000000 240 #define UVD_CGC_STATUS__SCPU_VCLK__SHIFT 0x1c 241 #define UVD_CGC_STATUS__JPEG_ACTIVE_MASK 0x40000000 242 #define UVD_CGC_STATUS__JPEG_ACTIVE__SHIFT 0x1e 243 #define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK 0x80000000 244 #define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT 0x1f 245 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1 246 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 247 #define UVD_CGC_CTRL__JPEG2_MODE_MASK 0x2 248 #define UVD_CGC_CTRL__JPEG2_MODE__SHIFT 0x1 249 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x3c 250 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 251 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x7c0 252 #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 253 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800 254 #define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb 255 #define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x1000 256 #define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc 257 #define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x2000 258 #define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd 259 #define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x4000 260 #define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe 261 #define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x8000 262 #define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf 263 #define UVD_CGC_CTRL__SYS_MODE_MASK 0x10000 264 #define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10 265 #define UVD_CGC_CTRL__UDEC_MODE_MASK 0x20000 266 #define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11 267 #define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x40000 268 #define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12 269 #define UVD_CGC_CTRL__REGS_MODE_MASK 0x80000 270 #define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13 271 #define UVD_CGC_CTRL__RBC_MODE_MASK 0x100000 272 #define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14 273 #define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x200000 274 #define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15 275 #define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x400000 276 #define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16 277 #define UVD_CGC_CTRL__IDCT_MODE_MASK 0x800000 278 #define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17 279 #define UVD_CGC_CTRL__MPRD_MODE_MASK 0x1000000 280 #define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18 281 #define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000 282 #define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19 283 #define UVD_CGC_CTRL__LBSI_MODE_MASK 0x4000000 284 #define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a 285 #define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x8000000 286 #define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b 287 #define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000 288 #define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c 289 #define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000 290 #define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d 291 #define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000 292 #define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e 293 #define UVD_CGC_CTRL__JPEG_MODE_MASK 0x80000000 294 #define UVD_CGC_CTRL__JPEG_MODE__SHIFT 0x1f 295 #define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x1 296 #define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0 297 #define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x2 298 #define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1 299 #define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x4 300 #define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2 301 #define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x8 302 #define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3 303 #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x10 304 #define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4 305 #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x20 306 #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 307 #define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x40 308 #define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6 309 #define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x80 310 #define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7 311 #define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x100 312 #define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8 313 #define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x200 314 #define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9 315 #define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x400 316 #define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa 317 #define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x800 318 #define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb 319 #define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x1000 320 #define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc 321 #define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x2000 322 #define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd 323 #define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x4000 324 #define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe 325 #define UVD_CGC_UDEC_STATUS__JPEG_VCLK_MASK 0x8000 326 #define UVD_CGC_UDEC_STATUS__JPEG_VCLK__SHIFT 0xf 327 #define UVD_CGC_UDEC_STATUS__JPEG_SCLK_MASK 0x10000 328 #define UVD_CGC_UDEC_STATUS__JPEG_SCLK__SHIFT 0x10 329 #define UVD_CGC_UDEC_STATUS__JPEG2_VCLK_MASK 0x20000 330 #define UVD_CGC_UDEC_STATUS__JPEG2_VCLK__SHIFT 0x11 331 #define UVD_CGC_UDEC_STATUS__JPEG2_SCLK_MASK 0x40000 332 #define UVD_CGC_UDEC_STATUS__JPEG2_SCLK__SHIFT 0x12 333 #define UVD_LMI_CTRL2__SPH_DIS_MASK 0x1 334 #define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0 335 #define UVD_LMI_CTRL2__STALL_ARB_MASK 0x2 336 #define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1 337 #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x4 338 #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2 339 #define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x8 340 #define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3 341 #define UVD_LMI_CTRL2__MCIF_WR_WATERMARK_MASK 0x70 342 #define UVD_LMI_CTRL2__MCIF_WR_WATERMARK__SHIFT 0x4 343 #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x80 344 #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7 345 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100 346 #define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 347 #define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x600 348 #define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 349 #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x1800 350 #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb 351 #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x2000 352 #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd 353 #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x4000 354 #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe 355 #define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x8000 356 #define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf 357 #define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x10000 358 #define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10 359 #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x1fe0000 360 #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11 361 #define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x1 362 #define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 363 #define UVD_MASTINT_EN__VCPU_EN_MASK 0x2 364 #define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1 365 #define UVD_MASTINT_EN__SYS_EN_MASK 0x4 366 #define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2 367 #define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x7ffff0 368 #define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 369 #define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT_MASK 0xf 370 #define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT__SHIFT 0x0 371 #define UVD_LMI_ADDR_EXT__CM_ADDR_EXT_MASK 0xf0 372 #define UVD_LMI_ADDR_EXT__CM_ADDR_EXT__SHIFT 0x4 373 #define UVD_LMI_ADDR_EXT__IT_ADDR_EXT_MASK 0xf00 374 #define UVD_LMI_ADDR_EXT__IT_ADDR_EXT__SHIFT 0x8 375 #define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT_MASK 0xf000 376 #define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT__SHIFT 0xc 377 #define UVD_LMI_ADDR_EXT__RE_ADDR_EXT_MASK 0xf0000 378 #define UVD_LMI_ADDR_EXT__RE_ADDR_EXT__SHIFT 0x10 379 #define UVD_LMI_ADDR_EXT__MP_ADDR_EXT_MASK 0xf00000 380 #define UVD_LMI_ADDR_EXT__MP_ADDR_EXT__SHIFT 0x14 381 #define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT_MASK 0xf000000 382 #define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT__SHIFT 0x18 383 #define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT_MASK 0xf0000000 384 #define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT__SHIFT 0x1c 385 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0xff 386 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 387 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x100 388 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8 389 #define UVD_LMI_CTRL__REQ_MODE_MASK 0x200 390 #define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9 391 #define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x800 392 #define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb 393 #define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x1000 394 #define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc 395 #define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x2000 396 #define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd 397 #define UVD_LMI_CTRL__CRC_RESET_MASK 0x4000 398 #define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe 399 #define UVD_LMI_CTRL__CRC_SEL_MASK 0xf8000 400 #define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf 401 #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x100000 402 #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x14 403 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x200000 404 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 405 #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x400000 406 #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16 407 #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x800000 408 #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17 409 #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x1000000 410 #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18 411 #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x2000000 412 #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19 413 #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x4000000 414 #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a 415 #define UVD_LMI_CTRL__RFU_MASK 0xf8000000 416 #define UVD_LMI_CTRL__RFU__SHIFT 0x1b 417 #define UVD_LMI_STATUS__READ_CLEAN_MASK 0x1 418 #define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0 419 #define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x2 420 #define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1 421 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x4 422 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2 423 #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x8 424 #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3 425 #define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x10 426 #define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4 427 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x20 428 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5 429 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x40 430 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6 431 #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x80 432 #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7 433 #define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x100 434 #define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8 435 #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x200 436 #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9 437 #define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x400 438 #define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa 439 #define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x800 440 #define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb 441 #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x1000 442 #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc 443 #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x2000 444 #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd 445 #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x3 446 #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 447 #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0xc 448 #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 449 #define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x30 450 #define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4 451 #define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0xc0 452 #define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6 453 #define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x300 454 #define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8 455 #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK 0xc00 456 #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa 457 #define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK 0x3000 458 #define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc 459 #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK 0xc000 460 #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe 461 #define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x30000 462 #define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10 463 #define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK 0xc0000 464 #define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12 465 #define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK 0xc00000 466 #define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT 0x16 467 #define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK 0x3000000 468 #define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18 469 #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0xc000000 470 #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a 471 #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000 472 #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c 473 #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xc0000000 474 #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e 475 #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x3 476 #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0 477 #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0xc 478 #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2 479 #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x30 480 #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4 481 #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0xc0 482 #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6 483 #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x300 484 #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8 485 #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0xc00 486 #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa 487 #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x3000 488 #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc 489 #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0xc000 490 #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe 491 #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x30000 492 #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10 493 #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0xc0000 494 #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12 495 #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x300000 496 #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14 497 #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0xc00000 498 #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16 499 #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x3000000 500 #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18 501 #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0xc000000 502 #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a 503 #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000 504 #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c 505 #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xc0000000 506 #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e 507 #define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x38 508 #define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3 509 #define UVD_MPC_CNTL__PERF_RST_MASK 0x40 510 #define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6 511 #define UVD_MPC_CNTL__DBG_MUX_MASK 0xf00 512 #define UVD_MPC_CNTL__DBG_MUX__SHIFT 0x8 513 #define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x30000 514 #define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10 515 #define UVD_MPC_CNTL__URGENT_EN_MASK 0x40000 516 #define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12 517 #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x3f 518 #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 519 #define UVD_MPC_SET_MUXA0__VARA_1_MASK 0xfc0 520 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 521 #define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x3f000 522 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc 523 #define UVD_MPC_SET_MUXA0__VARA_3_MASK 0xfc0000 524 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 525 #define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3f000000 526 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 527 #define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x3f 528 #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0 529 #define UVD_MPC_SET_MUXA1__VARA_6_MASK 0xfc0 530 #define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6 531 #define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x3f000 532 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc 533 #define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x3f 534 #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 535 #define UVD_MPC_SET_MUXB0__VARB_1_MASK 0xfc0 536 #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6 537 #define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x3f000 538 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc 539 #define UVD_MPC_SET_MUXB0__VARB_3_MASK 0xfc0000 540 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 541 #define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3f000000 542 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 543 #define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x3f 544 #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0 545 #define UVD_MPC_SET_MUXB1__VARB_6_MASK 0xfc0 546 #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 547 #define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x3f000 548 #define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc 549 #define UVD_MPC_SET_MUX__SET_0_MASK 0x7 550 #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 551 #define UVD_MPC_SET_MUX__SET_1_MASK 0x38 552 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 553 #define UVD_MPC_SET_MUX__SET_2_MASK 0x1c0 554 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 555 #define UVD_MPC_SET_ALU__FUNCT_MASK 0x7 556 #define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0 557 #define UVD_MPC_SET_ALU__OPERAND_MASK 0xff0 558 #define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4 559 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x1ffffff 560 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 561 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x1fffff 562 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0 563 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x1ffffff 564 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 565 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x1fffff 566 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0 567 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x1ffffff 568 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 569 #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x1fffff 570 #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0 571 #define UVD_VCPU_CNTL__IRQ_ERR_MASK 0xf 572 #define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0 573 #define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4_MASK 0x10 574 #define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4__SHIFT 0x4 575 #define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x20 576 #define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5 577 #define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x40 578 #define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6 579 #define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x80 580 #define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7 581 #define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x100 582 #define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8 583 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200 584 #define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9 585 #define UVD_VCPU_CNTL__TRCE_EN_MASK 0x400 586 #define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa 587 #define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x1800 588 #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb 589 #define UVD_VCPU_CNTL__DBG_MUX_MASK 0xe000 590 #define UVD_VCPU_CNTL__DBG_MUX__SHIFT 0xd 591 #define UVD_VCPU_CNTL__JTAG_EN_MASK 0x10000 592 #define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10 593 #define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK 0x20000 594 #define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP__SHIFT 0x11 595 #define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x40000 596 #define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12 597 #define UVD_VCPU_CNTL__SUVD_EN_MASK 0x80000 598 #define UVD_VCPU_CNTL__SUVD_EN__SHIFT 0x13 599 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0xff00000 600 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 601 #define UVD_VCPU_CNTL__CABAC_MB_ACC_MASK 0x10000000 602 #define UVD_VCPU_CNTL__CABAC_MB_ACC__SHIFT 0x1c 603 #define UVD_VCPU_CNTL__WMV9_EN_MASK 0x40000000 604 #define UVD_VCPU_CNTL__WMV9_EN__SHIFT 0x1e 605 #define UVD_VCPU_CNTL__RE_OFFLOAD_EN_MASK 0x80000000 606 #define UVD_VCPU_CNTL__RE_OFFLOAD_EN__SHIFT 0x1f 607 #define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x1 608 #define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0 609 #define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x2 610 #define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1 611 #define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x4 612 #define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2 613 #define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x8 614 #define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3 615 #define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x10 616 #define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4 617 #define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK 0x20 618 #define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT 0x5 619 #define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x40 620 #define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6 621 #define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x80 622 #define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7 623 #define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x100 624 #define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8 625 #define UVD_SOFT_RESET__JPEG_SCLK_RESET_STATUS_MASK 0x200 626 #define UVD_SOFT_RESET__JPEG_SCLK_RESET_STATUS__SHIFT 0x9 627 #define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x400 628 #define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa 629 #define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x800 630 #define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb 631 #define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x1000 632 #define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc 633 #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x2000 634 #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd 635 #define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x4000 636 #define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe 637 #define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x8000 638 #define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf 639 #define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x10000 640 #define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10 641 #define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x20000 642 #define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11 643 #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x40000 644 #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12 645 #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x80000 646 #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13 647 #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x100000 648 #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14 649 #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x200000 650 #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15 651 #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x400000 652 #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16 653 #define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS_MASK 0x800000 654 #define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS__SHIFT 0x17 655 #define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS_MASK 0x1000000 656 #define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS__SHIFT 0x18 657 #define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS_MASK 0x2000000 658 #define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS__SHIFT 0x19 659 #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x4000000 660 #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a 661 #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x8000000 662 #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b 663 #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000 664 #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c 665 #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000 666 #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d 667 #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000 668 #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e 669 #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000 670 #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f 671 #define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0xf 672 #define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0 673 #define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x7ffff0 674 #define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4 675 #define UVD_LMI_RBC_RB_VMID__RB_VMID_MASK 0xf 676 #define UVD_LMI_RBC_RB_VMID__RB_VMID__SHIFT 0x0 677 #define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x7ffff0 678 #define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4 679 #define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x7ffff0 680 #define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4 681 #define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x1f 682 #define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0 683 #define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x1f00 684 #define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8 685 #define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x10000 686 #define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10 687 #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x100000 688 #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14 689 #define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x1000000 690 #define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18 691 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000 692 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c 693 #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xffffffff 694 #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0 695 #define UVD_STATUS__RBC_BUSY_MASK 0x1 696 #define UVD_STATUS__RBC_BUSY__SHIFT 0x0 697 #define UVD_STATUS__VCPU_REPORT_MASK 0xfe 698 #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 699 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x1 700 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0 701 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x2 702 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1 703 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x4 704 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2 705 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x8 706 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3 707 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x1 708 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0 709 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x1ffffe 710 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1 711 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 712 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 713 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x1 714 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0 715 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x1ffffe 716 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1 717 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 718 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 719 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x1 720 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0 721 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x1ffffe 722 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1 723 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 724 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 725 #define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xffffffff 726 #define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0 727 #define UVD_SUVD_CGC_GATE__SRE_MASK 0x1 728 #define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0 729 #define UVD_SUVD_CGC_GATE__SIT_MASK 0x2 730 #define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1 731 #define UVD_SUVD_CGC_GATE__SMP_MASK 0x4 732 #define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2 733 #define UVD_SUVD_CGC_GATE__SCM_MASK 0x8 734 #define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3 735 #define UVD_SUVD_CGC_GATE__SDB_MASK 0x10 736 #define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4 737 #define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x20 738 #define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 739 #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x40 740 #define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 741 #define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x80 742 #define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 743 #define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x100 744 #define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 745 #define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x200 746 #define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 747 #define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x400 748 #define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 749 #define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x800 750 #define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 751 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x1000 752 #define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 753 #define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 0x1 754 #define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT 0x0 755 #define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x2 756 #define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT 0x1 757 #define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 0x4 758 #define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT 0x2 759 #define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x8 760 #define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3 761 #define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x10 762 #define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT 0x4 763 #define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x20 764 #define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5 765 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x40 766 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6 767 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x80 768 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT 0x7 769 #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x100 770 #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT 0x8 771 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x200 772 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 0x9 773 #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK 0x400 774 #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa 775 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x800 776 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb 777 #define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK 0x1000 778 #define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT 0xc 779 #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 0x2000 780 #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 0xd 781 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x1 782 #define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 783 #define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x2 784 #define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 785 #define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x4 786 #define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 787 #define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x8 788 #define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 789 #define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x10 790 #define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 791 #define UVD_LMI_VMID_INTERNAL__VCPU_NC0_VMID_MASK 0xf 792 #define UVD_LMI_VMID_INTERNAL__VCPU_NC0_VMID__SHIFT 0x0 793 #define UVD_LMI_VMID_INTERNAL__VCPU_NC1_VMID_MASK 0xf0 794 #define UVD_LMI_VMID_INTERNAL__VCPU_NC1_VMID__SHIFT 0x4 795 #define UVD_LMI_VMID_INTERNAL__DPB_VMID_MASK 0xf00 796 #define UVD_LMI_VMID_INTERNAL__DPB_VMID__SHIFT 0x8 797 #define UVD_LMI_VMID_INTERNAL__DBW_VMID_MASK 0xf000 798 #define UVD_LMI_VMID_INTERNAL__DBW_VMID__SHIFT 0xc 799 #define UVD_LMI_VMID_INTERNAL__LBSI_VMID_MASK 0xf0000 800 #define UVD_LMI_VMID_INTERNAL__LBSI_VMID__SHIFT 0x10 801 #define UVD_LMI_VMID_INTERNAL__IDCT_VMID_MASK 0xf00000 802 #define UVD_LMI_VMID_INTERNAL__IDCT_VMID__SHIFT 0x14 803 #define UVD_LMI_VMID_INTERNAL__JPEG_VMID_MASK 0xf000000 804 #define UVD_LMI_VMID_INTERNAL__JPEG_VMID__SHIFT 0x18 805 #define UVD_LMI_VMID_INTERNAL__JPEG2_VMID_MASK 0xf0000000 806 #define UVD_LMI_VMID_INTERNAL__JPEG2_VMID__SHIFT 0x1c 807 #define UVD_LMI_VMID_INTERNAL2__MIF_GPGPU_VMID_MASK 0xf 808 #define UVD_LMI_VMID_INTERNAL2__MIF_GPGPU_VMID__SHIFT 0x0 809 #define UVD_LMI_VMID_INTERNAL2__MIF_CURR_VMID_MASK 0xf0 810 #define UVD_LMI_VMID_INTERNAL2__MIF_CURR_VMID__SHIFT 0x4 811 #define UVD_LMI_VMID_INTERNAL2__MIF_REF_VMID_MASK 0xf00 812 #define UVD_LMI_VMID_INTERNAL2__MIF_REF_VMID__SHIFT 0x8 813 #define UVD_LMI_VMID_INTERNAL2__MIF_DBW_VMID_MASK 0xf000 814 #define UVD_LMI_VMID_INTERNAL2__MIF_DBW_VMID__SHIFT 0xc 815 #define UVD_LMI_VMID_INTERNAL2__MIF_CM_COLOC_VMID_MASK 0xf0000 816 #define UVD_LMI_VMID_INTERNAL2__MIF_CM_COLOC_VMID__SHIFT 0x10 817 #define UVD_LMI_VMID_INTERNAL2__MIF_BSD_VMID_MASK 0xf00000 818 #define UVD_LMI_VMID_INTERNAL2__MIF_BSD_VMID__SHIFT 0x14 819 #define UVD_LMI_VMID_INTERNAL2__MIF_BSP_VMID_MASK 0xf000000 820 #define UVD_LMI_VMID_INTERNAL2__MIF_BSP_VMID__SHIFT 0x18 821 #define UVD_LMI_VMID_INTERNAL2__VDMA_VMID_MASK 0xf0000000 822 #define UVD_LMI_VMID_INTERNAL2__VDMA_VMID__SHIFT 0x1c 823 #define UVD_LMI_CACHE_CTRL__IT_EN_MASK 0x1 824 #define UVD_LMI_CACHE_CTRL__IT_EN__SHIFT 0x0 825 #define UVD_LMI_CACHE_CTRL__IT_FLUSH_MASK 0x2 826 #define UVD_LMI_CACHE_CTRL__IT_FLUSH__SHIFT 0x1 827 #define UVD_LMI_CACHE_CTRL__CM_EN_MASK 0x4 828 #define UVD_LMI_CACHE_CTRL__CM_EN__SHIFT 0x2 829 #define UVD_LMI_CACHE_CTRL__CM_FLUSH_MASK 0x8 830 #define UVD_LMI_CACHE_CTRL__CM_FLUSH__SHIFT 0x3 831 #define UVD_LMI_CACHE_CTRL__VCPU_EN_MASK 0x10 832 #define UVD_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x4 833 #define UVD_LMI_CACHE_CTRL__VCPU_FLUSH_MASK 0x20 834 #define UVD_LMI_CACHE_CTRL__VCPU_FLUSH__SHIFT 0x5 835 #define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP_MASK 0x3 836 #define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP__SHIFT 0x0 837 #define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP_MASK 0xc 838 #define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP__SHIFT 0x2 839 #define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT_MASK 0xf 840 #define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT__SHIFT 0x0 841 #define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT_MASK 0xf0 842 #define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT__SHIFT 0x4 843 #define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT_MASK 0xf00 844 #define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT__SHIFT 0x8 845 #define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT_MASK 0xf000 846 #define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT__SHIFT 0xc 847 #define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN_MASK 0x1 848 #define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN__SHIFT 0x0 849 #define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x2 850 #define UVD_CGC_MEM_CTRL__MPC_LS_EN__SHIFT 0x1 851 #define UVD_CGC_MEM_CTRL__MPRD_LS_EN_MASK 0x4 852 #define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x2 853 #define UVD_CGC_MEM_CTRL__WCB_LS_EN_MASK 0x8 854 #define UVD_CGC_MEM_CTRL__WCB_LS_EN__SHIFT 0x3 855 #define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN_MASK 0x10 856 #define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN__SHIFT 0x4 857 #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x20 858 #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x5 859 #define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN_MASK 0x40 860 #define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN__SHIFT 0x6 861 #define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x80 862 #define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN__SHIFT 0x7 863 #define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x100 864 #define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN__SHIFT 0x8 865 #define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x200 866 #define UVD_CGC_MEM_CTRL__SYS_LS_EN__SHIFT 0x9 867 #define UVD_CGC_MEM_CTRL__VCPU_LS_EN_MASK 0x400 868 #define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0xa 869 #define UVD_CGC_MEM_CTRL__SCPU_LS_EN_MASK 0x800 870 #define UVD_CGC_MEM_CTRL__SCPU_LS_EN__SHIFT 0xb 871 #define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x1000 872 #define UVD_CGC_MEM_CTRL__MIF_LS_EN__SHIFT 0xc 873 #define UVD_CGC_MEM_CTRL__LCM_LS_EN_MASK 0x2000 874 #define UVD_CGC_MEM_CTRL__LCM_LS_EN__SHIFT 0xd 875 #define UVD_CGC_MEM_CTRL__JPEG_LS_EN_MASK 0x4000 876 #define UVD_CGC_MEM_CTRL__JPEG_LS_EN__SHIFT 0xe 877 #define UVD_CGC_MEM_CTRL__JPEG2_LS_EN_MASK 0x8000 878 #define UVD_CGC_MEM_CTRL__JPEG2_LS_EN__SHIFT 0xf 879 #define UVD_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0xf0000 880 #define UVD_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10 881 #define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0xf00000 882 #define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14 883 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x1 884 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0 885 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x2 886 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1 887 #define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x1c 888 #define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2 889 #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD0_VMID_MASK 0xf 890 #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD0_VMID__SHIFT 0x0 891 #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD1_VMID_MASK 0xf0 892 #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD1_VMID__SHIFT 0x4 893 #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR0_VMID_MASK 0xf00 894 #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR0_VMID__SHIFT 0x8 895 #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR1_VMID_MASK 0xf000 896 #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR1_VMID__SHIFT 0xc 897 #define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK 0xff 898 #define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR__SHIFT 0x0 899 #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK 0x100 900 #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN__SHIFT 0x8 901 #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK 0x200 902 #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP__SHIFT 0x9 903 #define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK 0x400 904 #define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT__SHIFT 0xa 905 #define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT_MASK 0x800 906 #define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT__SHIFT 0xb 907 #define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE_MASK 0x1000 908 #define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE__SHIFT 0xc 909 #define UVD_PGFSM_CONFIG__UVD_PGFSM_READ_MASK 0x2000 910 #define UVD_PGFSM_CONFIG__UVD_PGFSM_READ__SHIFT 0xd 911 #define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR_MASK 0xf0000000 912 #define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR__SHIFT 0x1c 913 #define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE_MASK 0xffffff 914 #define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE__SHIFT 0x0 915 #define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE_MASK 0xffffff 916 #define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE__SHIFT 0x0 917 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x3 918 #define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0 919 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x4 920 #define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2 921 #define UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT_MASK 0x8 922 #define UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT__SHIFT 0x3 923 #define UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT_MASK 0x10 924 #define UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT__SHIFT 0x4 925 #define UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT_MASK 0x20 926 #define UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT__SHIFT 0x5 927 #define UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE_MASK 0xc0 928 #define UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE__SHIFT 0x6 929 #define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x100 930 #define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8 931 #define UVD_POWER_STATUS__PAUSE_DPG_REQ_MASK 0x200 932 #define UVD_POWER_STATUS__PAUSE_DPG_REQ__SHIFT 0x9 933 #define UVD_POWER_STATUS__PAUSE_DPG_ACK_MASK 0x400 934 #define UVD_POWER_STATUS__PAUSE_DPG_ACK__SHIFT 0xa 935 #define UVD_PGFSM_READ_TILE3__UVD_PGFSM_READ_TILE3_VALUE_MASK 0xffffff 936 #define UVD_PGFSM_READ_TILE3__UVD_PGFSM_READ_TILE3_VALUE__SHIFT 0x0 937 #define UVD_PGFSM_READ_TILE4__UVD_PGFSM_READ_TILE4_VALUE_MASK 0xffffff 938 #define UVD_PGFSM_READ_TILE4__UVD_PGFSM_READ_TILE4_VALUE__SHIFT 0x0 939 #define UVD_PGFSM_READ_TILE5__UVD_PGFSM_READ_TILE5_VALUE_MASK 0xffffff 940 #define UVD_PGFSM_READ_TILE5__UVD_PGFSM_READ_TILE5_VALUE__SHIFT 0x0 941 #define UVD_PGFSM_READ_TILE6__UVD_PGFSM_READ_TILE6_VALUE_MASK 0xffffff 942 #define UVD_PGFSM_READ_TILE6__UVD_PGFSM_READ_TILE6_VALUE__SHIFT 0x0 943 #define UVD_PGFSM_READ_TILE7__UVD_PGFSM_READ_TILE7_VALUE_MASK 0xffffff 944 #define UVD_PGFSM_READ_TILE7__UVD_PGFSM_READ_TILE7_VALUE__SHIFT 0x0 945 #define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES_MASK 0x7 946 #define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 947 #define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 948 #define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 949 #define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 950 #define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 951 #define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 952 #define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 953 #define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 954 #define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 955 #define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 956 #define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 957 #define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 958 #define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 959 #define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 960 #define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 961 #define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 962 #define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 963 #define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES_MASK 0x7 964 #define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 965 #define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 966 #define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 967 #define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 968 #define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 969 #define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 970 #define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 971 #define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 972 #define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 973 #define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 974 #define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 975 #define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 976 #define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 977 #define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 978 #define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 979 #define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 980 #define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 981 #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES_MASK 0x7 982 #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 983 #define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 984 #define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 985 #define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 986 #define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 987 #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 988 #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 989 #define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 990 #define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 991 #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 992 #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 993 #define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 994 #define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 995 #define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 996 #define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 997 #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 998 #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 999 #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_PIPES_MASK 0x7 1000 #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 1001 #define UVD_MIF_SCLR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 1002 #define UVD_MIF_SCLR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 1003 #define UVD_MIF_SCLR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 1004 #define UVD_MIF_SCLR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 1005 #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 1006 #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 1007 #define UVD_MIF_SCLR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 1008 #define UVD_MIF_SCLR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 1009 #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 1010 #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 1011 #define UVD_MIF_SCLR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 1012 #define UVD_MIF_SCLR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 1013 #define UVD_MIF_SCLR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 1014 #define UVD_MIF_SCLR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 1015 #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 1016 #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 1017 #define UVD_JPEG_ADDR_CONFIG__NUM_PIPES_MASK 0x7 1018 #define UVD_JPEG_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 1019 #define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 1020 #define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 1021 #define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 1022 #define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 1023 #define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 1024 #define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 1025 #define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 1026 #define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 1027 #define UVD_JPEG_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 1028 #define UVD_JPEG_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 1029 #define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 1030 #define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 1031 #define UVD_JPEG_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 1032 #define UVD_JPEG_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 1033 #define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 1034 #define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 1035 1036 #endif /* UVD_6_0_SH_MASK_H */ 1037