1 /* $NetBSD: uvd_4_2_sh_mask.h,v 1.3 2021/12/18 23:45:24 riastradh Exp $ */ 2 3 /* 4 * UVD_4_2 Register documentation 5 * 6 * Copyright (C) 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included 16 * in all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 22 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26 #ifndef UVD_4_2_SH_MASK_H 27 #define UVD_4_2_SH_MASK_H 28 29 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff 30 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0 31 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff 32 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0 33 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf 34 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0 35 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30 36 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 37 #define UVD_SEMA_CMD__MODE_MASK 0x40 38 #define UVD_SEMA_CMD__MODE__SHIFT 0x6 39 #define UVD_SEMA_CMD__VMID_EN_MASK 0x80 40 #define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7 41 #define UVD_SEMA_CMD__VMID_MASK 0xf00 42 #define UVD_SEMA_CMD__VMID__SHIFT 0x8 43 #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x1 44 #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0 45 #define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7ffffffe 46 #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 47 #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000 48 #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f 49 #define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xffffffff 50 #define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 51 #define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xffffffff 52 #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 53 #define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x1 54 #define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0 55 #define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x2 56 #define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1 57 #define UVD_UDEC_ADDR_CONFIG__NUM_PIPES_MASK 0x7 58 #define UVD_UDEC_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 59 #define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 60 #define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 61 #define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 62 #define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 63 #define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 64 #define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 65 #define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 66 #define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 67 #define UVD_UDEC_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 68 #define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 69 #define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 70 #define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 71 #define UVD_UDEC_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 72 #define UVD_UDEC_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 73 #define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 74 #define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 75 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES_MASK 0x7 76 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 77 #define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 78 #define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 79 #define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 80 #define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 81 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 82 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 83 #define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 84 #define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 85 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 86 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 87 #define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 88 #define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 89 #define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 90 #define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 91 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 92 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 93 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x7 94 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 95 #define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 96 #define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 97 #define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 98 #define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 99 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 100 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 101 #define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 102 #define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 103 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 104 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 105 #define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 106 #define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 107 #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 108 #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 109 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 110 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 111 #define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x1 112 #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0 113 #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x2 114 #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1 115 #define UVD_LMI_EXT40_ADDR__ADDR_MASK 0xff 116 #define UVD_LMI_EXT40_ADDR__ADDR__SHIFT 0x0 117 #define UVD_LMI_EXT40_ADDR__INDEX_MASK 0x1f0000 118 #define UVD_LMI_EXT40_ADDR__INDEX__SHIFT 0x10 119 #define UVD_LMI_EXT40_ADDR__WRITE_ADDR_MASK 0x80000000 120 #define UVD_LMI_EXT40_ADDR__WRITE_ADDR__SHIFT 0x1f 121 #define UVD_CTX_INDEX__INDEX_MASK 0x1ff 122 #define UVD_CTX_INDEX__INDEX__SHIFT 0x0 123 #define UVD_CTX_DATA__DATA_MASK 0xffffffff 124 #define UVD_CTX_DATA__DATA__SHIFT 0x0 125 #define UVD_CGC_GATE__SYS_MASK 0x1 126 #define UVD_CGC_GATE__SYS__SHIFT 0x0 127 #define UVD_CGC_GATE__UDEC_MASK 0x2 128 #define UVD_CGC_GATE__UDEC__SHIFT 0x1 129 #define UVD_CGC_GATE__MPEG2_MASK 0x4 130 #define UVD_CGC_GATE__MPEG2__SHIFT 0x2 131 #define UVD_CGC_GATE__REGS_MASK 0x8 132 #define UVD_CGC_GATE__REGS__SHIFT 0x3 133 #define UVD_CGC_GATE__RBC_MASK 0x10 134 #define UVD_CGC_GATE__RBC__SHIFT 0x4 135 #define UVD_CGC_GATE__LMI_MC_MASK 0x20 136 #define UVD_CGC_GATE__LMI_MC__SHIFT 0x5 137 #define UVD_CGC_GATE__LMI_UMC_MASK 0x40 138 #define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6 139 #define UVD_CGC_GATE__IDCT_MASK 0x80 140 #define UVD_CGC_GATE__IDCT__SHIFT 0x7 141 #define UVD_CGC_GATE__MPRD_MASK 0x100 142 #define UVD_CGC_GATE__MPRD__SHIFT 0x8 143 #define UVD_CGC_GATE__MPC_MASK 0x200 144 #define UVD_CGC_GATE__MPC__SHIFT 0x9 145 #define UVD_CGC_GATE__LBSI_MASK 0x400 146 #define UVD_CGC_GATE__LBSI__SHIFT 0xa 147 #define UVD_CGC_GATE__LRBBM_MASK 0x800 148 #define UVD_CGC_GATE__LRBBM__SHIFT 0xb 149 #define UVD_CGC_GATE__UDEC_RE_MASK 0x1000 150 #define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc 151 #define UVD_CGC_GATE__UDEC_CM_MASK 0x2000 152 #define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd 153 #define UVD_CGC_GATE__UDEC_IT_MASK 0x4000 154 #define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe 155 #define UVD_CGC_GATE__UDEC_DB_MASK 0x8000 156 #define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf 157 #define UVD_CGC_GATE__UDEC_MP_MASK 0x10000 158 #define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10 159 #define UVD_CGC_GATE__WCB_MASK 0x20000 160 #define UVD_CGC_GATE__WCB__SHIFT 0x11 161 #define UVD_CGC_GATE__VCPU_MASK 0x40000 162 #define UVD_CGC_GATE__VCPU__SHIFT 0x12 163 #define UVD_CGC_GATE__SCPU_MASK 0x80000 164 #define UVD_CGC_GATE__SCPU__SHIFT 0x13 165 #define UVD_CGC_STATUS__SYS_SCLK_MASK 0x1 166 #define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0 167 #define UVD_CGC_STATUS__SYS_DCLK_MASK 0x2 168 #define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1 169 #define UVD_CGC_STATUS__SYS_VCLK_MASK 0x4 170 #define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2 171 #define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x8 172 #define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3 173 #define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x10 174 #define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4 175 #define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x20 176 #define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5 177 #define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x40 178 #define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6 179 #define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x80 180 #define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7 181 #define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x100 182 #define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8 183 #define UVD_CGC_STATUS__REGS_SCLK_MASK 0x200 184 #define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9 185 #define UVD_CGC_STATUS__REGS_VCLK_MASK 0x400 186 #define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa 187 #define UVD_CGC_STATUS__RBC_SCLK_MASK 0x800 188 #define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb 189 #define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x1000 190 #define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc 191 #define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x2000 192 #define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd 193 #define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x4000 194 #define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe 195 #define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x8000 196 #define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf 197 #define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x10000 198 #define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10 199 #define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x20000 200 #define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11 201 #define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x40000 202 #define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12 203 #define UVD_CGC_STATUS__MPC_SCLK_MASK 0x80000 204 #define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13 205 #define UVD_CGC_STATUS__MPC_DCLK_MASK 0x100000 206 #define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14 207 #define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x200000 208 #define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15 209 #define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x400000 210 #define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16 211 #define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x800000 212 #define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17 213 #define UVD_CGC_STATUS__WCB_SCLK_MASK 0x1000000 214 #define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18 215 #define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x2000000 216 #define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19 217 #define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x4000000 218 #define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a 219 #define UVD_CGC_STATUS__SCPU_SCLK_MASK 0x8000000 220 #define UVD_CGC_STATUS__SCPU_SCLK__SHIFT 0x1b 221 #define UVD_CGC_STATUS__SCPU_VCLK_MASK 0x10000000 222 #define UVD_CGC_STATUS__SCPU_VCLK__SHIFT 0x1c 223 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1 224 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 225 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x3c 226 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 227 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x7c0 228 #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 229 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800 230 #define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb 231 #define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x1000 232 #define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc 233 #define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x2000 234 #define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd 235 #define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x4000 236 #define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe 237 #define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x8000 238 #define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf 239 #define UVD_CGC_CTRL__SYS_MODE_MASK 0x10000 240 #define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10 241 #define UVD_CGC_CTRL__UDEC_MODE_MASK 0x20000 242 #define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11 243 #define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x40000 244 #define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12 245 #define UVD_CGC_CTRL__REGS_MODE_MASK 0x80000 246 #define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13 247 #define UVD_CGC_CTRL__RBC_MODE_MASK 0x100000 248 #define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14 249 #define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x200000 250 #define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15 251 #define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x400000 252 #define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16 253 #define UVD_CGC_CTRL__IDCT_MODE_MASK 0x800000 254 #define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17 255 #define UVD_CGC_CTRL__MPRD_MODE_MASK 0x1000000 256 #define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18 257 #define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000 258 #define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19 259 #define UVD_CGC_CTRL__LBSI_MODE_MASK 0x4000000 260 #define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a 261 #define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x8000000 262 #define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b 263 #define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000 264 #define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c 265 #define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000 266 #define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d 267 #define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000 268 #define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e 269 #define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x1 270 #define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0 271 #define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x2 272 #define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1 273 #define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x4 274 #define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2 275 #define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x8 276 #define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3 277 #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x10 278 #define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4 279 #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x20 280 #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 281 #define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x40 282 #define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6 283 #define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x80 284 #define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7 285 #define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x100 286 #define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8 287 #define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x200 288 #define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9 289 #define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x400 290 #define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa 291 #define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x800 292 #define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb 293 #define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x1000 294 #define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc 295 #define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x2000 296 #define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd 297 #define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x4000 298 #define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe 299 #define UVD_LMI_CTRL2__SPH_DIS_MASK 0x1 300 #define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0 301 #define UVD_LMI_CTRL2__STALL_ARB_MASK 0x2 302 #define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1 303 #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x4 304 #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2 305 #define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x8 306 #define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3 307 #define UVD_LMI_CTRL2__MCIF_WR_WATERMARK_MASK 0x70 308 #define UVD_LMI_CTRL2__MCIF_WR_WATERMARK__SHIFT 0x4 309 #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x80 310 #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7 311 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100 312 #define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 313 #define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x600 314 #define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 315 #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x1800 316 #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb 317 #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x2000 318 #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd 319 #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x4000 320 #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe 321 #define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x8000 322 #define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf 323 #define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x10000 324 #define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10 325 #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x1fe0000 326 #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11 327 #define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x1 328 #define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 329 #define UVD_MASTINT_EN__VCPU_EN_MASK 0x2 330 #define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1 331 #define UVD_MASTINT_EN__SYS_EN_MASK 0x4 332 #define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2 333 #define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x7ffff0 334 #define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 335 #define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT_MASK 0xf 336 #define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT__SHIFT 0x0 337 #define UVD_LMI_ADDR_EXT__CM_ADDR_EXT_MASK 0xf0 338 #define UVD_LMI_ADDR_EXT__CM_ADDR_EXT__SHIFT 0x4 339 #define UVD_LMI_ADDR_EXT__IT_ADDR_EXT_MASK 0xf00 340 #define UVD_LMI_ADDR_EXT__IT_ADDR_EXT__SHIFT 0x8 341 #define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT_MASK 0xf000 342 #define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT__SHIFT 0xc 343 #define UVD_LMI_ADDR_EXT__RE_ADDR_EXT_MASK 0xf0000 344 #define UVD_LMI_ADDR_EXT__RE_ADDR_EXT__SHIFT 0x10 345 #define UVD_LMI_ADDR_EXT__MP_ADDR_EXT_MASK 0xf00000 346 #define UVD_LMI_ADDR_EXT__MP_ADDR_EXT__SHIFT 0x14 347 #define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT_MASK 0xf000000 348 #define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT__SHIFT 0x18 349 #define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT_MASK 0xf0000000 350 #define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT__SHIFT 0x1c 351 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0xff 352 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 353 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x100 354 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8 355 #define UVD_LMI_CTRL__REQ_MODE_MASK 0x200 356 #define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9 357 #define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x800 358 #define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb 359 #define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x1000 360 #define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc 361 #define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x2000 362 #define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd 363 #define UVD_LMI_CTRL__CRC_RESET_MASK 0x4000 364 #define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe 365 #define UVD_LMI_CTRL__CRC_SEL_MASK 0xf8000 366 #define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf 367 #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x100000 368 #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x14 369 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x200000 370 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 371 #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x400000 372 #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16 373 #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x800000 374 #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17 375 #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x1000000 376 #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18 377 #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x2000000 378 #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19 379 #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x4000000 380 #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a 381 #define UVD_LMI_CTRL__RFU_MASK 0xf8000000 382 #define UVD_LMI_CTRL__RFU__SHIFT 0x1b 383 #define UVD_LMI_STATUS__READ_CLEAN_MASK 0x1 384 #define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0 385 #define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x2 386 #define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1 387 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x4 388 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2 389 #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x8 390 #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3 391 #define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x10 392 #define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4 393 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x20 394 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5 395 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x40 396 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6 397 #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x80 398 #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7 399 #define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x100 400 #define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8 401 #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x200 402 #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9 403 #define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x400 404 #define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa 405 #define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x800 406 #define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb 407 #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x1000 408 #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc 409 #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x2000 410 #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd 411 #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x3 412 #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 413 #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0xc 414 #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 415 #define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x30 416 #define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4 417 #define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0xc0 418 #define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6 419 #define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x300 420 #define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8 421 #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK 0xc00 422 #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa 423 #define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK 0x3000 424 #define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc 425 #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK 0xc000 426 #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe 427 #define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x30000 428 #define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10 429 #define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK 0xc0000 430 #define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12 431 #define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK 0xc00000 432 #define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT 0x16 433 #define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK 0x3000000 434 #define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18 435 #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0xc000000 436 #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a 437 #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000 438 #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c 439 #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xc0000000 440 #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e 441 #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x3 442 #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0 443 #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0xc 444 #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2 445 #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x30 446 #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4 447 #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0xc0 448 #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6 449 #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x300 450 #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8 451 #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0xc00 452 #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa 453 #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x3000 454 #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc 455 #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0xc000 456 #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe 457 #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x30000 458 #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10 459 #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0xc0000 460 #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12 461 #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x300000 462 #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14 463 #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0xc00000 464 #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16 465 #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x3000000 466 #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18 467 #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0xc000000 468 #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a 469 #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000 470 #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c 471 #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xc0000000 472 #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e 473 #define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x38 474 #define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3 475 #define UVD_MPC_CNTL__PERF_RST_MASK 0x40 476 #define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6 477 #define UVD_MPC_CNTL__DBG_MUX_MASK 0x700 478 #define UVD_MPC_CNTL__DBG_MUX__SHIFT 0x8 479 #define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x30000 480 #define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10 481 #define UVD_MPC_CNTL__URGENT_EN_MASK 0x40000 482 #define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12 483 #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x3f 484 #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 485 #define UVD_MPC_SET_MUXA0__VARA_1_MASK 0xfc0 486 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 487 #define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x3f000 488 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc 489 #define UVD_MPC_SET_MUXA0__VARA_3_MASK 0xfc0000 490 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 491 #define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3f000000 492 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 493 #define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x3f 494 #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0 495 #define UVD_MPC_SET_MUXA1__VARA_6_MASK 0xfc0 496 #define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6 497 #define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x3f000 498 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc 499 #define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x3f 500 #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 501 #define UVD_MPC_SET_MUXB0__VARB_1_MASK 0xfc0 502 #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6 503 #define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x3f000 504 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc 505 #define UVD_MPC_SET_MUXB0__VARB_3_MASK 0xfc0000 506 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 507 #define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3f000000 508 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 509 #define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x3f 510 #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0 511 #define UVD_MPC_SET_MUXB1__VARB_6_MASK 0xfc0 512 #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 513 #define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x3f000 514 #define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc 515 #define UVD_MPC_SET_MUX__SET_0_MASK 0x7 516 #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 517 #define UVD_MPC_SET_MUX__SET_1_MASK 0x38 518 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 519 #define UVD_MPC_SET_MUX__SET_2_MASK 0x1c0 520 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 521 #define UVD_MPC_SET_ALU__FUNCT_MASK 0x7 522 #define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0 523 #define UVD_MPC_SET_ALU__OPERAND_MASK 0xff0 524 #define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4 525 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x1ffffff 526 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 527 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x1fffff 528 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0 529 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x1ffffff 530 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 531 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x1fffff 532 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0 533 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x1ffffff 534 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 535 #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x1fffff 536 #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0 537 #define UVD_VCPU_CNTL__IRQ_ERR_MASK 0xf 538 #define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0 539 #define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4_MASK 0x10 540 #define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4__SHIFT 0x4 541 #define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x20 542 #define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5 543 #define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x40 544 #define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6 545 #define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x80 546 #define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7 547 #define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x100 548 #define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8 549 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200 550 #define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9 551 #define UVD_VCPU_CNTL__TRCE_EN_MASK 0x400 552 #define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa 553 #define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x1800 554 #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb 555 #define UVD_VCPU_CNTL__DBG_MUX_MASK 0xe000 556 #define UVD_VCPU_CNTL__DBG_MUX__SHIFT 0xd 557 #define UVD_VCPU_CNTL__JTAG_EN_MASK 0x10000 558 #define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10 559 #define UVD_VCPU_CNTL__CLK_ACTIVE_MASK 0x20000 560 #define UVD_VCPU_CNTL__CLK_ACTIVE__SHIFT 0x11 561 #define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x40000 562 #define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12 563 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0xff00000 564 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 565 #define UVD_VCPU_CNTL__CABAC_MB_ACC_MASK 0x10000000 566 #define UVD_VCPU_CNTL__CABAC_MB_ACC__SHIFT 0x1c 567 #define UVD_VCPU_CNTL__ECPU_AM32_EN_MASK 0x20000000 568 #define UVD_VCPU_CNTL__ECPU_AM32_EN__SHIFT 0x1d 569 #define UVD_VCPU_CNTL__WMV9_EN_MASK 0x40000000 570 #define UVD_VCPU_CNTL__WMV9_EN__SHIFT 0x1e 571 #define UVD_VCPU_CNTL__RE_OFFLOAD_EN_MASK 0x80000000 572 #define UVD_VCPU_CNTL__RE_OFFLOAD_EN__SHIFT 0x1f 573 #define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x1 574 #define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0 575 #define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x2 576 #define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1 577 #define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x4 578 #define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2 579 #define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x8 580 #define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3 581 #define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x10 582 #define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4 583 #define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK 0x20 584 #define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT 0x5 585 #define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x40 586 #define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6 587 #define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x80 588 #define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7 589 #define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x100 590 #define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8 591 #define UVD_SOFT_RESET__FWV_SOFT_RESET_MASK 0x200 592 #define UVD_SOFT_RESET__FWV_SOFT_RESET__SHIFT 0x9 593 #define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x400 594 #define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa 595 #define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x800 596 #define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb 597 #define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x1000 598 #define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc 599 #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x2000 600 #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd 601 #define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x4000 602 #define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe 603 #define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x8000 604 #define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf 605 #define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x10000 606 #define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10 607 #define UVD_RBC_IB_BASE__IB_BASE_MASK 0xffffffc0 608 #define UVD_RBC_IB_BASE__IB_BASE__SHIFT 0x6 609 #define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x7ffff0 610 #define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4 611 #define UVD_RBC_RB_BASE__RB_BASE_MASK 0xffffffc0 612 #define UVD_RBC_RB_BASE__RB_BASE__SHIFT 0x6 613 #define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x7ffff0 614 #define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4 615 #define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x7ffff0 616 #define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4 617 #define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x1f 618 #define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0 619 #define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x1f00 620 #define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8 621 #define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x10000 622 #define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10 623 #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x100000 624 #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14 625 #define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x1000000 626 #define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18 627 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000 628 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c 629 #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xffffffff 630 #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0 631 #define UVD_STATUS__RBC_BUSY_MASK 0x1 632 #define UVD_STATUS__RBC_BUSY__SHIFT 0x0 633 #define UVD_STATUS__VCPU_REPORT_MASK 0xfe 634 #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 635 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x1 636 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0 637 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x2 638 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1 639 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x4 640 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2 641 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x8 642 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3 643 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x1 644 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0 645 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x1ffffe 646 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1 647 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 648 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 649 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x1 650 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0 651 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x1ffffe 652 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1 653 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 654 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 655 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x1 656 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0 657 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x1ffffe 658 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1 659 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 660 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 661 #define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xffffffff 662 #define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0 663 #define UVD_LMI_CACHE_CTRL__IT_EN_MASK 0x1 664 #define UVD_LMI_CACHE_CTRL__IT_EN__SHIFT 0x0 665 #define UVD_LMI_CACHE_CTRL__IT_FLUSH_MASK 0x2 666 #define UVD_LMI_CACHE_CTRL__IT_FLUSH__SHIFT 0x1 667 #define UVD_LMI_CACHE_CTRL__CM_EN_MASK 0x4 668 #define UVD_LMI_CACHE_CTRL__CM_EN__SHIFT 0x2 669 #define UVD_LMI_CACHE_CTRL__CM_FLUSH_MASK 0x8 670 #define UVD_LMI_CACHE_CTRL__CM_FLUSH__SHIFT 0x3 671 #define UVD_LMI_CACHE_CTRL__VCPU_EN_MASK 0x10 672 #define UVD_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x4 673 #define UVD_LMI_CACHE_CTRL__VCPU_FLUSH_MASK 0x20 674 #define UVD_LMI_CACHE_CTRL__VCPU_FLUSH__SHIFT 0x5 675 #define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP_MASK 0x3 676 #define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP__SHIFT 0x0 677 #define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP_MASK 0xc 678 #define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP__SHIFT 0x2 679 #define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT_MASK 0xf 680 #define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT__SHIFT 0x0 681 #define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT_MASK 0xf0 682 #define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT__SHIFT 0x4 683 #define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT_MASK 0xf00 684 #define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT__SHIFT 0x8 685 #define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT_MASK 0xf000 686 #define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT__SHIFT 0xc 687 #define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN_MASK 0x1 688 #define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN__SHIFT 0x0 689 #define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x2 690 #define UVD_CGC_MEM_CTRL__MPC_LS_EN__SHIFT 0x1 691 #define UVD_CGC_MEM_CTRL__MPRD_LS_EN_MASK 0x4 692 #define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x2 693 #define UVD_CGC_MEM_CTRL__WCB_LS_EN_MASK 0x8 694 #define UVD_CGC_MEM_CTRL__WCB_LS_EN__SHIFT 0x3 695 #define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN_MASK 0x10 696 #define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN__SHIFT 0x4 697 #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x20 698 #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x5 699 #define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN_MASK 0x40 700 #define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN__SHIFT 0x6 701 #define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x80 702 #define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN__SHIFT 0x7 703 #define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x100 704 #define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN__SHIFT 0x8 705 #define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x200 706 #define UVD_CGC_MEM_CTRL__SYS_LS_EN__SHIFT 0x9 707 #define UVD_CGC_MEM_CTRL__VCPU_LS_EN_MASK 0x400 708 #define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0xa 709 #define UVD_CGC_MEM_CTRL__SCPU_LS_EN_MASK 0x800 710 #define UVD_CGC_MEM_CTRL__SCPU_LS_EN__SHIFT 0xb 711 #define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x1000 712 #define UVD_CGC_MEM_CTRL__MIF_LS_EN__SHIFT 0xc 713 #define UVD_CGC_MEM_CTRL__LCM_LS_EN_MASK 0x2000 714 #define UVD_CGC_MEM_CTRL__LCM_LS_EN__SHIFT 0xd 715 #define UVD_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0xf0000 716 #define UVD_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10 717 #define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0xf00000 718 #define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14 719 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x1 720 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0 721 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x2 722 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1 723 #define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x1c 724 #define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2 725 #define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK 0xff 726 #define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR__SHIFT 0x0 727 #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK 0x100 728 #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN__SHIFT 0x8 729 #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK 0x200 730 #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP__SHIFT 0x9 731 #define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK 0x400 732 #define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT__SHIFT 0xa 733 #define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT_MASK 0x800 734 #define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT__SHIFT 0xb 735 #define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE_MASK 0x1000 736 #define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE__SHIFT 0xc 737 #define UVD_PGFSM_CONFIG__UVD_PGFSM_READ_MASK 0x2000 738 #define UVD_PGFSM_CONFIG__UVD_PGFSM_READ__SHIFT 0xd 739 #define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR_MASK 0xf0000000 740 #define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR__SHIFT 0x1c 741 #define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE_MASK 0xffffff 742 #define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE__SHIFT 0x0 743 #define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE_MASK 0xffffff 744 #define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE__SHIFT 0x0 745 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x1 746 #define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0 747 #define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES_MASK 0x7 748 #define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 749 #define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 750 #define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 751 #define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 752 #define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 753 #define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 754 #define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 755 #define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 756 #define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 757 #define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 758 #define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 759 #define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 760 #define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 761 #define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 762 #define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 763 #define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 764 #define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 765 #define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES_MASK 0x7 766 #define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 767 #define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 768 #define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 769 #define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 770 #define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 771 #define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 772 #define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 773 #define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 774 #define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 775 #define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 776 #define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 777 #define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 778 #define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 779 #define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 780 #define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 781 #define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 782 #define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 783 #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES_MASK 0x7 784 #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 785 #define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 786 #define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 787 #define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 788 #define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 789 #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 790 #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 791 #define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 792 #define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 793 #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 794 #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 795 #define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 796 #define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 797 #define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 798 #define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 799 #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 800 #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 801 802 #endif /* UVD_4_2_SH_MASK_H */ 803