1 /* $NetBSD: ti_iic.c,v 1.13 2021/01/27 03:10:20 thorpej Exp $ */
2
3 /*
4 * Copyright (c) 2013 Manuel Bouyer. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 /*-
28 * Copyright (c) 2012 Jared D. McNeill <jmcneill@invisible.ca>
29 * All rights reserved.
30 *
31 * Redistribution and use in source and binary forms, with or without
32 * modification, are permitted provided that the following conditions
33 * are met:
34 * 1. Redistributions of source code must retain the above copyright
35 * notice, this list of conditions and the following disclaimer.
36 * 2. The name of the author may not be used to endorse or promote products
37 * derived from this software without specific prior written permission.
38 *
39 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
40 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
41 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
42 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
43 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
44 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
45 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
46 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
47 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
48 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
49 * SUCH DAMAGE.
50 */
51
52 #include <sys/cdefs.h>
53 __KERNEL_RCSID(0, "$NetBSD: ti_iic.c,v 1.13 2021/01/27 03:10:20 thorpej Exp $");
54
55 #include <sys/param.h>
56 #include <sys/systm.h>
57 #include <sys/device.h>
58 #include <sys/conf.h>
59 #include <sys/bus.h>
60 #include <sys/proc.h>
61 #include <sys/kernel.h>
62 #include <sys/mutex.h>
63 #include <sys/condvar.h>
64
65 #include <dev/i2c/i2cvar.h>
66
67 #include <dev/fdt/fdtvar.h>
68
69 #include <arm/ti/ti_prcm.h>
70 #include <arm/ti/ti_iicreg.h>
71
72 #ifndef OMAP2_I2C_SLAVE_ADDR
73 #define OMAP2_I2C_SLAVE_ADDR 0x01
74 #endif
75
76 #define OMAP2_I2C_FIFOBYTES(fd) (8 << (fd))
77
78 #ifdef I2CDEBUG
79 #define DPRINTF(args) printf args
80 #else
81 #define DPRINTF(args)
82 #endif
83
84 enum ti_iic_type {
85 TI_IIC_OMAP3,
86 TI_IIC_OMAP4,
87 TI_NTYPES
88 };
89
90 enum {
91 I2C_SYSC,
92 I2C_IRQSTATUS_RAW,
93 I2C_IRQSTATUS,
94 I2C_IRQENABLE, /* OMAP3 */
95 I2C_IRQENABLE_SET, /* OMAP4 */
96 I2C_IRQENABLE_CLR, /* OMAP4 */
97 I2C_SYSS,
98 I2C_BUF,
99 I2C_CNT,
100 I2C_DATA,
101 I2C_CON,
102 I2C_OA,
103 I2C_SA,
104 I2C_PSC,
105 I2C_SCLL,
106 I2C_SCLH,
107 I2C_BUFSTAT,
108 TI_NREGS
109 };
110
111 static const u_int ti_iic_regmap[TI_NTYPES][TI_NREGS] = {
112 [TI_IIC_OMAP3] = {
113 [I2C_SYSC] = 0x20,
114 [I2C_IRQSTATUS_RAW] = 0x08,
115 [I2C_IRQSTATUS] = 0x08,
116 [I2C_IRQENABLE] = 0x04,
117 [I2C_SYSS] = 0x10,
118 [I2C_BUF] = 0x14,
119 [I2C_CNT] = 0x18,
120 [I2C_DATA] = 0x1c,
121 [I2C_CON] = 0x24,
122 [I2C_OA] = 0x28,
123 [I2C_SA] = 0x2c,
124 [I2C_PSC] = 0x30,
125 [I2C_SCLL] = 0x34,
126 [I2C_SCLH] = 0x38,
127 [I2C_BUFSTAT] = 0x40,
128 },
129 [TI_IIC_OMAP4] = {
130 [I2C_SYSC] = 0x10,
131 [I2C_IRQSTATUS_RAW] = 0x24,
132 [I2C_IRQSTATUS] = 0x28,
133 [I2C_IRQENABLE_SET] = 0x2c,
134 [I2C_IRQENABLE_CLR] = 0x30,
135 [I2C_SYSS] = 0x90,
136 [I2C_BUF] = 0x94,
137 [I2C_CNT] = 0x98,
138 [I2C_DATA] = 0x9c,
139 [I2C_CON] = 0xa4,
140 [I2C_OA] = 0xa8,
141 [I2C_SA] = 0xac,
142 [I2C_PSC] = 0xb0,
143 [I2C_SCLL] = 0xb4,
144 [I2C_SCLH] = 0xb8,
145 [I2C_BUFSTAT] = 0xc0,
146 },
147 };
148
149 static const struct device_compatible_entry compat_data[] = {
150 /* compatible type */
151 { .compat = "ti,omap3-i2c", .value = TI_IIC_OMAP3 },
152 { .compat = "ti,omap4-i2c", .value = TI_IIC_OMAP4 },
153 DEVICE_COMPAT_EOL
154 };
155
156 /* operation in progress */
157 typedef enum {
158 TI_I2CREAD,
159 TI_I2CWRITE,
160 TI_I2CDONE,
161 TI_I2CERROR
162 } ti_i2cop_t;
163
164 struct ti_iic_softc {
165 device_t sc_dev;
166 struct i2c_controller sc_ic;
167 kmutex_t sc_lock;
168 device_t sc_i2cdev;
169
170 bus_space_tag_t sc_iot;
171 bus_space_handle_t sc_ioh;
172
173 enum ti_iic_type sc_type;
174
175 void *sc_ih;
176 kmutex_t sc_mtx;
177 kcondvar_t sc_cv;
178 ti_i2cop_t sc_op;
179 int sc_opflags;
180 int sc_buflen;
181 int sc_bufidx;
182 char *sc_buf;
183
184 bool sc_busy;
185
186 int sc_rxthres;
187 int sc_txthres;
188 };
189
190 #define I2C_READ_REG(sc, reg) \
191 bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, ti_iic_regmap[(sc)->sc_type][(reg)])
192 #define I2C_READ_DATA(sc) \
193 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, ti_iic_regmap[(sc)->sc_type][I2C_DATA])
194 #define I2C_WRITE_REG(sc, reg, val) \
195 bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, ti_iic_regmap[(sc)->sc_type][(reg)], (val))
196 #define I2C_WRITE_DATA(sc, val) \
197 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, ti_iic_regmap[(sc)->sc_type][I2C_DATA], (val))
198
199 static int ti_iic_match(device_t, cfdata_t, void *);
200 static void ti_iic_attach(device_t, device_t, void *);
201
202 static int ti_iic_intr(void *);
203
204 static int ti_iic_acquire_bus(void *, int);
205 static void ti_iic_release_bus(void *, int);
206 static int ti_iic_exec(void *, i2c_op_t, i2c_addr_t, const void *,
207 size_t, void *, size_t, int);
208
209 static int ti_iic_reset(struct ti_iic_softc *);
210 static int ti_iic_op(struct ti_iic_softc *, i2c_addr_t, ti_i2cop_t,
211 uint8_t *, size_t, int);
212 static void ti_iic_handle_intr(struct ti_iic_softc *, uint32_t);
213 static void ti_iic_do_read(struct ti_iic_softc *, uint32_t);
214 static void ti_iic_do_write(struct ti_iic_softc *, uint32_t);
215
216 static int ti_iic_wait(struct ti_iic_softc *, uint16_t, uint16_t, int);
217 static uint32_t ti_iic_stat(struct ti_iic_softc *, uint32_t);
218 static int ti_iic_flush(struct ti_iic_softc *);
219
220 CFATTACH_DECL_NEW(ti_iic, sizeof(struct ti_iic_softc),
221 ti_iic_match, ti_iic_attach, NULL, NULL);
222
223 static int
ti_iic_match(device_t parent,cfdata_t match,void * opaque)224 ti_iic_match(device_t parent, cfdata_t match, void *opaque)
225 {
226 struct fdt_attach_args * const faa = opaque;
227
228 return of_compatible_match(faa->faa_phandle, compat_data);
229 }
230
231 static void
ti_iic_attach(device_t parent,device_t self,void * opaque)232 ti_iic_attach(device_t parent, device_t self, void *opaque)
233 {
234 struct ti_iic_softc *sc = device_private(self);
235 struct fdt_attach_args * const faa = opaque;
236 const int phandle = faa->faa_phandle;
237 int fifodepth, fifo;
238 const char *modname;
239 char intrstr[128];
240 bus_addr_t addr;
241 bus_size_t size;
242
243 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
244 aprint_error(": couldn't get registers\n");
245 return;
246 }
247 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
248 aprint_error(": couldn't decode interrupt\n");
249 return;
250 }
251
252 if (ti_prcm_enable_hwmod(phandle, 0) != 0) {
253 aprint_error(": couldn't enable module\n");
254 return;
255 }
256
257 sc->sc_dev = self;
258 sc->sc_iot = faa->faa_bst;
259 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE);
260 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_NET);
261 cv_init(&sc->sc_cv, "tiiic");
262 iic_tag_init(&sc->sc_ic);
263 sc->sc_ic.ic_cookie = sc;
264 sc->sc_ic.ic_acquire_bus = ti_iic_acquire_bus;
265 sc->sc_ic.ic_release_bus = ti_iic_release_bus;
266 sc->sc_ic.ic_exec = ti_iic_exec;
267
268 if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh) != 0) {
269 aprint_error(": couldn't map registers\n");
270 return;
271 }
272 sc->sc_type = of_compatible_lookup(phandle, compat_data)->value;
273
274 sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_NET, 0,
275 ti_iic_intr, sc, device_xname(self));
276 if (sc->sc_ih == NULL) {
277 aprint_error(": couldn't establish interrupt\n");
278 return;
279 }
280
281 modname = fdtbus_get_string(phandle, "ti,hwmods");
282 if (modname == NULL)
283 modname = fdtbus_get_string(OF_parent(phandle), "ti,hwmods");
284
285 fifodepth = I2C_BUFSTAT_FIFODEPTH(I2C_READ_REG(sc, I2C_BUFSTAT));
286 fifo = OMAP2_I2C_FIFOBYTES(fifodepth);
287 sc->sc_rxthres = sc->sc_txthres = fifo >> 1;
288
289 aprint_naive("\n");
290 if (modname != NULL)
291 aprint_normal(": I2C controller (%s), %d-bytes FIFO\n", modname, fifo);
292 else
293 aprint_normal(": I2C controller (i2c@%" PRIxBUSADDR "), %d-bytes FIFO\n",
294 addr, fifo);
295
296 ti_iic_reset(sc);
297 ti_iic_flush(sc);
298
299 fdtbus_register_i2c_controller(&sc->sc_ic, phandle);
300
301 fdtbus_attach_i2cbus(self, phandle, &sc->sc_ic, iicbus_print);
302 }
303
304 static int
ti_iic_intr(void * arg)305 ti_iic_intr(void *arg)
306 {
307 struct ti_iic_softc *sc = arg;
308 uint32_t stat;
309
310 mutex_enter(&sc->sc_mtx);
311 DPRINTF(("ti_iic_intr opflags=%#x\n", sc->sc_opflags));
312 if ((sc->sc_opflags & I2C_F_POLL) == 0) {
313 stat = I2C_READ_REG(sc, I2C_IRQSTATUS);
314 DPRINTF(("ti_iic_intr pre handle sc->sc_op eq %#x\n", sc->sc_op));
315 ti_iic_handle_intr(sc, stat);
316 I2C_WRITE_REG(sc, I2C_IRQSTATUS, stat);
317 if (sc->sc_op == TI_I2CERROR || sc->sc_op == TI_I2CDONE) {
318 DPRINTF(("ti_iic_intr post handle sc->sc_op %#x\n", sc->sc_op));
319 cv_broadcast(&sc->sc_cv);
320 }
321 }
322 mutex_exit(&sc->sc_mtx);
323 DPRINTF(("ti_iic_intr status 0x%x\n", stat));
324 return 1;
325 }
326
327 static int
ti_iic_acquire_bus(void * opaque,int flags)328 ti_iic_acquire_bus(void *opaque, int flags)
329 {
330 struct ti_iic_softc *sc = opaque;
331
332 mutex_enter(&sc->sc_lock);
333 while (sc->sc_busy)
334 cv_wait(&sc->sc_cv, &sc->sc_lock);
335 sc->sc_busy = true;
336 mutex_exit(&sc->sc_lock);
337
338 return 0;
339 }
340
341 static void
ti_iic_release_bus(void * opaque,int flags)342 ti_iic_release_bus(void *opaque, int flags)
343 {
344 struct ti_iic_softc *sc = opaque;
345
346 mutex_enter(&sc->sc_lock);
347 sc->sc_busy = false;
348 cv_broadcast(&sc->sc_cv);
349 mutex_exit(&sc->sc_lock);
350 }
351
352 static int
ti_iic_exec(void * opaque,i2c_op_t op,i2c_addr_t addr,const void * cmdbuf,size_t cmdlen,void * buf,size_t len,int flags)353 ti_iic_exec(void *opaque, i2c_op_t op, i2c_addr_t addr,
354 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags)
355 {
356 struct ti_iic_softc *sc = opaque;
357 int err;
358
359 DPRINTF(("ti_iic_exec: op 0x%x cmdlen %zd len %zd flags 0x%x\n",
360 op, cmdlen, len, flags));
361
362 if (cmdlen > 0) {
363 err = ti_iic_op(sc, addr, TI_I2CWRITE,
364 __UNCONST(cmdbuf), cmdlen,
365 (I2C_OP_READ_P(op) ? 0 : I2C_F_STOP) | flags);
366 if (err)
367 goto done;
368 }
369
370 if (I2C_OP_STOP_P(op))
371 flags |= I2C_F_STOP;
372
373 /*
374 * I2C controller doesn't allow for zero-byte transfers.
375 */
376 if (len == 0) {
377 err = EINVAL;
378 goto done;
379 }
380
381 if (I2C_OP_READ_P(op)) {
382 err = ti_iic_op(sc, addr, TI_I2CREAD, buf, len, flags);
383 } else {
384 err = ti_iic_op(sc, addr, TI_I2CWRITE, buf, len, flags);
385 }
386
387 done:
388 if (err)
389 ti_iic_reset(sc);
390
391 ti_iic_flush(sc);
392
393 DPRINTF(("ti_iic_exec: done %d\n", err));
394 return err;
395 }
396
397 static int
ti_iic_reset(struct ti_iic_softc * sc)398 ti_iic_reset(struct ti_iic_softc *sc)
399 {
400 uint32_t psc, scll, sclh;
401 int i;
402
403 DPRINTF(("ti_iic_reset\n"));
404
405 /* Disable */
406 I2C_WRITE_REG(sc, I2C_CON, 0);
407 /* Soft reset */
408 I2C_WRITE_REG(sc, I2C_SYSC, I2C_SYSC_SRST);
409 delay(1000);
410 /* enable so that we can check for reset complete */
411 I2C_WRITE_REG(sc, I2C_CON, I2C_CON_EN);
412 delay(1000);
413 for (i = 0; i < 1000; i++) { /* 1s delay for reset */
414 if (I2C_READ_REG(sc, I2C_SYSS) & I2C_SYSS_RDONE)
415 break;
416 }
417 /* Disable again */
418 I2C_WRITE_REG(sc, I2C_CON, 0);
419 delay(50000);
420
421 if (i >= 1000) {
422 aprint_error_dev(sc->sc_dev, ": couldn't reset module\n");
423 return 1;
424 }
425
426
427 /* XXX standard speed only */
428 if (sc->sc_type == TI_IIC_OMAP3) {
429 psc = (96000000 / 19200000) - 1;
430 scll = sclh = (19200000 / (2 * 100000)) - 6;
431 } else {
432 psc = 3;
433 scll = 53;
434 sclh = 55;
435 }
436
437 /* Clocks */
438 I2C_WRITE_REG(sc, I2C_PSC, psc);
439 I2C_WRITE_REG(sc, I2C_SCLL, scll);
440 I2C_WRITE_REG(sc, I2C_SCLH, sclh);
441
442 /* Own I2C address */
443 I2C_WRITE_REG(sc, I2C_OA, OMAP2_I2C_SLAVE_ADDR);
444
445 /* 5 bytes fifo */
446 I2C_WRITE_REG(sc, I2C_BUF,
447 I2C_BUF_RXTRSH(sc->sc_rxthres) | I2C_BUF_TXTRSH(sc->sc_txthres));
448
449 /* Enable */
450 I2C_WRITE_REG(sc, I2C_CON, I2C_CON_EN);
451
452 return 0;
453 }
454
455 static int
ti_iic_op(struct ti_iic_softc * sc,i2c_addr_t addr,ti_i2cop_t op,uint8_t * buf,size_t buflen,int flags)456 ti_iic_op(struct ti_iic_softc *sc, i2c_addr_t addr, ti_i2cop_t op,
457 uint8_t *buf, size_t buflen, int flags)
458 {
459 uint16_t con, stat, mask;
460 int err, retry;
461
462 KASSERT(op == TI_I2CREAD || op == TI_I2CWRITE);
463 DPRINTF(("ti_iic_op: addr %#x op %#x buf %p buflen %#x flags %#x\n",
464 addr, op, buf, (unsigned int) buflen, flags));
465
466 mask = I2C_IRQSTATUS_ARDY | I2C_IRQSTATUS_NACK | I2C_IRQSTATUS_AL;
467 if (op == TI_I2CREAD) {
468 mask |= I2C_IRQSTATUS_RDR | I2C_IRQSTATUS_RRDY;
469 } else {
470 mask |= I2C_IRQSTATUS_XDR | I2C_IRQSTATUS_XRDY;
471 }
472
473 err = ti_iic_wait(sc, I2C_IRQSTATUS_BB, 0, flags);
474 if (err) {
475 DPRINTF(("ti_iic_op: wait error %d\n", err));
476 return err;
477 }
478
479 con = I2C_CON_EN;
480 con |= I2C_CON_MST;
481 con |= I2C_CON_STT;
482 if (flags & I2C_F_STOP)
483 con |= I2C_CON_STP;
484 if (addr & ~0x7f)
485 con |= I2C_CON_XSA;
486 if (op == TI_I2CWRITE)
487 con |= I2C_CON_TRX;
488
489 mutex_enter(&sc->sc_mtx);
490 sc->sc_op = op;
491 sc->sc_opflags = flags;
492 sc->sc_buf = buf;
493 sc->sc_buflen = buflen;
494 sc->sc_bufidx = 0;
495
496 I2C_WRITE_REG(sc, I2C_CON, I2C_CON_EN | I2C_CON_MST | I2C_CON_STP);
497 DPRINTF(("ti_iic_op: op %d con 0x%x ", op, con));
498 I2C_WRITE_REG(sc, I2C_CNT, buflen);
499 I2C_WRITE_REG(sc, I2C_SA, (addr & I2C_SA_MASK));
500 DPRINTF(("SA 0x%x len %d\n", I2C_READ_REG(sc, I2C_SA), I2C_READ_REG(sc, I2C_CNT)));
501
502 if ((flags & I2C_F_POLL) == 0 || sc->sc_type == TI_IIC_OMAP3) {
503 /* clear any pending interrupt */
504 I2C_WRITE_REG(sc, I2C_IRQSTATUS,
505 I2C_READ_REG(sc, I2C_IRQSTATUS));
506 /* and enable */
507 if (sc->sc_type == TI_IIC_OMAP4) {
508 I2C_WRITE_REG(sc, I2C_IRQENABLE_SET, mask);
509 } else {
510 I2C_WRITE_REG(sc, I2C_IRQENABLE, mask);
511 }
512 }
513 /* start transfer */
514 I2C_WRITE_REG(sc, I2C_CON, con);
515
516 if ((flags & I2C_F_POLL) == 0) {
517 /* and wait for completion */
518 DPRINTF(("ti_iic_op waiting, op %#x\n", sc->sc_op));
519 while (sc->sc_op == op) {
520 if (cv_timedwait(&sc->sc_cv, &sc->sc_mtx,
521 mstohz(5000)) == EWOULDBLOCK) {
522 /* timeout */
523 op = TI_I2CERROR;
524 }
525 }
526 DPRINTF(("ti_iic_op waiting done, op %#x\n", sc->sc_op));
527
528 /* disable interrupts */
529 if (sc->sc_type == TI_IIC_OMAP4) {
530 I2C_WRITE_REG(sc, I2C_IRQENABLE_CLR, 0xffff);
531 } else {
532 I2C_WRITE_REG(sc, I2C_IRQENABLE, 0);
533 }
534 } else {
535 /* poll for completion */
536 DPRINTF(("ti_iic_op polling, op %x\n", sc->sc_op));
537 while (sc->sc_op == op) {
538 stat = ti_iic_stat(sc, mask);
539 DPRINTF(("ti_iic_op stat 0x%x\n", stat));
540 if (stat == 0) {
541 /* timeout */
542 sc->sc_op = TI_I2CERROR;
543 } else {
544 ti_iic_handle_intr(sc, stat);
545 }
546 I2C_WRITE_REG(sc, I2C_IRQSTATUS, stat);
547 }
548 DPRINTF(("ti_iic_op polling done, op now %x\n", sc->sc_op));
549 }
550 mutex_exit(&sc->sc_mtx);
551 retry = 10000;
552 I2C_WRITE_REG(sc, I2C_CON, 0);
553 while (I2C_READ_REG(sc, I2C_CON) & I2C_CON_MST) {
554 delay(100);
555 if (--retry == 0)
556 break;
557 }
558 return (sc->sc_op == TI_I2CDONE) ? 0 : EIO;
559 }
560
561 static void
ti_iic_handle_intr(struct ti_iic_softc * sc,uint32_t stat)562 ti_iic_handle_intr(struct ti_iic_softc *sc, uint32_t stat)
563 {
564 KASSERT(mutex_owned(&sc->sc_mtx));
565 KASSERT(stat != 0);
566 DPRINTF(("ti_iic_handle_intr stat %#x\n", stat));
567
568 if (stat &
569 (I2C_IRQSTATUS_NACK|I2C_IRQSTATUS_AL)) {
570 sc->sc_op = TI_I2CERROR;
571 return;
572 }
573 if (stat & I2C_IRQSTATUS_ARDY) {
574 sc->sc_op = TI_I2CDONE;
575 return;
576 }
577 if (sc->sc_op == TI_I2CREAD)
578 ti_iic_do_read(sc, stat);
579 else if (sc->sc_op == TI_I2CWRITE)
580 ti_iic_do_write(sc, stat);
581 else
582 return;
583 }
584 void
ti_iic_do_read(struct ti_iic_softc * sc,uint32_t stat)585 ti_iic_do_read(struct ti_iic_softc *sc, uint32_t stat)
586 {
587 int len = 0;
588
589 KASSERT(mutex_owned(&sc->sc_mtx));
590 DPRINTF(("ti_iic_do_read stat %#x\n", stat));
591 if (stat & I2C_IRQSTATUS_RDR) {
592 len = I2C_READ_REG(sc, I2C_BUFSTAT);
593 len = I2C_BUFSTAT_RXSTAT(len);
594 DPRINTF(("ti_iic_do_read receive drain len %d left %d\n",
595 len, I2C_READ_REG(sc, I2C_CNT)));
596 } else if (stat & I2C_IRQSTATUS_RRDY) {
597 len = sc->sc_rxthres + 1;
598 DPRINTF(("ti_iic_do_read receive len %d left %d\n",
599 len, I2C_READ_REG(sc, I2C_CNT)));
600 }
601 for (;
602 sc->sc_bufidx < sc->sc_buflen && len > 0;
603 sc->sc_bufidx++, len--) {
604 sc->sc_buf[sc->sc_bufidx] = I2C_READ_DATA(sc);
605 DPRINTF(("ti_iic_do_read got b[%d]=0x%x\n", sc->sc_bufidx,
606 sc->sc_buf[sc->sc_bufidx]));
607 }
608 DPRINTF(("ti_iic_do_read done\n"));
609 }
610
611 void
ti_iic_do_write(struct ti_iic_softc * sc,uint32_t stat)612 ti_iic_do_write(struct ti_iic_softc *sc, uint32_t stat)
613 {
614 int len = 0;
615
616 DPRINTF(("ti_iic_do_write stat %#x\n", stat));
617 KASSERT(mutex_owned(&sc->sc_mtx));
618 if (stat & I2C_IRQSTATUS_XDR) {
619 len = I2C_READ_REG(sc, I2C_BUFSTAT);
620 len = I2C_BUFSTAT_TXSTAT(len);
621 DPRINTF(("ti_iic_do_write xmit drain len %d left %d\n",
622 len, I2C_READ_REG(sc, I2C_CNT)));
623 } else if (stat & I2C_IRQSTATUS_XRDY) {
624 len = sc->sc_txthres + 1;
625 DPRINTF(("ti_iic_do_write xmit len %d left %d\n",
626 len, I2C_READ_REG(sc, I2C_CNT)));
627 }
628 for (;
629 sc->sc_bufidx < sc->sc_buflen && len > 0;
630 sc->sc_bufidx++, len--) {
631 DPRINTF(("ti_iic_do_write send b[%d]=0x%x\n",
632 sc->sc_bufidx, sc->sc_buf[sc->sc_bufidx]));
633 I2C_WRITE_DATA(sc, sc->sc_buf[sc->sc_bufidx]);
634 }
635 DPRINTF(("ti_iic_do_write done\n"));
636 }
637
638 static int
ti_iic_wait(struct ti_iic_softc * sc,uint16_t mask,uint16_t val,int flags)639 ti_iic_wait(struct ti_iic_softc *sc, uint16_t mask, uint16_t val, int flags)
640 {
641 int retry = 10;
642 uint16_t v;
643 DPRINTF(("ti_iic_wait mask %#x val %#x flags %#x\n", mask, val, flags));
644
645 while (((v = I2C_READ_REG(sc, I2C_IRQSTATUS_RAW)) & mask) != val) {
646 --retry;
647 if (retry == 0) {
648 aprint_error_dev(sc->sc_dev, ": wait timeout, "
649 "mask = %#x val = %#x stat = %#x\n",
650 mask, val, v);
651 return EBUSY;
652 }
653 if (flags & I2C_F_POLL) {
654 delay(50000);
655 } else {
656 kpause("tiiic", false, mstohz(50), NULL);
657 }
658 }
659 DPRINTF(("ti_iic_wait done retry %#x\n", retry));
660
661 return 0;
662 }
663
664 static uint32_t
ti_iic_stat(struct ti_iic_softc * sc,uint32_t mask)665 ti_iic_stat(struct ti_iic_softc *sc, uint32_t mask)
666 {
667 uint32_t v;
668 int retry = 500;
669 DPRINTF(("ti_iic_wait mask %#x\n", mask));
670 while (--retry > 0) {
671 v = I2C_READ_REG(sc, I2C_IRQSTATUS_RAW) & mask;
672 if (v != 0)
673 break;
674 delay(100);
675 }
676 DPRINTF(("ti_iic_wait done retry %#x\n", retry));
677 return v;
678 }
679
680 static int
ti_iic_flush(struct ti_iic_softc * sc)681 ti_iic_flush(struct ti_iic_softc *sc)
682 {
683 DPRINTF(("ti_iic_flush\n"));
684 #if 0
685 int retry = 1000;
686 uint16_t v;
687
688 while ((v = I2C_READ_REG(sc, I2C_IRQSTATUS_RAW)) & I2C_IRQSTATUS_RRDY) {
689 if (--retry == 0) {
690 aprint_error_dev(sc->sc_dev,
691 ": flush timeout, stat = %#x\n", v);
692 return EBUSY;
693 }
694 (void)I2C_READ_DATA(sc);
695 delay(1000);
696 }
697 #endif
698
699 I2C_WRITE_REG(sc, I2C_CNT, 0);
700 return 0;
701 }
702