1 /* $NetBSD: ti_gpio.c,v 1.15 2024/04/01 15:52:08 jakllsch Exp $ */
2
3 /*-
4 * Copyright (c) 2019 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: ti_gpio.c,v 1.15 2024/04/01 15:52:08 jakllsch Exp $");
31
32 #include <sys/param.h>
33 #include <sys/bitops.h>
34 #include <sys/bus.h>
35 #include <sys/device.h>
36 #include <sys/gpio.h>
37 #include <sys/intr.h>
38 #include <sys/kmem.h>
39 #include <sys/lwp.h>
40 #include <sys/mutex.h>
41 #include <sys/systm.h>
42
43 #include <dev/fdt/fdtvar.h>
44 #include <dev/gpio/gpiovar.h>
45
46 #include <arm/ti/ti_prcm.h>
47
48 #define TI_GPIO_NPINS 32
49
50 enum ti_gpio_type {
51 TI_GPIO_OMAP3,
52 TI_GPIO_OMAP4,
53 TI_NGPIO
54 };
55
56 enum {
57 GPIO_IRQSTATUS1,
58 GPIO_IRQENABLE1, /* OMAP3 */
59 GPIO_IRQENABLE1_SET, /* OMAP4 */
60 GPIO_IRQENABLE1_CLR, /* OMAP4 */
61 GPIO_OE,
62 GPIO_DATAIN,
63 GPIO_DATAOUT,
64 GPIO_LEVELDETECT0,
65 GPIO_LEVELDETECT1,
66 GPIO_RISINGDETECT,
67 GPIO_FALLINGDETECT,
68 GPIO_CLEARDATAOUT,
69 GPIO_SETDATAOUT,
70 GPIO_NREG
71 };
72
73 static const u_int ti_gpio_regmap[TI_NGPIO][GPIO_NREG] = {
74 [TI_GPIO_OMAP3] = {
75 [GPIO_IRQSTATUS1] = 0x18,
76 [GPIO_IRQENABLE1] = 0x1c,
77 [GPIO_OE] = 0x34,
78 [GPIO_DATAIN] = 0x38,
79 [GPIO_DATAOUT] = 0x3c,
80 [GPIO_LEVELDETECT0] = 0x40,
81 [GPIO_LEVELDETECT1] = 0x44,
82 [GPIO_RISINGDETECT] = 0x48,
83 [GPIO_FALLINGDETECT] = 0x4c,
84 [GPIO_CLEARDATAOUT] = 0x90,
85 [GPIO_SETDATAOUT] = 0x94,
86 },
87 [TI_GPIO_OMAP4] = {
88 [GPIO_IRQSTATUS1] = 0x2c,
89 [GPIO_IRQENABLE1_SET] = 0x34,
90 [GPIO_IRQENABLE1_CLR] = 0x38,
91 [GPIO_OE] = 0x134,
92 [GPIO_DATAIN] = 0x138,
93 [GPIO_DATAOUT] = 0x13c,
94 [GPIO_LEVELDETECT0] = 0x140,
95 [GPIO_LEVELDETECT1] = 0x144,
96 [GPIO_RISINGDETECT] = 0x148,
97 [GPIO_FALLINGDETECT] = 0x14c,
98 [GPIO_CLEARDATAOUT] = 0x190,
99 [GPIO_SETDATAOUT] = 0x194,
100 },
101 };
102
103 static const struct device_compatible_entry compat_data[] = {
104 { .compat = "ti,omap3-gpio", .value = TI_GPIO_OMAP3 },
105 { .compat = "ti,omap4-gpio", .value = TI_GPIO_OMAP4 },
106 DEVICE_COMPAT_EOL
107 };
108
109 struct ti_gpio_intr {
110 u_int intr_pin;
111 int (*intr_func)(void *);
112 void *intr_arg;
113 bool intr_mpsafe;
114 };
115
116 struct ti_gpio_softc {
117 device_t sc_dev;
118 bus_space_tag_t sc_bst;
119 bus_space_handle_t sc_bsh;
120 kmutex_t sc_lock;
121 enum ti_gpio_type sc_type;
122 const char *sc_modname;
123 void *sc_ih;
124
125 struct gpio_chipset_tag sc_gp;
126 gpio_pin_t sc_pins[TI_GPIO_NPINS];
127 bool sc_pinout[TI_GPIO_NPINS];
128 struct ti_gpio_intr sc_intr[TI_GPIO_NPINS];
129 device_t sc_gpiodev;
130 };
131
132 struct ti_gpio_pin {
133 struct ti_gpio_softc *pin_sc;
134 u_int pin_nr;
135 int pin_flags;
136 bool pin_actlo;
137 };
138
139 #define RD4(sc, reg) \
140 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, ti_gpio_regmap[(sc)->sc_type][(reg)])
141 #define WR4(sc, reg, val) \
142 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, ti_gpio_regmap[(sc)->sc_type][(reg)], (val))
143
144 static int ti_gpio_match(device_t, cfdata_t, void *);
145 static void ti_gpio_attach(device_t, device_t, void *);
146
147 CFATTACH_DECL_NEW(ti_gpio, sizeof(struct ti_gpio_softc),
148 ti_gpio_match, ti_gpio_attach, NULL, NULL);
149
150 static int
ti_gpio_ctl(struct ti_gpio_softc * sc,u_int pin,int flags)151 ti_gpio_ctl(struct ti_gpio_softc *sc, u_int pin, int flags)
152 {
153 uint32_t oe;
154
155 KASSERT(mutex_owned(&sc->sc_lock));
156
157 oe = RD4(sc, GPIO_OE);
158 if (flags & GPIO_PIN_INPUT)
159 oe |= __BIT(pin);
160 else if (flags & GPIO_PIN_OUTPUT)
161 oe &= ~__BIT(pin);
162 WR4(sc, GPIO_OE, oe);
163
164 sc->sc_pinout[pin] = (flags & GPIO_PIN_OUTPUT) != 0;
165
166 return 0;
167 }
168
169 static void *
ti_gpio_acquire(device_t dev,const void * data,size_t len,int flags)170 ti_gpio_acquire(device_t dev, const void *data, size_t len, int flags)
171 {
172 struct ti_gpio_softc * const sc = device_private(dev);
173 struct ti_gpio_pin *gpin;
174 const u_int *gpio = data;
175 int error;
176
177 if (len != 12)
178 return NULL;
179
180 const uint8_t pin = be32toh(gpio[1]) & 0xff;
181 const bool actlo = be32toh(gpio[2]) & 1;
182
183 if (pin >= __arraycount(sc->sc_pins))
184 return NULL;
185
186 mutex_enter(&sc->sc_lock);
187 error = ti_gpio_ctl(sc, pin, flags);
188 mutex_exit(&sc->sc_lock);
189
190 if (error != 0)
191 return NULL;
192
193 gpin = kmem_zalloc(sizeof(*gpin), KM_SLEEP);
194 gpin->pin_sc = sc;
195 gpin->pin_nr = pin;
196 gpin->pin_flags = flags;
197 gpin->pin_actlo = actlo;
198
199 return gpin;
200 }
201
202 static void
ti_gpio_release(device_t dev,void * priv)203 ti_gpio_release(device_t dev, void *priv)
204 {
205 struct ti_gpio_softc * const sc = device_private(dev);
206 struct ti_gpio_pin *pin = priv;
207
208 mutex_enter(&sc->sc_lock);
209 ti_gpio_ctl(pin->pin_sc, pin->pin_nr, GPIO_PIN_INPUT);
210 mutex_exit(&sc->sc_lock);
211
212 kmem_free(pin, sizeof(*pin));
213 }
214
215 static int
ti_gpio_read(device_t dev,void * priv,bool raw)216 ti_gpio_read(device_t dev, void *priv, bool raw)
217 {
218 struct ti_gpio_softc * const sc = device_private(dev);
219 struct ti_gpio_pin *pin = priv;
220 uint32_t data;
221 int val;
222
223 KASSERT(sc == pin->pin_sc);
224
225 const uint32_t data_mask = __BIT(pin->pin_nr);
226
227 /* No lock required for reads */
228 if (sc->sc_pinout[pin->pin_nr])
229 data = RD4(sc, GPIO_DATAOUT);
230 else
231 data = RD4(sc, GPIO_DATAIN);
232 val = __SHIFTOUT(data, data_mask);
233 if (!raw && pin->pin_actlo)
234 val = !val;
235
236 return val;
237 }
238
239 static void
ti_gpio_write(device_t dev,void * priv,int val,bool raw)240 ti_gpio_write(device_t dev, void *priv, int val, bool raw)
241 {
242 struct ti_gpio_softc * const sc = device_private(dev);
243 struct ti_gpio_pin *pin = priv;
244
245 KASSERT(sc == pin->pin_sc);
246
247 const uint32_t data_mask = __BIT(pin->pin_nr);
248
249 if (!raw && pin->pin_actlo)
250 val = !val;
251
252 const u_int data_reg = val ? GPIO_SETDATAOUT : GPIO_CLEARDATAOUT;
253
254 WR4(sc, data_reg, data_mask);
255 }
256
257 static struct fdtbus_gpio_controller_func ti_gpio_funcs = {
258 .acquire = ti_gpio_acquire,
259 .release = ti_gpio_release,
260 .read = ti_gpio_read,
261 .write = ti_gpio_write,
262 };
263
264 static void
ti_gpio_intr_disable(struct ti_gpio_softc * const sc,struct ti_gpio_intr * const intr)265 ti_gpio_intr_disable(struct ti_gpio_softc * const sc, struct ti_gpio_intr * const intr)
266 {
267 const u_int pin = intr->intr_pin;
268 const uint32_t pin_mask = __BIT(pin);
269 uint32_t val;
270
271 /* Disable interrupts */
272 if (sc->sc_type == TI_GPIO_OMAP3) {
273 val = RD4(sc, GPIO_IRQENABLE1);
274 WR4(sc, GPIO_IRQENABLE1, val & ~pin_mask);
275 } else {
276 WR4(sc, GPIO_IRQENABLE1_CLR, pin_mask);
277 }
278
279 intr->intr_func = NULL;
280 intr->intr_arg = NULL;
281 intr->intr_mpsafe = false;
282 }
283
284 static void *
ti_gpio_intr_establish(device_t dev,u_int * specifier,int ipl,int flags,int (* func)(void *),void * arg,const char * xname)285 ti_gpio_intr_establish(device_t dev, u_int *specifier, int ipl, int flags,
286 int (*func)(void *), void *arg, const char *xname)
287 {
288 struct ti_gpio_softc * const sc = device_private(dev);
289 uint32_t val;
290
291 /* 1st cell is the pin */
292 /* 2nd cell is flags */
293 const u_int pin = be32toh(specifier[0]);
294 const u_int type = be32toh(specifier[2]) & 0xf;
295
296 if (ipl != IPL_VM || pin >= __arraycount(sc->sc_pins))
297 return NULL;
298
299 /*
300 * Enabling both high and low level triggers will cause the GPIO
301 * controller to always assert the interrupt.
302 */
303 if ((type & (FDT_INTR_TYPE_LOW_LEVEL|FDT_INTR_TYPE_HIGH_LEVEL)) ==
304 (FDT_INTR_TYPE_LOW_LEVEL|FDT_INTR_TYPE_HIGH_LEVEL))
305 return NULL;
306
307 if (sc->sc_intr[pin].intr_func != NULL)
308 return NULL;
309
310 /* Set pin as input */
311 if (ti_gpio_ctl(sc, pin, GPIO_PIN_INPUT) != 0)
312 return NULL;
313
314 sc->sc_intr[pin].intr_pin = pin;
315 sc->sc_intr[pin].intr_func = func;
316 sc->sc_intr[pin].intr_arg = arg;
317 sc->sc_intr[pin].intr_mpsafe = (flags & FDT_INTR_MPSAFE) != 0;
318
319 const uint32_t pin_mask = __BIT(pin);
320
321 /* Configure triggers */
322 val = RD4(sc, GPIO_LEVELDETECT0);
323 if ((type & FDT_INTR_TYPE_LOW_LEVEL) != 0)
324 val |= pin_mask;
325 else
326 val &= ~pin_mask;
327 WR4(sc, GPIO_LEVELDETECT0, val);
328
329 val = RD4(sc, GPIO_LEVELDETECT1);
330 if ((type & FDT_INTR_TYPE_HIGH_LEVEL) != 0)
331 val |= pin_mask;
332 else
333 val &= ~pin_mask;
334 WR4(sc, GPIO_LEVELDETECT1, val);
335
336 val = RD4(sc, GPIO_RISINGDETECT);
337 if ((type & FDT_INTR_TYPE_POS_EDGE) != 0)
338 val |= pin_mask;
339 else
340 val &= ~pin_mask;
341 WR4(sc, GPIO_RISINGDETECT, val);
342
343 val = RD4(sc, GPIO_FALLINGDETECT);
344 if ((type & FDT_INTR_TYPE_NEG_EDGE) != 0)
345 val |= pin_mask;
346 else
347 val &= ~pin_mask;
348 WR4(sc, GPIO_FALLINGDETECT, val);
349
350 /* Enable interrupts */
351 if (sc->sc_type == TI_GPIO_OMAP3) {
352 val = RD4(sc, GPIO_IRQENABLE1);
353 WR4(sc, GPIO_IRQENABLE1, val | pin_mask);
354 } else {
355 WR4(sc, GPIO_IRQENABLE1_SET, pin_mask);
356 }
357
358 return &sc->sc_intr[pin];
359 }
360
361 static void
ti_gpio_intr_disestablish(device_t dev,void * ih)362 ti_gpio_intr_disestablish(device_t dev, void *ih)
363 {
364 struct ti_gpio_softc * const sc = device_private(dev);
365 struct ti_gpio_intr * const intr = ih;
366
367 ti_gpio_intr_disable(sc, intr);
368 }
369
370 static bool
ti_gpio_intrstr(device_t dev,u_int * specifier,char * buf,size_t buflen)371 ti_gpio_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen)
372 {
373 struct ti_gpio_softc * const sc = device_private(dev);
374
375 /* 1st cell is the pin */
376 /* 2nd cell is flags */
377 const u_int pin = be32toh(specifier[0]);
378
379 if (pin >= __arraycount(sc->sc_pins))
380 return false;
381
382 snprintf(buf, buflen, "%s pin %d", sc->sc_modname, pin);
383 return true;
384 }
385
386 static struct fdtbus_interrupt_controller_func ti_gpio_intrfuncs = {
387 .establish = ti_gpio_intr_establish,
388 .disestablish = ti_gpio_intr_disestablish,
389 .intrstr = ti_gpio_intrstr,
390 };
391
392 static int
ti_gpio_pin_read(void * priv,int pin)393 ti_gpio_pin_read(void *priv, int pin)
394 {
395 struct ti_gpio_softc * const sc = priv;
396 uint32_t data;
397 int val;
398
399 KASSERT(pin < __arraycount(sc->sc_pins));
400
401 const uint32_t data_mask = __BIT(pin);
402
403 data = RD4(sc, GPIO_DATAIN);
404 val = __SHIFTOUT(data, data_mask);
405
406 return val;
407 }
408
409 static void
ti_gpio_pin_write(void * priv,int pin,int val)410 ti_gpio_pin_write(void *priv, int pin, int val)
411 {
412 struct ti_gpio_softc * const sc = priv;
413
414 KASSERT(pin < __arraycount(sc->sc_pins));
415
416 const u_int data_reg = val ? GPIO_SETDATAOUT : GPIO_CLEARDATAOUT;
417 const uint32_t data_mask = __BIT(pin);
418
419 WR4(sc, data_reg, data_mask);
420 }
421
422 static void
ti_gpio_pin_ctl(void * priv,int pin,int flags)423 ti_gpio_pin_ctl(void *priv, int pin, int flags)
424 {
425 struct ti_gpio_softc * const sc = priv;
426
427 KASSERT(pin < __arraycount(sc->sc_pins));
428
429 mutex_enter(&sc->sc_lock);
430 ti_gpio_ctl(sc, pin, flags);
431 mutex_exit(&sc->sc_lock);
432 }
433
434 static void *
ti_gpio_gp_intr_establish(void * vsc,int pin,int ipl,int irqmode,int (* func)(void *),void * arg)435 ti_gpio_gp_intr_establish(void *vsc, int pin, int ipl, int irqmode,
436 int (*func)(void *), void *arg)
437 {
438 struct ti_gpio_softc * const sc = vsc;
439 uint32_t val;
440
441 if (ipl != IPL_VM || pin < 0 || pin >= __arraycount(sc->sc_pins))
442 return NULL;
443
444 if (sc->sc_intr[pin].intr_func != NULL)
445 return NULL;
446
447 /*
448 * Enabling both high and low level triggers will cause the GPIO
449 * controller to always assert the interrupt.
450 */
451 if ((irqmode & (GPIO_INTR_LOW_LEVEL|GPIO_INTR_HIGH_LEVEL)) ==
452 (GPIO_INTR_LOW_LEVEL|GPIO_INTR_HIGH_LEVEL))
453 return NULL;
454
455 /* Set pin as input */
456 mutex_enter(&sc->sc_lock);
457 if (ti_gpio_ctl(sc, pin, GPIO_PIN_INPUT) != 0) {
458 mutex_exit(&sc->sc_lock);
459 return NULL;
460 }
461
462 sc->sc_intr[pin].intr_pin = pin;
463 sc->sc_intr[pin].intr_func = func;
464 sc->sc_intr[pin].intr_arg = arg;
465 sc->sc_intr[pin].intr_mpsafe = (irqmode & GPIO_INTR_MPSAFE) != 0;
466
467 const uint32_t pin_mask = __BIT(pin);
468
469 /* Configure triggers */
470 val = RD4(sc, GPIO_LEVELDETECT0);
471 if ((irqmode & GPIO_INTR_LOW_LEVEL) != 0)
472 val |= pin_mask;
473 else
474 val &= ~pin_mask;
475 WR4(sc, GPIO_LEVELDETECT0, val);
476
477 val = RD4(sc, GPIO_LEVELDETECT1);
478 if ((irqmode & GPIO_INTR_HIGH_LEVEL) != 0)
479 val |= pin_mask;
480 else
481 val &= ~pin_mask;
482 WR4(sc, GPIO_LEVELDETECT1, val);
483
484 val = RD4(sc, GPIO_RISINGDETECT);
485 if ((irqmode & GPIO_INTR_POS_EDGE) != 0 ||
486 (irqmode & GPIO_INTR_DOUBLE_EDGE) != 0)
487 val |= pin_mask;
488 else
489 val &= ~pin_mask;
490 WR4(sc, GPIO_RISINGDETECT, val);
491
492 val = RD4(sc, GPIO_FALLINGDETECT);
493 if ((irqmode & GPIO_INTR_NEG_EDGE) != 0 ||
494 (irqmode & GPIO_INTR_DOUBLE_EDGE) != 0)
495 val |= pin_mask;
496 else
497 val &= ~pin_mask;
498 WR4(sc, GPIO_FALLINGDETECT, val);
499
500 /* Enable interrupts */
501 if (sc->sc_type == TI_GPIO_OMAP3) {
502 val = RD4(sc, GPIO_IRQENABLE1);
503 WR4(sc, GPIO_IRQENABLE1, val | pin_mask);
504 } else {
505 WR4(sc, GPIO_IRQENABLE1_SET, pin_mask);
506 }
507
508 mutex_exit(&sc->sc_lock);
509
510 return &sc->sc_intr[pin];
511 }
512
513 static void
ti_gpio_gp_intr_disestablish(void * vsc,void * ih)514 ti_gpio_gp_intr_disestablish(void *vsc, void *ih)
515 {
516 struct ti_gpio_softc * const sc = vsc;
517 struct ti_gpio_intr * const intr = ih;
518
519 ti_gpio_intr_disable(sc, intr);
520 }
521
522 static bool
ti_gpio_gp_intrstr(void * vsc,int pin,int irqmode,char * buf,size_t buflen)523 ti_gpio_gp_intrstr(void *vsc, int pin, int irqmode, char *buf, size_t buflen)
524 {
525 struct ti_gpio_softc * const sc = vsc;
526
527 if (pin < 0 || pin >= TI_GPIO_NPINS)
528 return false;
529
530 snprintf(buf, buflen, "%s pin %d", sc->sc_modname, pin);
531 return true;
532 }
533
534 static void
ti_gpio_attach_ports(struct ti_gpio_softc * sc)535 ti_gpio_attach_ports(struct ti_gpio_softc *sc)
536 {
537 struct gpio_chipset_tag *gp = &sc->sc_gp;
538 struct gpiobus_attach_args gba;
539 u_int pin;
540
541 gp->gp_cookie = sc;
542 gp->gp_pin_read = ti_gpio_pin_read;
543 gp->gp_pin_write = ti_gpio_pin_write;
544 gp->gp_pin_ctl = ti_gpio_pin_ctl;
545 gp->gp_intr_establish = ti_gpio_gp_intr_establish;
546 gp->gp_intr_disestablish = ti_gpio_gp_intr_disestablish;
547 gp->gp_intr_str = ti_gpio_gp_intrstr;
548
549 for (pin = 0; pin < __arraycount(sc->sc_pins); pin++) {
550 sc->sc_pins[pin].pin_num = pin;
551 sc->sc_pins[pin].pin_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT;
552 sc->sc_pins[pin].pin_intrcaps =
553 GPIO_INTR_POS_EDGE | GPIO_INTR_NEG_EDGE |
554 GPIO_INTR_DOUBLE_EDGE | GPIO_INTR_HIGH_LEVEL |
555 GPIO_INTR_LOW_LEVEL | GPIO_INTR_MPSAFE;
556 sc->sc_pins[pin].pin_state = ti_gpio_pin_read(sc, pin);
557 }
558
559 memset(&gba, 0, sizeof(gba));
560 gba.gba_gc = gp;
561 gba.gba_pins = sc->sc_pins;
562 gba.gba_npins = __arraycount(sc->sc_pins);
563 sc->sc_gpiodev = config_found(sc->sc_dev, &gba, NULL, CFARGS_NONE);
564 }
565
566 static int
ti_gpio_intr(void * priv)567 ti_gpio_intr(void *priv)
568 {
569 struct ti_gpio_softc * const sc = priv;
570 uint32_t status;
571 u_int bit;
572 int rv = 0;
573
574 status = RD4(sc, GPIO_IRQSTATUS1);
575 WR4(sc, GPIO_IRQSTATUS1, status);
576
577 while ((bit = ffs32(status)) != 0) {
578 const u_int pin = bit - 1;
579 const uint32_t pin_mask = __BIT(pin);
580 struct ti_gpio_intr *intr = &sc->sc_intr[pin];
581 status &= ~pin_mask;
582 if (intr->intr_func == NULL)
583 continue;
584 if (!intr->intr_mpsafe)
585 KERNEL_LOCK(1, curlwp);
586 rv |= intr->intr_func(intr->intr_arg);
587 if (!intr->intr_mpsafe)
588 KERNEL_UNLOCK_ONE(curlwp);
589 }
590
591 return rv;
592 }
593
594 static int
ti_gpio_match(device_t parent,cfdata_t cf,void * aux)595 ti_gpio_match(device_t parent, cfdata_t cf, void *aux)
596 {
597 struct fdt_attach_args * const faa = aux;
598
599 return of_compatible_match(faa->faa_phandle, compat_data);
600 }
601
602 static void
ti_gpio_attach(device_t parent,device_t self,void * aux)603 ti_gpio_attach(device_t parent, device_t self, void *aux)
604 {
605 struct ti_gpio_softc * const sc = device_private(self);
606 struct fdt_attach_args * const faa = aux;
607 const int phandle = faa->faa_phandle;
608 char intrstr[128];
609 bus_addr_t addr;
610 bus_size_t size;
611
612 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
613 aprint_error(": couldn't get registers\n");
614 return;
615 }
616 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
617 aprint_error(": couldn't decode interrupt\n");
618 return;
619 }
620 if (ti_prcm_enable_hwmod(phandle, 0) != 0) {
621 aprint_error(": couldn't enable module\n");
622 return;
623 }
624
625 sc->sc_dev = self;
626 sc->sc_bst = faa->faa_bst;
627 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
628 aprint_error(": couldn't map registers\n");
629 return;
630 }
631 sc->sc_type = of_compatible_lookup(phandle, compat_data)->value;
632 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM);
633
634 sc->sc_modname = fdtbus_get_string(phandle, "ti,hwmods");
635 if (sc->sc_modname == NULL)
636 sc->sc_modname = fdtbus_get_string(OF_parent(phandle), "ti,hwmods");
637 if (sc->sc_modname == NULL)
638 sc->sc_modname = kmem_asprintf("gpio@%" PRIxBUSADDR, addr);
639
640 aprint_naive("\n");
641 aprint_normal(": GPIO (%s)\n", sc->sc_modname);
642
643 fdtbus_register_gpio_controller(self, phandle, &ti_gpio_funcs);
644
645 ti_gpio_attach_ports(sc);
646
647 sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_VM,
648 FDT_INTR_MPSAFE, ti_gpio_intr, sc, device_xname(self));
649 if (sc->sc_ih == NULL) {
650 aprint_error_dev(self, "failed to establish interrupt on %s\n",
651 intrstr);
652 return;
653 }
654 aprint_normal_dev(self, "interrupting on %s\n", intrstr);
655 fdtbus_register_interrupt_controller(self, phandle, &ti_gpio_intrfuncs);
656 }
657