1 /* $NetBSD: tegra_pmcreg.h,v 1.5 2015/10/17 21:14:49 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _ARM_TEGRA_PMCREG_H 30 #define _ARM_TEGRA_PMCREG_H 31 32 #define PMC_CNTRL_0_REG 0x00 33 34 #define PMC_CNTRL_0_CPUPWRGOOD_SEL __BITS(21,20) 35 #define PMC_CNTRL_0_CPUPWRGOOD_EN __BIT(19) 36 #define PMC_CNTRL_0_FUSE_OVERRIDE __BIT(18) 37 #define PMC_CNTRL_0_INTR_POLARITY __BIT(17) 38 #define PMC_CNTRL_0_CPUPWRREG_OE __BIT(16) 39 #define PMC_CNTRL_0_CPUPWRREG_POLARITY __BIT(15) 40 #define PMC_CNTRL_0_SIDE_EFFECT_LP0 __BIT(14) 41 #define PMC_CNTRL_0_AOINIT __BIT(13) 42 #define PMC_CNTRL_0_PWRGATE_DIS __BIT(12) 43 #define PMC_CNTRL_0_SYSCLK_OE __BIT(11) 44 #define PMC_CNTRL_0_SYSCLK_POLARITY __BIT(10) 45 #define PMC_CNTRL_0_PWRREQ_OE __BIT(9) 46 #define PMC_CNTRL_0_PWRREQ_POLARITY __BIT(8) 47 #define PMC_CNTRL_0_BLINK_EN __BIT(7) 48 #define PMC_CNTRL_0_GLITCHDET_DIS __BIT(6) 49 #define PMC_CNTRL_0_LATCHWAKE_EN __BIT(5) 50 #define PMC_CNTRL_0_MAIN_RST __BIT(4) 51 #define PMC_CNTRL_0_KBC_RST __BIT(3) 52 #define PMC_CNTRL_0_RTC_RST __BIT(2) 53 #define PMC_CNTRL_0_RTC_CLK_DIS __BIT(1) 54 #define PMC_CNTRL_0_KBC_CLK_DIS __BIT(0) 55 56 #define PMC_PWRGATE_TOGGLE_0_REG 0x30 57 58 #define PMC_PWRGATE_TOGGLE_0_START __BIT(8) 59 #define PMC_PWRGATE_TOGGLE_0_PARTID __BITS(4,0) 60 61 #define PMC_REMOVE_CLAMPING_CMD_0_REG 0x34 62 63 #define PMC_PWRGATE_STATUS_0_REG 0x38 64 65 #define PMC_PARTID_IRAM 24 66 #define PMC_PARTID_VIC 23 67 #define PMC_PARTID_XUSBC 22 68 #define PMC_PARTID_XUSBB 21 69 #define PMC_PARTID_XUSBA 20 70 #define PMC_PARTID_DISB 19 71 #define PMC_PARTID_DIS 18 72 #define PMC_PARTID_SOR 17 73 #define PMC_PARTID_C1NC 16 74 #define PMC_PARTID_C0NC 15 75 #define PMC_PARTID_CE0 14 76 #define PMC_PARTID_A9LP 12 77 #define PMC_PARTID_CPU3 11 78 #define PMC_PARTID_CPU2 10 79 #define PMC_PARTID_CPU1 9 80 #define PMC_PARTID_SAX 8 81 #define PMC_PARTID_HEG 7 82 #define PMC_PARTID_MPE 6 83 #define PMC_PARTID_L2C 5 84 #define PMC_PARTID_VDE 4 85 #define PMC_PARTID_PCX 3 86 #define PMC_PARTID_VE 2 87 #define PMC_PARTID_TD 1 88 #define PMC_PARTID_CPU0 0 89 90 #define PMC_IO_DPD_STATUS_REG 0x1bc 91 #define PMC_IO_DPD_STATUS_HDMI __BIT(28) 92 93 #define PMC_IO_DPD2_STATUS_REG 0x1c4 94 #define PMC_IO_DPD2_STATUS_HV __BIT(6) 95 96 #define PMC_GPU_RG_CNTRL_REG 0x2d4 97 #define PMC_GPU_RG_CNTRL_RAIL_CLAMP __BIT(0) 98 99 #endif /* _ARM_TEGRA_PMCREG_H */ 100